CN101106111B - 集成电路器件封装体及其装配方法 - Google Patents

集成电路器件封装体及其装配方法 Download PDF

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Publication number
CN101106111B
CN101106111B CN2007101040241A CN200710104024A CN101106111B CN 101106111 B CN101106111 B CN 101106111B CN 2007101040241 A CN2007101040241 A CN 2007101040241A CN 200710104024 A CN200710104024 A CN 200710104024A CN 101106111 B CN101106111 B CN 101106111B
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crystal grain
lead
sealing cap
wire
lead frame
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CN101106111A (zh
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萨姆·齐昆·赵
雷泽厄·拉曼·卡恩
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Avago Technologies General IP Singapore Pte Ltd
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Zyray Wireless Inc
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Abstract

本发明涉及在集成电路(IC)封装体中提高散热性能和电磁干扰屏蔽性能的方法和装置。晶粒向上或晶粒向下的封装体包括IC晶粒、晶粒托盘、与晶粒托盘相连且其内部形成空腔的散热封帽，以及晶粒托盘周围的一排或多排外部引线。引线并未完全露出到密围结构之外。晶粒托盘和散热封帽构成完全密封IC晶粒的密围结构，同时可屏蔽IC晶粒发出或向IC晶粒辐射的电磁干扰。该密围结构还可将IC晶粒在工作期间产生的热量向外散发。

Description

集成电路器件封装体及其装配方法
技术领域
本发明涉及集成电路(IC)器件封装技术，更具体地说，涉及IC器件无引线封装中的提高散热性能和电磁干扰(EMI)屏蔽性能的装置及方法。
背景技术
集成电路(IC)半导体芯片或晶粒(die)一般封装在封装体内或其上，该封装体与印刷电路板(PCB)或印刷线路板(PWB)相连。通常将在封装体装配过程中用于贴装半导体晶粒的结构框架称为导线架(leadframe)，其一般由金属或其它导电材料制成。导线架广泛地应用于IC封装中，作为IC晶粒的载体并可作为晶粒和PCB/PWB电子电路之间的互连装置。导线架包括用于安装多个IC晶粒的位置。晶粒连接到导线架之后，采用金属线将IC晶粒的接合焊盘(bond pad)连接到导线架的接合焊盘，接合焊盘有时也称为接合手指(bond finger)。接着，用塑封料(molding compound)，如热固性环氧塑料，将导线架中晶粒所在的位置密封。塑封之后，将密封好的芯片从导线架的支撑框上机械地分离出。如果导线架的一部分从封装体中露出，则该封装称为有引线封装。相反，如果封装体引线并未从导线架覆盖区(footprint)露出，则该封装称为无引线导线架式封装或简称为无引线封装。在无引线封装中，直线引线或弯曲引线向下和/或往内弯曲，以安装在PCB/PWB基板上。
一种无引线导线架式封装体中带有外露的晶粒托盘(die attach pad，简称为DAP)。该外露DAP具有与晶粒贴装表面相对的可焊接外表面，用于与PCB/PWB焊接在一起。另一种可选的无引线封装称为薄体阵列塑料封装(thinarray plastic package，简称为TAPP)，该封装体具有多排用于线焊(wire bonding)的外部引线。
目前业内已开发了各种带有或不带有导线架的封装体，并且电气工业联盟 (electronic industries alliance，简称为EIA)、电子器件工业联合委员会(JointElectron Device Engineering Council，简称为JEDEC)和日本电气工业联盟(electronic industries alliance of Japan，简称为EIAJ)已针对各封装系列的要点(outlines)制定了标准。
然而，目前商用的无引线封装，其散热性能有限且EMI屏蔽较差。因此，有必要在集成电路封装中降低EMI敏感性，同时提高散热和电性能。另外，集成电路封装中还希望提高环境防护性能。
发明内容
本发明涉及一种在IC封装中增强散热性能和EMI屏蔽的方法和装置。
本发明一方面提供了一种IC器件封装体，其中包括具有彼此相对的第一和第二表面的封帽(cap)。封帽第二表面的第一部分内部形成一空腔(cavity)。封帽第二表面的平面第二部分连接到DAP。DAP包括中心部(central portion)以及连接到DAP中心部的多个连接杆(tie bar)。IC晶粒贴装在DAP的中心部。封帽和DAP形成密围结构，以将IC晶粒完全包围。
本发明另一方面提出了一种IC器件封装的装配方法。形成专用于无引线封装的导线架。将IC晶粒连接到导线架的晶粒托盘的中心部。通过焊线(wirebond)连接IC晶粒和导线架。将封帽安装到导线架上。封帽的第二表面内包括空腔。封帽和DAP形成密围结构，以将IC晶粒完全包围。采用塑封材料(molding material)密封IC晶粒。切除(trim)导线架的周界支撑环。将引线的一部分打弯，以便于引线到电路板的连接。在工作过程中，该密围结构将IC晶粒产生的热量散发出去。此外，该密围结构可屏蔽IC晶粒发出的EMI，同时可屏蔽封装体外部向IC晶粒辐射的EMI。
根据本发明的一方面，提供一种集成电路(IC)器件封装体，包括：
带有接合焊盘(bond pad)的IC晶粒；
包围IC晶粒的密围结构，其包括：
带有平坦中心部的晶粒托盘，所述中心部具有彼此相对的第一和第二表面；与晶粒托盘中心部相连且从中心部向外延伸的多个连接杆(tie bar)；其中IC晶粒贴装在晶粒托盘中心部的第一表面；以及，
带有空腔和围绕该空腔的平整边缘(rim)的封帽，当封帽边缘连接到晶粒托盘时，空腔面向IC晶粒，从而将IC晶粒包围；
带有线焊用引线手指的多条引线，所述引线围绕晶粒托盘周围至少排列一排；以及
塑封材料，用于密封IC晶粒且至少部分地填充所述空腔；
其中，所述晶粒托盘和多条引线连接在一起形成导线架，其中有一个或多个周界支撑环或堤坝在结构上连接各引线；所述多个连接杆中有至少一个连接杆要宽于所述多个连接杆中的其它连接杆，除四个角外，其还可位于沿着晶粒托盘中心部的其它位置，且连接杆上可熔接任意数量的引线。
优选地，所述封装体为晶粒朝上(die-up)或晶粒朝下(die-down)配置。
优选地，所述密围结构将IC晶粒工作期间产生的热量向外散发。
优选地，所述封帽朝向IC晶粒的内表面连接有导热块。
优选地，所述密围结构屏蔽IC晶粒发出的电磁干扰，同时屏蔽封装体外部向IC晶粒辐射的电磁干扰。
优选地，所述晶粒托盘和多条引线连接在一起形成导线架，其中有一个或多个周界支撑环或堤坝(dam bar)在结构上连接各引线。
优选地，所述引线以一排以上的阵列方式排列。
优选地，其特征在于，所述封装体进一步包括一个或多个与晶粒托盘周围的连接杆相连的内插导电环(interposer conducting ring)。
优选地，所述晶粒托盘、内插环(interposer ring)和多条引线连接在一起形成导线架，其中有一个或多个周界支撑环或堤坝在结构上连接各引线。
优选地，所述封帽边缘包括从包围IC晶粒的空腔向外扩伸的完全平坦的周边(lip)部分。
优选地，所述封帽与至少一条引线电、热接触。
优选地，所述封帽与多条引线中的任意引线电绝缘。
优选地，所述封帽的平坦边缘的至少一部分被绝缘材料覆盖。
优选地，与所述封帽相连的晶粒托盘的至少一部分被绝缘材料覆盖。
优选地，所述多个连接杆中有至少一个连接杆要宽于所述多个连接杆中的其它连接杆。
优选地，所述多条引线中有至少一条引线要宽于所述多条引线中的其它引线。
优选地，所述封帽与至少一个连接杆电、热接触。
优选地，所述多个连接杆和所述多条引线位于第一平面(plane)。
优选地，所述多个连接杆位于第一平面(plane)，而所述多条引线位于第二平面。
优选地，所述封帽的平坦边缘部分通过导热和导电粘结剂(adhesive)连接到晶粒托盘。
优选地，所述封装体进一步包括：
晶粒托盘上敷有至少一个导电镀层区(plated area)，且所述导电镀层区与所述封帽的平坦边缘部分相接触。
优选地，所述封帽与所述晶粒托盘电绝缘。
优选地，所述封帽连接到地电位(ground potential)。
优选地，所述封帽连接到电源电位(power potential)。
优选地，所述至少一个突出部为圆锥形或平截头形(frustum)或横向细条形(laterally elongated shape)。
优选地，所述突出部位于所述平坦边缘部分的角上。
优选地，所述至少一个对应匹配座有通孔、凹孔或边缘切口的配置方式。
优选地，所述至少一个突出部和至少一个对应匹配座被配置为便于将封帽在预定方向上连接到晶粒托盘。
优选地，所述封装体进一步包括：
至少一条焊线，用于将IC晶粒上的至少一个接合焊盘连接到所述密围结构，由此所述密围结构连接到一个电位。
优选地，所述至少一个接合焊盘为接地焊盘(ground pad)，由此所述密围结构连接到地电位。
优选地，所述封帽具有背向背向空腔的外表面，其中所述外表面的第一部分被塑封材料覆盖，而所述封帽外表面的第二部分未被塑封材料覆盖。
优选地，所述塑封材料进一步密封背向空腔的封帽外表面。
优选地，所述封帽具有背向空腔的外表面，其中所述封帽进一步包括：
穿透所述封帽的至少一个开口，所述开口在外表面开设并连接到空腔。
优选地，所述穿透封帽的至少一个开口被配置为便于塑封材料流入空腔。
优选地，所述穿透封帽的至少一个开口被配置为便于释放密封结构内部的空气压力。
优选地，所述封帽的周界尺寸与外排引线包围的平坦区域的周界尺寸完全一致。
优选地，所述封帽的周界尺寸小于外排引线包围的平坦区域的周界尺寸。
优选地，所述封帽的周界尺寸大于外排引线包围的平坦区域的周界尺寸。
优选地，所述封帽具有背向空腔的外表面，进一步包括：
连接在封帽外表面的散热器。
优选地，所述封帽具有背向空腔的外表面，其中封帽外表面被配置为连接到基板上，所述基板包括印刷电路板(PCB)和印刷线路板(PWB)。
优选地，所述封装体进步一步包括用于将封帽外表面连接到基板上的导热和导电粘结剂。
优选地，所述晶粒托盘的中心部的第二表面暴露在外，以连接到基板上，所述基板包括印刷电路板和印刷线路板的。
优选地，所述封装体进一步包括用于将晶粒托盘连接到基板上的导热和导电粘结剂。
优选地，所述封装体进一步包括：
散热块，其第一表面连接到晶粒托盘中心部的外露第二表面，其第二表面被配置为连接到基板上，所述基板包括印刷电路板和印刷线路板。
优选地，所述密围结构和塑封材料为IC晶粒提供环境防护。
优选地，所述密围结构和塑封材料提供减缓机械冲击和摇动。
优选地，所述封帽和晶粒托盘由相同材料制成，所述材料包括金属、金属合金、铁磁材料和金属化聚合体在内。
优选地，所述封帽和晶粒托盘由不同材料制成。
根据本发明的一方面，提供一种装配集成电路(IC)器件封装体的方法，其特征在于，其中包括：
(a)采用导电板料形成导线架，该导线架包括：
位于其中部的晶粒托盘，所述晶粒托盘包括带有彼此相对的第一和第二表面的平坦中心部，以及与所述中心部相连并从其中向外延伸的多个连接杆；
围绕晶粒托盘周围排列成一排或多排的多条引线，其中连接杆将晶粒托盘连接到一条或多条引线；及
对应于每排引线的周界支撑环，其将各引线横向连接在一起；
(b)将IC晶粒贴装到晶粒托盘的中心部；
(c)通过形成焊线将IC晶粒的接合焊盘连接到导线架；
(d)连接封帽，该封帽具有面向导线架的空腔，将围绕着空腔的封帽的平坦边缘部分连接到导线架上，使封帽和导线架形成密围结构，以将IC晶粒包围；其中包括将封帽平整边缘部分伸出的至少一个突出部插入晶粒托盘连接杆表面形成的对应于至少一个突出部的至少一个匹配座中；
(e)使用塑封材料至少将IC晶粒密封；及
(f)从导线架上切除周界支撑环。
优选地，同时执行步骤(d)和(e)，并进一步包括：
(g1)在步骤(d)之前，将封帽和导线架放到模具中。
优选地，所述方法进一步包括：
(g2)在步骤(d)之前，在导线架的部分表面涂敷导热导电粘结剂。
优选地，所述方法进一步包括：
(g3)在步骤(d)之前，在导线架的部分表面涂敷导电材料。
优选地，步骤(d)包括：
将封帽的平坦边缘部分上的突出部连接到导线架上的对应匹配座中，从而大大提高封帽和导线架的连接性。
优选地，步骤(c)包括：
连接IC晶粒焊盘和导线架之间的焊线，由此将所述密围结构电连接到某一电位。
优选地，所述焊盘为接地焊盘，由此将所述密围结构电连接到地电位。
优选地，步骤(e)进一步包括：
利用塑封材料来密封封帽外表面的第一部分，而封帽外表面的第二部分未被塑封材料覆盖。
优选地，步骤(e)进一步包括：
利用塑封材料来密封封帽的外表面。
优选地，步骤(e)进一步包括：
利用塑封材料密封导线架的一部分，而导线架表面暴露在外的部分将与封帽相连。
优选地，该方法进一步包括：
(g4)形成穿透封帽的开口，该开口开设在封帽的外表面和空腔表面。
优选地，步骤(e)包括：
通过所述开口将塑封材料注入到空腔中。
优选地，该方法进一步包括：
允许通过开口释放密围结构内部的空气压力。
优选地，该方法进一步包括：
(g5)将散热器连接到封帽外表面。
优选地，所述密围结构提供了下述一项或多项功能：在IC晶粒工作期间向外扩散来自IC晶粒的热量、屏蔽IC晶粒发出的电磁干扰(EMI)并屏蔽封装体外部向IC晶粒辐射的EMI、为IC晶粒提供环境防护、以及减缓机械冲击和摇动。
优选地，步骤(a)进一步包括：
形成一个或多个连接到晶粒托盘的连接杆的导体环。
从下面对本发明的具体描述中可更清楚地了解其各种优点和创新特征。请注意，概述和摘要部分提出了一个或多个典型实施例，但并未说明发明者所预 期的所有实施例。
附图说明
下面将结合附图及实施例对本发明作进一步说明，附图可进一步解释本发明的原理，使本领域技术人员能更好地理解和使用本发明。
图1A、1B、2A、2B、3A和3B是各种用于提高散热性能的DAP外露的IC封装体的横截面视图和仰视图；
图4是球栅阵列(BGA)IC封装的示意图；
图5A-5F是根据本发明实施例的封帽的示意图；
图6A-6C是根据本发明实施例的导线架的俯视图；
图7A-7F是根据本发明实施例的带有集成散热器封帽的IC封装体的横截面视图；
图8是根据本发明实施例的导线架式IC封装体的装配步骤流程图；
图9A-9D是根据本发明实施例，在装配过程中导线架式IC封装体的俯视图；
图9E-9G是根据本发明实施例，在装配过程中导线架式IC封装体的侧视图；
图10是不同于图8所示的导线架式IC封装体的另一装配步骤流程图；
图11A-11C示出了密封后再将封帽连接到导线架的示意图。
以下将参照附图并结合实施例对本发明进行详细描述。附图中，同一个附图标记在各幅附图中用于表示相同的或功能相似的部件。另外，附图标记最左边的数字用于标识该附图标记首次出现的那幅附图的编号。
具体实施方式
本申请公开了结合有本发明特征的一个或多个实施例。所公开的实施例仅仅是对本发明的举例，本发明的范围不局限于所公开的实施例，而由本申请的权利要求界定。
应注意的是，本说明书中提及的“一个实施例”、“一实施例”、“示例性实 施例”等等指的是所描述的实施例可能包括某特定特征、结构或特点，但是并不是每一个实施例都必定包括该特定特征、结构或特点。此外，这些短语不一定指的是同一个实施例。还有，当结合某一实施例描述某特定特征、结构或特点时，无论是否明确说明，本领域的技术人员应当知悉，这些特定特征、结构或特点也可以结合到其它实施例中。
概述
本发明涉及在集成电路(IC)封装中提高散热性能和电磁干扰(EMI)屏蔽性能的方法和装置。IC晶粒贴装在DAP上。IC晶粒可按晶粒朝上(die-up)的方式贴装，即晶粒连接到DAP中远离基板(如PCB)的那面上。IC晶粒也可按晶粒朝下(die-down)的方式安装，即晶粒贴装在DAP朝向基板的那面上。采用焊线(wire bond)将晶粒上的接合焊盘(bond pad)电连接到DAP周围的引线手指(lead finger)上。请注意，与焊线相连的引线根部区域(base region)称为“引线手指(lead finger)”。
在无引线IC封装中，引线并未从其各自根部区域(base region)完全伸出。引线向下弯曲，以便安装到PCB/PWB上，进而得到封装后IC晶粒的致密足迹(compact footprint)，有时也称为“IC芯片”。这种类型的封装称为“芯片级封装(Chip Scale Package)”或CSP。CSP可以基于导线架，其中DAP和引线连接在一起形成导线架，且有一个或多个周界支撑环(perimetersupport ring)或堤坝(dam bar)在结构上将各引线连接在一起。这种类型的封装称为无引线导线架式封装。无引线导线架式封装的典型实例包括无引线塑料芯片载体(Leadless Plastic Chip Carrier或LPCC)和微型导线架封装(MicroLeadframe Package或MLP)，其中一般只有单排外围端子(peripheralterminal)。
非导线架式CSP的一个实例为TAPP封装，其中有多排用于焊线的外部引线。TAPP封装采用虑及多排外部输出以及接地或电源内插环的独特过程来装配。该封装体非常薄，平均厚度为0.7mm，且输入/输出(I/O)密度与精密球栅阵列(fine pitch Ball Grid Array，简称为fpBGA)封装相当。请注意，可采用 适当设计的带有多排外部引线的导线架来装配TAPP类型封装的修改版本，其中每排引线有一个对应的周界支撑环。还可有一个或多个内插(interposer)接地/电源环连接到DAP。
金属封帽与DAP相连接(如，电连接、结构连接和/或热连接)，形成密围结构。采用或不采用导热和/或导电粘结剂(诸如含有金属颗粒或薄片的焊料或环氧树脂)均可实现连接。在一实施例中，封帽与贴装在导线架上的一条或多条引线上的连接杆相连接。连接杆焊接或熔接到引线上。在另一实施例中，封帽直接连接在引线上。在又一实施例中，封帽连接在DAP上。封帽可连接于DAP、引线和连接杆中的任意一种、二种或三种之上。封帽上的突出部(tab)与一个或多个熔接引线和/或连接杆上的匹配座(matching receptacle)紧密配合，以改善连接强度和整个结构的强度。
由封帽和导线架形成的密围结构近似于等电位表面或法拉第笼(FaradayCage)，其包围着晶粒和互连导线。密围结构材料一般是非常好的导热体且具有相对较强的刚度(例如铜或铜合金C151)。这种密围结构可以改善EMI屏蔽性能、改善IC晶粒的散热性能、增强封装刚性、提高对环境(例如机械震动、摇动、冲撞、压力、温度、湿度、腐蚀等)的防护性能。
在一实施例中，晶粒和焊线密封在塑封材料中，以提高对环境的防护性能。塑封料可以将封帽全部覆盖住。在另一实施例中，封帽被塑封材料部分覆盖，或者也可以不覆盖。
集成电路封装实例
在C.A.HARPER，Electronic Packaging and Interconnection Handbook，3rd edition，McGraw-Hill，NewYork，pp.7.61-7.67，2000中讨论了不同系列的基于导线架的有引线封装和无引线封装，在本申请中全文引用。
一般用塑料塑封材料密封的导线架式封装体(其中一个实例就是塑料方形扁平封装(Plastic Quad Flat Pack，简称为PQFP))表现出较差的散热性能，因为在DAP和引线之间没有连续的散热路径。IC晶粒的活动表面所产生的热量主要通过封装体的上表面和下表面散出。导线架将部分热量传导到与封装体 相连的PCB/PWB。密封IC晶粒的塑封材料通过各种对流路径或辐射路径将部分热量传送到周围环境中。一般塑封材料的导热系数较低，如介于0.2～0.9W/m.K之间或左右。因此，传统导线架式封装中的塑封材料就成了将热量从晶粒散出到封装体外表面和热引线的主要瓶颈。
通过将DAP暴露在塑封材料的底面之外，可以改进有引线和无引线导线架式封装体的散热性能。
图1A和1B分别是带有外露DAP的有引线PQFP封装体100的侧视图和仰视图。封装体100包括IC晶粒150、DAP 140、焊线130、塑封材料120、粘结剂170和封装引线180。DAP 140和封装引线180可作为导线架的一部分。利用粘结剂170将IC晶粒150贴装在DAP 140上。塑封材料120密封IC晶粒150和焊线130。焊线130将IC晶粒150上的接合焊盘(bond pad)连接到封装体引线180。如图1所示，其它焊线130位于IC晶粒和DAP 140之间，以及位于DAP 140和引线180之间。DAP 140至少有一部分外表面暴露在外。包覆在DAP 140外露表面的导热焊料/粘结剂将封装体100接合到PCB/PWB 160。PCB/PWB 160作为该封装体的散热器，因为在晶粒150活动表面产生的热量将散出到具有极低热阻的PCB/PWB 160中。这种类型的封装称为“托盘外露薄体四方扁平封装(Exposed Pad Thin Quad Flat Pack，简称为eTQFP)”。
图2A和2B分别是带有外露DAP的无引线导线架式封装体200的侧视图和仰视图。封装体200包括IC晶粒150、DAP 140、焊线130、塑封材料120、粘结剂170和封装引线280。DAP 140和封装引线280可作为导线架的一部分。利用粘结剂170将IC晶粒150贴装在DAP 140上。塑封材料120密封IC晶粒150和焊线130。包覆在DAP 140的至少一部分外表面的导热焊料/粘结剂将封装体200接合到PCB/PWB 160。这种类型的封装称为“微型导线架封装(MicroLeadframe Package，简称为MLP)”，还可称为“四方扁平无引线”或QFN封装，因为封装体导线280并未露在封装体外面。封装引线280在DAP 140四周。一般地，在无引线封装中，如封装体200，只有一排外部引线。焊线130将引线280连接到IC晶粒150的接合焊盘(bond pad)。DAP 140可连接到地电位(接地)或特定电位。
图3A和3B分别是带有外露DAP 140的无引线TAPP型封装体300的侧视图和仰视图。封装体300包括IC晶粒150、DAP 140、焊线130、塑封材料120、粘结剂170、内插环(interposer ring)390和封装引线385。包覆在DAP 140外表面的导热焊料或粘结剂将封装体300接合到PCB/PWB 160。引线385以多于一排的方式围绕在DAP 140四周，形成了输出引线阵列。焊线130将引线385连接到IC晶粒150的对应接合焊盘(bond pad)。多排封装引线增强了封装电路的I/O密度。此外，封装体中可包括一个或多个内插环390。内插环390一般连接到地电位(接地)。请注意，内插环390并不是必须接地，它也可连接到特定电位。TAPP封装具有独特的装配过程。不过，如前所述，如果导线架设计修改为包括内插环和多排外部引线，则TAPP类型的封装可以基于导线架的装配过程。
尽管上述封装在散热性能方面有所增强，但它们的电磁干扰(EMI)屏蔽性能仍然较差。导体中承载的电流在发生变化时将产生电磁波辐射。这些电磁波以光速在空间传播，如果这些电磁波是不希望有的，则称为EMI。电流变化率相对较低时，将辐射出少量的长波低频电磁波。而当电流变化率相对较高时，将辐射出大量的短波高频电磁波。这些不希望有的高频电磁辐射有时称为射频干扰(RFI)，但为了简便起见，本申请中将所有不希望有的电磁辐射都称为EMI，而不管其频率高低。
IC晶粒150更容易受到较高频EMI的影响。因为高频EMI的能量更大，它们可能在IC晶粒的金属线路上产生较大的电压波动。由于现在的IC门尺寸很小，并且用低信号电压进行操作。因此，高频EMI产生的信号线电压波动可能导致其逻辑状态的变化，从而导致电子器件的定时和逻辑错误。
塑封材料120对电磁辐射而言通常是透明的。如图1A所示，晶粒150产生的电磁辐射会泄漏出封装体100并可能干扰邻近元件的操作。相反地，邻近元件的EMI也将进入封装体100，且可能干扰晶粒150的操作。
为了解决散热和EMI问题，已经考虑了各种封装配置。图4给出了BGA封装的实例示意图，该封装提高了散热性能，并在EMI屏蔽方面略有改进。图4给出了BGA封装体400的横截面视图，其中IC晶粒150通过粘结剂170贴 装在印刷电路基板410上。焊线130和IC晶粒150被塑封材料120所密封。IC晶粒150通过焊球(solder ball)430与PCB/PWB160电连接。BGA封装体400包括内装式散热器(drop-in heat spreader)425，用于加快塑封材料120内的热量散出。不过，封装体400中不允许IC晶粒150与散热器425直接接触。相应地，IC晶粒150产生的热量必须通过塑封材料120才能到达散热器425，因此可能有部分热量残留在BGA封装体400中。此外，如果有屏蔽作用，内装式散热器425也只能提供有限的EMI屏蔽。例如，BGA封装体400外部产生的EMI可能穿过印刷电路基板410并干扰IC晶粒150的操作。同样地，IC晶粒150产生的EMI也可能通过印刷电路基板410中的金属开口或缺口泄漏出BGA封装体400。
在各种参考文献中讨论了不同类型的散热器设计。如专利号为5，977，626，名称为“Thermally and Electrically Enhanced PBGA Package”，发明人为Wang等的美国专利，专利号为6,552，428，名称为“SemiconductorPackage Having An Exposed Heat Spreader”，发明人为Huang等的美国专利，公开号为20030057550-A1，名称为“Ball Grid Array Package Enhancedwith a Thermal and Electrical Connector”的美国专利，公开号为2005-0280127 A1，名称为“Apparatus And Method For Thermal AndElectromagnetic Interference(EMI)Shielding Enhancement In Die-UpArray Packages”的美国专利，所有这些参考文献都在本申请中全文引用。
各种参考文献中也提出了多种EMI屏蔽设计。如U.S.Patent专利号为5，294，826，名称为”Integrated Circuit Package and Assembly Thereof forThermal and EMI Management”的美国专利和专利号为5,650，659，名称为”Semiconductor Component Package Assembly Including an IntegralRF/EMI Shield”的美国专利，这两个参考文献都可在本申请中全文引用。
商用的导线架式封装体中的集成散热器，或者是安装在正对着DAP的背面(如内装式散热器MQFP封装)，或者是移去导线架中的DAP并将其替换成可贴装IC晶粒的集成散热器。IC晶粒与集成散热器一起封装。这些集成散热器在提高散热性能时，却无法提供针对电磁干扰(EMI)的保护。此外，集成散热 器在结构上完全位于晶粒背面。为了将集成散热器暴露在封装体顶部以连接外部散热器，必须使用晶粒朝下的导线架式封装。如果IC晶粒最初按照传统的晶粒朝上的方式封装，而随后又要添加暴露在封装体顶部的内装式散热器，为了能与管脚输出匹配，就必须重新设计IC晶粒。因此，需要有一种健壮的内装式散热器集成方法，为IC晶粒提供EMI屏蔽并可用于晶粒朝上和晶粒朝下这两种导线架式封装。
本发明将内装式散热器很容易地集成到基于导线架的无引线封装和TAPP型无引线封装中，仅可采用晶粒朝上也可采用晶粒朝下配置。在下面部分，将详细讨论无引线封装中的主要部件，如封帽以及无引线导线架。
散热器封帽结构实例
本部分将讨论改进后的散热器封帽的结构实施例。从其中的启示得出其它实施例对本领域技术人员而言是显而易见的。在此所述的封帽结构实施例的各部件可按任何方式进行组合。
根据本发明实施例，图5A示出了封帽510的横截面示意图。图5B示出了封帽510的仰视图。封帽510可集成到各种集成电路封装体中，如图7A-7F所示，下文将对其进行详细说明。该封装体可集成导线架，如图6A-6C所示，下面将对其进行详细说明。
封帽510包括顶部590、侧壁592和沿着封帽510底部的四周向外延伸的边缘594。应注意，“顶部”和“底部”的说法只是为了便于说明，而不是说本发明将限于某特定空间方向。
侧壁592将顶部590和边缘594连接(如，电连接、结构连接和热连接)在一起。此外，侧壁592从顶部590开始向外倾斜。尽管图5A中所示的顶部590为平面形，顶部590也可为非平面形的(如，为曲面、凹面、凸面、球面或其它形状)。此外，尽管图5A和5B示出了向外倾斜的侧壁592，侧壁592也可为垂直的或从顶部590向内倾斜。此外，侧壁592的横截面不限于直线形，如本领域的技术人员应当知晓，也可以是其它的横截面形状，诸如向内弯或向 外弯的曲线形。
封帽510进一步包括第一表面580(外表面)和第二表面585(内表面)。第二表面585构成封帽510的底部中的空腔(cavity)570的上边界。边缘594围绕着空腔570。图5A所示的空腔570的横截面为梯形，但也可为其它形状(如，正方形、长方形、不规则形状等)。尽管图5B所示空腔570为圆形，空腔570还可为其它形状。另外，封帽510可以为各种形状，诸如圆形、矩形、方形、椭圆形、卵形或其它任何形状。
在封帽510中，边缘594的周边部分是完全平坦的。边缘594周边(lip)部分的底面设有一个或多个突出部515a-e。突出部515a-e可为任何形状。例如，图5A和5B示出了平截头形突出部515a、圆锥形突出部515b、圆锥形突出部515c和515d形成的突出部对517和长方形突出部515e。封帽510并不限于所示突出部515的形状、尺寸、位置或数量。封帽510可具有零个或多个任意形状、任意尺寸、位于任意位置的突出部。
优选地，封帽510的外围尺寸等于或小于外排引线所包围的平坦区域的外围尺寸，以便于检查与PCB/PWB相连的引线。在另一实施例中，封帽510的外围尺寸超出外排引线所包围的平坦区域的外围。从制造角度考虑，封帽510的外围尺寸最好小于导线架周界支撑环630的尺寸(如，请参见图6A，下面将进行说明)。尽管所示封帽510具有特定尺寸，本领域技术人员应知晓，可采用其它尺寸的封帽。
在一实施例中，封帽510可配置为安装有外部散热器。在另一实施例中，封帽510可配置为热连接和/或电连接到PCB/PWB。
封帽510可由导热材料和/或导电材料制成，如金属。例如，用于制造封帽510的材料可包括铜、铜合金(如，C194、C151、C7025或EFTEC 64T)、铝、铝合金、铁磁性材料、铜箔或铁箔等。还可使用其它金属或金属/合金组合物，或其它导热和导电材料(如，陶瓷、镀金属塑料、覆有金属箔的塑料或陶瓷等)。封帽510和DAP 140可由相同或不同的材料制成。当封帽510由相同材料制成时，或者由热膨胀系数相同的材料制成时，可提高结构完整性，如减小晶粒(夹在封帽和导线架中间)上的热应力。此外，封帽510的厚度根据具体应用而定， 可以是任意厚度。例如，封帽厚度可介于0.1-0.5mm。可选地，封帽510的厚度可小于1.0mm。
边缘594周边部分的底面或部分底面涂敷或压制有绝缘材料层(如，阻焊层(solder mask)、绝缘膜等)。这样，可避免封装体在装配后发生引线短路。
在一实施例中，封帽具有贯穿第一表面580和第二表面585的开口。例如，图5C和5D示出了封帽511，其中在侧壁592形成了开口或狭槽520。尽管图5C和5D所示的侧壁592中的狭槽520为方形或梯形，狭槽520还可为其它形状。
在另一实施例中，图5E示出了封帽512在顶部590具有洞孔/开口530。封帽512可开设任意数量的洞孔。此外，洞孔530可为任意形状。
在制造过程中，封帽512中的洞孔530和封帽511中的狭槽520允许塑封材料120流入空腔570中。另外或者可选地，狭槽520和洞孔530可释放在空腔570中形成(在制造中或制造后)的压力。由于较小的洞孔530和狭槽520需要更高的压力将塑封材料120流入或注入空腔570，因此，从制造角度出发就希望有较大的洞孔530和狭槽520。然而，为了降低EMI的穿透，则希望能限制洞孔530和狭槽520的尺寸。洞孔530和狭槽520的尺寸可介于0.5-3.0mm的范围。直径为1.5mm的洞孔可屏蔽10GHz左右的最高谐波频率的EMI。封帽510的外表面可完全或部分密封在塑封材料120中，或者不用塑封材料120覆盖。
如图5F所示，封帽510+的内表面(第二表面585)可连接有导热块586，用于减小散热器封帽和IC晶粒150顶部表面之间的距离。导热块586还可连接到IC晶粒150的顶部表面的中心区域，并离开IC晶粒150的外围接合焊盘。导热块可为任何形状，且可由包括铜、铝、金属合金、硅等材料在内的任意材料制成。当封帽510+由连接到IC晶粒150的导热块586支撑时，封帽510+ 可悬挂着而不与DAP、DAP扩展部(如连接杆(tie bar))或封装引线相连。
导线架结构实例
本部分说明导线架结构的实施例。如前所述，无引线封装可基于导线架也 可不基于导线架。从其中的启示得出其它实施例对本领域技术人员而言是显而易见的。在此所述的导线架实施例的各部件可按任何方式进行组合。
图6A-6C示出了各种导线架结构。图6A给出了导线架600，其中包括具有中心部605的DAP 604和多个连接杆(tie bar)620。导线架600还包括多条引线607和周界支撑环630。DAP中心部605类似于图1A中的外露DAP 140。图6A中，导线架600为矩形，围绕其外围的是矩形周界支撑环630。周界支撑环630包括相互连接为矩形环的第一周界边缘或堤坝(dam bar)634a，第二周界边缘或堤坝634b，第三周界边缘或堤坝634c和第四周界边缘或堤坝634d。请注意，堤坝634a-634b可为单独横条(bar)，可以连接成环状也可不连接成环状。DAP中心部605位于导线架600的中心。DAP中心部605可为方形。在图6A实施例中，连接杆(tie bar)620从DAP中心部605的四个角上向外延伸。
引线607从周界支撑环630向内垂直延伸。引线607a-7连接到连接杆620。引线607a连接在导线架600的边缘634a和连接杆620a之间。引线607b连接在导线架600的边缘634a和连接杆620b之间。引线607c连接在导线架600的边缘634b和连接杆620b之间。引线607d连接在导线架600的边缘634b和连接杆620c之间。引线607e连接在导线架600的边缘634c和连接杆620c之间。引线607f连接在导线架600的边缘634c和连接杆620d之间。引线607g连接在导线架600的边缘634d和连接杆620d之间。引线607h连接在导线架600的边缘634d和连接杆620a之间。引线607由导线架600中的周界支撑环630支撑。引线607(除了引线607a-h之外)可能有一部分位于周界支撑环630中，与导线架600的中心成放射状角度。
尽管图6A-6C示出的导线架、DAP中心部605和周界支撑环630均为方形，但还可使用其它形状(如，矩形、圆形、椭圆、曲线矩形(curvilinearrectangle)等)。此外，引线607的数量也并不限于图6A所示，导线架可有任意数量的引线607。
图6B示出了导线架600实施例601。可加宽连接杆620，且可位于沿着DAP中心部605的其它位置，如图6B所示。连接杆上可熔接任意数量的引线 607，这将进一步地有效加宽连接杆。图6B给出了连接在DAP中心部605和第一及第二引线607x及607y之间的连接杆640。导线架601可有一个或多个熔接连接杆引线620、加宽熔接引线640，或者两者兼而有之。可选地，导线架601可以既没有加宽熔接引线640也没有熔接连接杆引线620。此外，如图6B所示，导线架601可有一个或多个未连接引线607的连接杆610。
在图6C所示的另一实施例602中，连接杆602a-d上设有匹配座615。匹配座615对应于封帽中形成的突出部515(如图5A所示)。匹配座615包括矩形匹配座615a，圆锥形匹配座615b和615c形成的匹配座对617、圆形匹配座615d和615e形成的匹配座对619和圆形匹配座615f。不过，匹配座615并不限于这些形状和形状、数量、位置或尺寸的组合。匹配座615可以是凹孔(未完全穿透导线架602)，也可以是通孔(完全穿透导线架602)。导线架602可以有任意数量的具有任意尺寸、形状和位置的匹配座615。导线架602中的匹配座615被配置为与封帽510中的突出部515相连，以增强结构强度，同时增强热连接和电连接。
导线架的材料包括金属，如铜、铜合金(如，C194、C151、C7025或EFTEC64T)、铝、铝合金、铁磁性材料、其它金属或金属/合金组合物，或其它导热和导电材料。封帽510和导线架600可由相同或不同的材料制成。根据应用的不同，导线架600可为任意厚度。例如，导线架600的厚度可介于0.05mm到0.5mm之间。在另一实施例中，导线架600的厚度小于1.17mm。
在一实施例中，导线架600为IC封装体提供了加强(stiffening)和/或结构支撑。在另一实施例中，导线架600为IC封装体提供了热扩散渠道。在又一实施例中，导线架600具有导电性，可作为IC封装体的电源平面(powerplane)或接地平面(ground plane)。根据特定应用的要求，导线架600可配置为可提供加强、散热和导电的任何组合。
采用导线架-封帽密围结构的封装实例
本部分说明IC封装体的实施例。从其中的启示得出其它实施例对本领域技术人员而言是显而易见的。在此所述的导线架实施例的各部件可按任何方式 进行组合。
图7A示出了安装在PCB/PWB上的IC封装体702。封装体702包括IC晶粒150、焊线130、塑封材料120、粘结剂170、导线架600和封帽510。导线架600包括DAP中心部605、连接杆620(图中未示出)和引线607。贴装在DAP中心部605的IC晶粒150采用晶粒朝上的配置方式。封帽510正对着晶粒150。导线架600和封帽510形成了完全包覆IC晶粒150的密围结构720，增强了结构完整性、EMI屏蔽性能、散热性能和环境(如机械撞击、摇动、腐蚀、湿度和辐射)防护性能。请注意，DAP中心部605还可连接更多的IC晶粒和/或其它电子器件。
封帽510和导线架600可由铜或铜合金制成。铜的热传导系数(大约为390W/m.K)远大于一般的塑封材料120(0.2-0.9W/m.K)。因此，晶粒150产生的热量通过粘结剂170传到DAP中心部605，并通过连接杆620(图7A中未示出)、封装引线607和封帽510传到封装体外部。另外，由于封帽510和导线架600电连接在一起，它们可形成近似等电位表面，这样该密围结构就近似于理想“法拉第笼(Faraday Cage)”。在这种情况下，晶粒150与外部EMI隔离。此外，还可为外部设备屏蔽晶粒150产生的EMI。由于与塑封材料120使用的一般固化塑封材料(大约为25GPa)相比，铜和铜合金具有高得多的弹性系数(大约为125GPa)，本发明的实施例采用铜，可提供更好的结构刚性和环境防护性能。
在一实施例中，封帽510和导线架600不采用突出部和匹配座而连接在一起。在另一实施例中，如图7A所示，封帽510具有适合导线架600中的对应匹配座(类似于匹配座615，图中未示出)的突出部515。突出部515和导线架600中的对应匹配座有助于将封帽510锁紧到导线架600中。进一步地，突出部515和导线架600中对应匹配座的配置方式使得封帽510只能在一个方向正确装配到导线架上，以便于装配。请注意，在可选实施例中，封帽510中可有与导线架600中的突出部互锁的匹配座。
导热和/或导电粘结剂材料(如，填充有银薄片或其它传导微粒的环氧树脂)可用于加强封帽510和导线架600之间的连接性。粘结剂材料可用于粘合 突出部515和导线架600中的对应匹配座。可选地，粘附材料可用于封帽510与导线架600相接触的地方。通过诸如焊料涂敷和回流焊，或焊料丝网印刷和回流焊等工艺(through processes such as solder plating and reflow orscreen printing of solder paste and reflow)，可采用锡焊料或银焊料来连接封帽510和导线架600。在另一实施例中，可采用焊接或其它金属连接方式将封帽510接合到导线架600。
导线架600可镀上一层传导材料以增强热连接和电连接。在一实施例中，封帽510安装在导线架600的DAP中心部605上。在另一实施例中，封帽510安装在连接DAP中心部605和封装引线607的连接杆620上。在又一实施例中，如图7A所示，封帽510安装在一个或多个引线607上。封帽510可安装在DAP中心部605、连接杆620和引线607的任何组合上。此外，封帽510边缘594的部分底面或全部底面可涂敷有绝缘材料层(如，阻焊层、绝缘膜等)，以避免与一条或多条引线607短路。在一个实施例中，封帽510可能与导线架600没有物理上的接触。在另一实施例中，当采用焊接或其它金属连接方法来接合封帽510和导线架600时，封帽510和导线架600间的接触面完全平坦且光滑。
导线架600的引线607被制造成一定形状以连接到PCB/PWB 160。例如，从封装体702延伸出的引线607外面部分向下弯曲，使引线607与PCB/PWB 160接触。
集成电路封装的其它实例
在密围结构中填充塑封材料，如圆顶封装体(glob top)或塑封料，可增强IC封装体的结构刚性和平整性。例如，塑封材料和密围结构的组合可以降低IC晶粒裂化和分层。在密围结构中填充塑封材料还可提高环境防护性能。例如，集成封装体可对机械压力、撞击、摇动、化学腐蚀、湿度、热照(heatexposure)、辐射等进行防护。
此外，将IC晶粒直接连接到密围结构可增加晶粒支撑力度(mass)，同时有助于降低微噪效应(microphonics)。IC晶粒的金属痕量(trace)具有电阻、电容和电感。进行IC封装并将封装体装配到PCB/PWB之后，该IC晶粒处 于机械应力之下。摇动、机械撞击或温度的突然变化可能导致IC晶粒内的应力分布发生变化，从而改变电容和电阻，进而产生电压波动或漂移，这一现象称为微噪效应。将半导体晶粒直接连接到密围结构上，可增加该力度，有助于减缓这些机械撞击和摇动，进而降低微噪效应。
一般的塑封材料，如塑料塑封材料，其热传导系数较低(如，约为0.2-0.9W/m.K)，因此成为传统IC封装体中的散热瓶颈。该密围结构通过提供从IC晶粒底面到封装体外表面的热传导路径，可消除这一瓶颈。此外，该密围结构可由具有较高热传导系数(如，约为390W/m.K的铜)的材料支撑，因此可加快散热。
由封帽510和导线架600形成的密围结构可用许多不同的配置方式集成到IC封装体中。图7A-7F示出了本发明的几个实施例，每个实施例给出了一种密围结构。例如，在图7A中，封帽510与导线架600相连以形成密围结构720。密围结构720完全包覆IC晶粒150。在图7A-7F所示的封装体中，至少有一条焊线130将IC晶粒150表面的至少一个接合焊盘(bond pad)(图中未示出)连接到导线架600。连接到导线架600的IC接合焊盘可为接地焊盘(groundpad)。
如图7A所示，封帽510的顶部表面590从密封封装体702的塑封材料120中露出。因此，塑封材料120并没有完全覆盖第一表面580(封帽510的外表面)。第二表面585(封帽510的内表面)被塑封材料120覆盖。
图7B中的封装体704和图7C中的封装体706与图7A中的封装体702类似，不过给出了与导线架600中的引线607相关的连接杆620的相对位置(图7A中未示出)。图7B示出的导线架600中连接杆620与引线607处于同一平面。连接杆也可位于与引线不同的平面上。如图7C所示，连接杆621位于引线607上。
图7D示出了与图7A中封装体702类似的IC封装体708。不过，在IC封装体708中，封帽510被配置成安装有外部散热器。导线架600和封帽510提供了一条供热量从晶粒150传导到散热器701的路径，进而可散出到封装体708外。在封装体708中，封帽510的第一和第二表面580和585都未被塑封 材料120覆盖。在IC封装体708中，在装配过程中，使用了塑封材料120之后才将封帽510添加到封装体中。
与封装体702类似，封装体710可包括封帽511，而不是不带开口的封帽510。如图7E所示，封帽511有一个或多个开口(如，狭槽520)。这些开口可作为塑封材料入口，以使塑封材料120流入或注入到空腔570中。在封装体710中，封帽511的第一表面580和第二表面585均被塑封材料120覆盖。
图7F示出了封装体712，它是图7A所示封装体702的等价TAPP版本。由于TAPP类型封装的特性，引线385可按阵列方式围绕着DAP 140排列，其中多排而不是单排。焊线130用于将IC晶粒150的接合焊盘连接到引线385。带有突出部515的封帽510可连接到最外一排引线385。DAP 140周围可有一个或多个插入环390。封帽510和DAP 140可为包覆IC晶粒150的密围结构的一部分。在一个实施例中，DAP 140、插入环390和引线385可相互连接构成导线架。接合图7B-7E所述的各种封装结构也适用于TAPP封装体712。
本发明的实施例并不限于晶粒朝上的配置。根据本发明实施例，封装体可配置为晶粒朝下。与图7A中的封装体702相比，封帽510的表面580可暴露在封装体的底面外。图7A-7F示出的实施例所反映的特征也适用于晶体朝下的配置。在晶粒朝下的封装体中，封帽510的外露表面580可用导热和/或导电接合剂或焊料连接到PCB/PWB 160中。这样，从IC晶粒150传出的热量通过导线架600和封帽510传导出封装体进入PCB/PWB 160。封帽510的表面580可电连接到PCB/PWB 160的电源焊盘(power pad)，以提高EMI屏蔽和来自封装体的电传输(power delivery)。可选地，封帽510的表面580可电连接到PCB/PWB 160的接地焊盘(ground pad)，以改进EMI屏蔽和从封装体返回的电流。在晶粒朝下的配置中，封帽510的外表面580可连接热和/或电连接器，诸如导热块，其中该导热块将封装体连接到PCB/PWB。
制造流程实例
根据本发明的一个实施例，图8给出了图7A所示导线架式封装体702的装配步骤流程图800。本领域技术人员应知晓，可采用这些装配流程来装配任 意实施例，包括图7A-7F所示的那些实施例。根据该教导，相关领域技术人员应知晓，图8中的步骤并不必须按照其显示顺序进行，根据下面的讨论，其它操作和结构实施例对于相关领域技术人员是显而易见的。出于解释说明的目的，下面将结合图9A-9G详细描述这些步骤。图9A-9D给出了装配中不同阶段的俯视图，而图9E-9G给出了截面图。
流程图800开始于步骤805。在步骤805中，用板料加工成导线架。导线架材料实例和特性在本文其它地方已经讨论。
在步骤810中，将至少一个IC晶粒安装到导线架的DAP中。
在步骤815中，将各焊线相互连接。
在步骤820中，将封帽安装到导线架。
在步骤825中，密封该封装体。
在步骤830中，切除导线架的周界支撑环。
在步骤870中，形成单个封装体，即，将封装体从导线架板中切开。
图9A给出了单个导线架600的视图。请注意，图9A-9G中的导线架600具有导线架实施例601和602中所述的特征。
图9B示出了包含导线架600阵列的导线架板900的实例。导线架板900中的导线架600通过蚀刻或冲压工艺制成。
图9C示出了已完成部分装配的封装体910。至少一个IC晶粒150连接到DAP中心部605。焊线130用于将IC晶粒150的接合焊盘连接到导线架600，从而提供了从IC晶粒150到引线607、连接杆620和/或DAP中心部605的电连接。封帽510连接到导线架600。导电和/或导热粘结材料用于增强封帽510和导线架600直接的连接。封帽510和导线架600连接在一起形成密围结构，以完全包覆IC晶粒150。封帽510的空腔尺寸应足够大，以避免封帽510与焊线接触。
图9D示出了已完成部分装配的导线架板920中的部分装配后的封装体910。
图9E示出了在完成流程图800中的步骤815之后的部分装配后的封装体的截面图。
图9F示出了在完成流程图800中的步骤820之后，图9D的部分装配的导线架板920的截面图。
图9G示出了在完成流程图800中的步骤825之后，密封导线架板930的导线架式封装体的截面图。在步骤825中，密封封装体。在该步骤中，使用塑封材料密封部分装配的封装体910。封装体910被夹在模具(mold chase)上，使密封该封装体的塑封料成型。如本文其它地方所述，封帽的外部周界尺寸小于周界支撑环630的周界尺寸。从而防止塑封材料通过引线607间的缺口溢出。在转移成型处理期间，支撑环630还可提供夹紧的模具间的气密性(sealing)。
在步骤830中，切除导线架周界支撑环630进。引线607已经形成电路板安装的接触引脚，导线架式封装体已装配完毕。例如，从封装体向外延伸的引线607外侧部分可向下弯曲，以允许它们接触PCB/PWB。
在步骤870中，从导线架板中切下单个封装体，如图7A的封装体702。
根据本发明的另一实施例，图10示出了集成电路封装体的形成步骤的流程图1000。步骤805、810和815与图8所示的流程图800相同。不过，步骤1055(将导线架放在模具中)，步骤1060(将封帽放在模具中)和步骤1070(完成密封)与流程图800不相同。
根据流程图1000中所示的装配流程图，不是在模具外面将封帽510连接到导线架600上，而是在步骤1055和1060中将导线架600和封帽510放在模具中。导线架600夹在上模具和下模具之间，通过将导线架与封帽夹紧，使得到放置在模具中的封帽和导线架上的连接杆或熔接引线相接触。为了加强封帽和导线架之间的电接触，在夹紧模具上的部件前，可在导线架的接触块上预先放置导电粘结剂(adhesive)，如含有银片/粉的环氧树脂。
在步骤1065中，完成封装体密封。
流程图1000中的后续装配步骤与流程图800类似。
在步骤830中，切除导线架周界支撑环630，
在步骤870中，形成(singulate)单个封装体，即，从导线架板中切开。
图11A-11C给出了根据不同于流程图800和1000中所述的另一装配处理过程如何装配封装体1101(与图7D中的封装体708类似，不过没有外部散热 器701)的示意图。在该处理过程中，成型步骤之后将封帽510连接到DAP中心部605。图11A是完全装配后单个封装体1101的截面图。图11B示出了多个未分开的导线架在同时成型后形成的成型条1103。成型后，各封装体的部分DAP暴露在外，如四个角上的连接杆。图11C示出了单个导线架式封装体1102经过成型处理后且安装封帽510之前的俯视图。图11C示出了单一封装体1102的外露连接杆。封帽510连接到外露连接杆以形成密围结构。封帽表面580和585均未被塑封材料120覆盖。
请注意，当使用包括连接到连接杆或熔接引线的接地/电源内插环的TAPP型导线架时而不是传统导线架时，可利用类似的装配处理。
实施例的优点
除了前述优点，连接有集成导热和导电封帽的晶粒托盘提供了各种优点。其中包括：当封帽连接到IC或PCB上的对应接合焊盘时，可容易连接到封装体的等电位平面(包括地电位)；在非密封塑料封装中，减少湿气对IC表面的影响；可灵活增加或移除集成封帽，而无需更改导线架或TAPP型封装设计。
结论
尽管上文描述了本发明的各种实施例，但应明白，这些实施例仅为示例而非限制。本领域技术人员应知晓，在不脱离本发明的精神和范围的情况下，可以对这些特征和实施例进行各种改变或等效替换。因此，本发明不受此处所公开的具体实施例的限制，所有落入本申请的权利要求范围内的实施例都属于本发明的保护范围。
相关申请交叉引用
本申请要求申请日为2006年5月16日、申请号为60/800，433的美国临时专利的优先权，本申请引用其全部内容。
本申请还引用以下美国专利申请：
2005年10月20提交、申请号为11/153，714、名称为“Methods and Apparatus for Improved Thermal Performance and ElectromagneticInterference(EMI) Shielding in Leadframe Integrated Circuit (IC)Packages”。
2004睥6月21日提交、公开号为2005-0280127A1、名称为“Apparatusand Method for Thermal and Electromagnetic Interference(EMI) ShieldingEnhancement in Die-Up Array Packages”。

Claims (12)

1.一种集成电路器件封装体，其特征在于，包括：
带有接合焊盘的集成电路晶粒；
包围集成电路晶粒的密围结构，其包括：
带有平坦中心部的晶粒托盘，所述中心部具有彼此相对的第一和第二表面；与晶粒托盘中心部相连且从中心部向外延伸的多个连接杆；其中集成电路晶粒贴装在晶粒托盘中心部的第一表面；以及
带有空腔和围绕该空腔的平整边缘的封帽，当封帽边缘连接到晶粒托盘时，空腔面向集成电路晶粒，从而将集成电路晶粒包围；
带有线焊用引线手指的多条引线，所述引线围绕晶粒托盘周围至少排列一排；以及
塑封材料，用于密封集成电路晶粒且至少部分地填充所述空腔；
其中，所述晶粒托盘和多条引线连接在一起形成导线架，其中有一个或多个周界支撑环或堤坝在结构上连接各引线；所述多个连接杆中有至少一个连接杆要宽于所述多个连接杆中的其它连接杆，除四个角外，其还可位于沿着晶粒托盘中心部的其它位置，且连接杆上可熔接任意数量的引线。
2.根据权利要求1所述的集成电路器件封装体，其特征在于，所述封装体为晶粒朝上或晶粒朝下配置。
3.根据权利要求1所述的集成电路器件封装体，其特征在于，所述密围结构将集成电路晶粒工作期间产生的热量向外散发。
4.根据权利要求1所述的集成电路器件封装体，其特征在于，所述密围结构屏蔽集成电路晶粒发出的电磁干扰，同时屏蔽封装体外部向集成电路晶粒辐射的电磁干扰。
5.根据权利要求3所述的集成电路器件封装体，其特征在于，所述封帽朝向集成电路晶粒的内表面连接有导热块。
6.根据权利要求1所述的集成电路器件封装体，其特征在于，所述引线以一排以上的阵列方式排列。
7.根据权利要求6所述的集成电路器件封装体，其特征在于，所述封装体进一步包括一个或多个与晶粒托盘周围的连接杆相连的内插导电环。
8.根据权利要求7所述的集成电路器件封装体，其特征在于，所述晶粒托盘、内插环导电和多条引线连接在一起形成导线架。
9.根据权利要求1所述的集成电路器件封装体，其特征在于，所述多条引线中有至少一条引线要宽于所述多条引线中的其它引线。
10.根据权利要求1所述的集成电路器件封装体，其特征在于，所述多个连接杆和所述多条引线位于第一平面。
11.根据权利要求1所述的集成电路器件封装体，其特征在于，所述多个连接杆位于第一平面，而所述多条引线位于第二平面。
12.根据权利要求4所述的集成电路器件封装体，其特征在于，所述封装体进一步包括：至少一条焊线，用于将IC晶粒上的至少一个接合焊盘连接到所述密围结构，由此所述密围结构连接到一个电位。
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Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7271479B2 (en) * 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
US7968377B2 (en) * 2005-09-22 2011-06-28 Stats Chippac Ltd. Integrated circuit protruding pad package system
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US9299634B2 (en) * 2006-05-16 2016-03-29 Broadcom Corporation Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages
US20070273023A1 (en) * 2006-05-26 2007-11-29 Broadcom Corporation Integrated circuit package having exposed thermally conducting body
US7808087B2 (en) * 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US9013035B2 (en) * 2006-06-20 2015-04-21 Broadcom Corporation Thermal improvement for hotspots on dies in integrated circuit packages
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US8169067B2 (en) * 2006-10-20 2012-05-01 Broadcom Corporation Low profile ball grid array (BGA) package with exposed die and method of making same
US20080111219A1 (en) * 2006-11-14 2008-05-15 Gem Services, Inc. Package designs for vertical conduction die
US8183687B2 (en) * 2007-02-16 2012-05-22 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
US7875965B2 (en) * 2008-03-18 2011-01-25 Mediatek Inc. Semiconductor chip package
US7705447B2 (en) * 2008-09-29 2010-04-27 Intel Corporation Input/output package architectures, and methods of using same
KR20120048875A (ko) * 2010-11-08 2012-05-16 삼성전자주식회사 노출 패들을 갖는 쿼드 플랫 패키지
US8513786B2 (en) * 2010-12-09 2013-08-20 Qpl Limited Pre-bonded substrate for integrated circuit package and method of making the same
CN102157405B (zh) * 2010-12-22 2012-07-04 北京时代民芯科技有限公司 基于熔封封帽工艺的芯片真空共晶焊接方法
US8969136B2 (en) 2011-03-25 2015-03-03 Stats Chippac Ltd. Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof
US8669646B2 (en) * 2011-05-31 2014-03-11 Broadcom Corporation Apparatus and method for grounding an IC package lid for EMI reduction
US20140103505A1 (en) * 2012-10-16 2014-04-17 Broadcom Corporation Die down integrated circuit package with integrated heat spreader and leads
JP5802695B2 (ja) * 2013-03-19 2015-10-28 株式会社東芝 半導体装置、半導体装置の製造方法
ITVI20130077A1 (it) 2013-03-20 2014-09-21 St Microelectronics Srl Un materiale riempitivo a base di grafene con una elevata conducibilita' termica per il collegamento di chips in dispositivi a microstruttura
CN104378915A (zh) * 2013-08-12 2015-02-25 三星电机株式会社 无线通信模块及其制造方法
US9064838B2 (en) 2013-09-17 2015-06-23 Freescale Semiconductor, Inc. Heat spreader for integrated circuit device
US20150311143A1 (en) * 2014-04-29 2015-10-29 Freescale Semiconductor, Inc. Lead frames having metal traces with metal stubs
WO2017001369A1 (en) * 2015-07-02 2017-01-05 Koninklijke Philips N.V. A surface mount device and a method of attaching such a device
US10217717B2 (en) * 2015-11-18 2019-02-26 Stmicroelectronics (Rousset) Sas Distribution of electronic circuit power supply potentials
JP6577374B2 (ja) * 2016-01-19 2019-09-18 三菱電機株式会社 半導体装置
US9953929B2 (en) * 2016-03-18 2018-04-24 Intel Corporation Systems and methods for electromagnetic interference shielding
US9793222B1 (en) 2016-04-21 2017-10-17 Apple Inc. Substrate designed to provide EMI shielding
IT201700000485A1 (it) * 2017-01-03 2018-07-03 St Microelectronics Srl Dispositivo a semiconduttore, apparecchiatura e procedimento corrispondenti
US10651127B2 (en) * 2017-09-29 2020-05-12 Intel Corporation Ring-in-ring configurable-capacitance stiffeners and methods of assembling same
KR102565415B1 (ko) * 2018-02-21 2023-08-09 삼성디스플레이 주식회사 표시 장치
US10440813B1 (en) 2018-06-28 2019-10-08 Nxp Usa, Inc. Microelectronic modules including thermal extension levels and methods for the fabrication thereof
CN109223019B (zh) * 2018-09-21 2021-12-21 上海联影医疗科技股份有限公司 一种pet探测单元及pet探测器
WO2020057654A1 (en) 2018-09-21 2020-03-26 Shanghai United Imaging Healthcare Co., Ltd. Systems for imaging
US11264309B2 (en) * 2019-06-24 2022-03-01 Mediatek Inc. Multi-row QFN semiconductor package
CN111653552B (zh) * 2020-06-16 2022-06-10 西安科技大学 一种具有高抗电磁脉冲干扰能力的四方扁平芯片封装结构
US11901308B2 (en) * 2020-07-21 2024-02-13 UTAC Headquarters Pte. Ltd. Semiconductor packages with integrated shielding
JP2022046921A (ja) * 2020-09-11 2022-03-24 セイコーエプソン株式会社 電子デバイスの製造方法
TWI761116B (zh) * 2021-03-08 2022-04-11 南茂科技股份有限公司 半導體封裝結構及導線架
CN114582733B (zh) * 2022-05-07 2022-07-26 广东气派科技有限公司 一种具有电磁屏蔽功能的芯片封装结构及封装方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223739A (en) * 1989-09-14 1993-06-29 Kabushiki Kaisha Toshiba Plastic molded semiconductor device having waterproof cap
US5482898A (en) * 1993-04-12 1996-01-09 Amkor Electronics, Inc. Method for forming a semiconductor device having a thermal dissipator and electromagnetic shielding
US5486720A (en) * 1994-05-26 1996-01-23 Analog Devices, Inc. EMF shielding of an integrated circuit package

Family Cites Families (216)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3790866A (en) * 1973-05-14 1974-02-05 Gen Motors Corp Semiconductor device enclosure and method of making same
US4611238A (en) 1982-05-05 1986-09-09 Burroughs Corporation Integrated circuit package incorporating low-stress omnidirectional heat sink
US4480262A (en) 1982-07-15 1984-10-30 Olin Corporation Semiconductor casing
US4680613A (en) 1983-12-01 1987-07-14 Fairchild Semiconductor Corporation Low impedance package for integrated circuit die
US4560826A (en) 1983-12-29 1985-12-24 Amp Incorporated Hermetically sealed chip carrier
DE3623419A1 (de) * 1986-07-11 1988-01-21 Junghans Uhren Gmbh Verfahren zum bestuecken eines leiterbahnen-netzwerkes fuer den schaltungstraeger eines elektromechanischen uhrwerks und teilbestuecktes leiterbahnen-netzwerk eines uhrwerks-schaltungstraegers
US5105260A (en) * 1989-10-31 1992-04-14 Sgs-Thomson Microelectronics, Inc. Rf transistor package with nickel oxide barrier
US5045921A (en) 1989-12-26 1991-09-03 Motorola, Inc. Pad array carrier IC device using flexible tape
US5065281A (en) 1990-02-12 1991-11-12 Rogers Corporation Molded integrated circuit package incorporating heat sink
US5173766A (en) 1990-06-25 1992-12-22 Lsi Logic Corporation Semiconductor device package and method of making such a package
DE69129619T2 (de) 1990-09-19 1999-02-25 Fujitsu Ltd Halbleitervorrichtung mit einer vielzahl von anschlussstiften
US5153379A (en) 1990-10-09 1992-10-06 Motorola, Inc. Shielded low-profile electronic component assembly
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5208504A (en) * 1990-12-28 1993-05-04 Raytheon Company Saw device and method of manufacture
JPH04322452A (ja) 1991-04-23 1992-11-12 Mitsubishi Electric Corp 半導体装置、半導体素子収納容器および半導体装置の製造方法
US5376756A (en) 1991-12-20 1994-12-27 Vlsi Technology, Inc. Wire support and guide
DE4212948A1 (de) 1992-04-18 1993-10-21 Telefunken Microelectron Halbleiterbaugruppe, insbesondere Fernsteuer-Empfangsmodul
JP3322429B2 (ja) 1992-06-04 2002-09-09 新光電気工業株式会社 半導体装置
US5801432A (en) 1992-06-04 1998-09-01 Lsi Logic Corporation Electronic system using multi-layer tab tape semiconductor device having distinct signal, power and ground planes
US5583377A (en) 1992-07-15 1996-12-10 Motorola, Inc. Pad array semiconductor device having a heat sink with die receiving cavity
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5438216A (en) 1992-08-31 1995-08-01 Motorola, Inc. Light erasable multichip module
JPH06163794A (ja) * 1992-11-19 1994-06-10 Shinko Electric Ind Co Ltd メタルコアタイプの多層リードフレーム
US5386344A (en) 1993-01-26 1995-01-31 International Business Machines Corporation Flex circuit card elastomeric cable connector assembly
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts
US5497032A (en) * 1993-03-17 1996-03-05 Fujitsu Limited Semiconductor device and lead frame therefore
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US5294826A (en) * 1993-04-16 1994-03-15 Northern Telecom Limited Integrated circuit package and assembly thereof for thermal and EMI management
US5397917A (en) * 1993-04-26 1995-03-14 Motorola, Inc. Semiconductor package capable of spreading heat
US5825042A (en) * 1993-06-18 1998-10-20 Space Electronics, Inc. Radiation shielding of plastic integrated circuits
US5394009A (en) * 1993-07-30 1995-02-28 Sun Microsystems, Inc. Tab semiconductor package with cushioned land grid array outer lead bumps
JPH0766331A (ja) 1993-08-02 1995-03-10 Motorola Inc 半導体デバイス・パッケージの製造方法
US5650662A (en) 1993-08-17 1997-07-22 Edwards; Steven F. Direct bonded heat spreader
US5397921A (en) * 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array
US6326678B1 (en) * 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5772451A (en) * 1993-11-16 1998-06-30 Form Factor, Inc. Sockets for electronic components and methods of connecting to electronic components
US5366589A (en) 1993-11-16 1994-11-22 Motorola, Inc. Bonding pad with circular exposed area and method thereof
US5642261A (en) * 1993-12-20 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball-grid-array integrated circuit package with solder-connected thermal conductor
KR970005712B1 (ko) 1994-01-11 1997-04-19 삼성전자 주식회사 고 열방출용 반도체 패키지
JP3247384B2 (ja) 1994-03-18 2002-01-15 日立化成工業株式会社 半導体パッケージの製造法及び半導体パッケージ
US5578869A (en) 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US6720493B1 (en) 1994-04-01 2004-04-13 Space Electronics, Inc. Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages
US6347037B2 (en) * 1994-04-28 2002-02-12 Fujitsu Limited Semiconductor device and method of forming the same
US5474957A (en) 1994-05-09 1995-12-12 Nec Corporation Process of mounting tape automated bonded semiconductor chip on printed circuit board through bumps
US5583378A (en) 1994-05-16 1996-12-10 Amkor Electronics, Inc. Ball grid array integrated circuit package with thermal conductor
WO1995031826A1 (en) * 1994-05-17 1995-11-23 Olin Corporation Electronic packages with improved electrical performance
JP3046203B2 (ja) 1994-05-18 2000-05-29 三菱電機株式会社 ハンズフリー通話装置
JP2565300B2 (ja) 1994-05-31 1996-12-18 日本電気株式会社 半導体装置
MY112145A (en) * 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
JPH0883866A (ja) * 1994-07-15 1996-03-26 Shinko Electric Ind Co Ltd 片面樹脂封止型半導体装置の製造方法及びこれに用いるキャリアフレーム
US5717252A (en) * 1994-07-25 1998-02-10 Mitsui High-Tec, Inc. Solder-ball connected semiconductor device with a recessed chip mounting area
JPH0846085A (ja) 1994-08-02 1996-02-16 Fujitsu Ltd 半導体装置及びその製造方法
US5648679A (en) 1994-09-16 1997-07-15 National Semiconductor Corporation Tape ball lead integrated circuit package
US5541450A (en) 1994-11-02 1996-07-30 Motorola, Inc. Low-profile ball-grid array semiconductor package
US5798909A (en) 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US5572405A (en) 1995-06-07 1996-11-05 International Business Machines Corporation (Ibm) Thermally enhanced ball grid array package
US5844168A (en) 1995-08-01 1998-12-01 Minnesota Mining And Manufacturing Company Multi-layer interconnect sutructure for ball grid arrays
US5650659A (en) 1995-08-04 1997-07-22 National Semiconductor Corporation Semiconductor component package assembly including an integral RF/EMI shield
US5691567A (en) 1995-09-19 1997-11-25 National Semiconductor Corporation Structure for attaching a lead frame to a heat spreader/heat slug structure
US5843808A (en) 1996-01-11 1998-12-01 Asat, Limited Structure and method for automated assembly of a tab grid array package
US5796170A (en) 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
JPH09232465A (ja) * 1996-02-27 1997-09-05 Fuji Kiko Denshi Kk 半導体実装用プリント配線板
KR100192760B1 (ko) * 1996-02-29 1999-06-15 황인길 메탈 캐리어 프레임을 이용한 bag반도체 패키지의 제조방법 및 그반도체 패키지
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
US5986340A (en) 1996-05-02 1999-11-16 National Semiconductor Corporation Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same
US5907903A (en) * 1996-05-24 1999-06-01 International Business Machines Corporation Multi-layer-multi-chip pyramid and circuit board structure and method of forming same
JP2755252B2 (ja) * 1996-05-30 1998-05-20 日本電気株式会社 半導体装置用パッケージ及び半導体装置
US5822848A (en) * 1996-06-04 1998-10-20 Industrial Technology Research Institute Lead frame having a detachable and interchangeable die-attach paddle
US5726079A (en) * 1996-06-19 1998-03-10 International Business Machines Corporation Thermally enhanced flip chip package and method of forming
US5805430A (en) * 1996-07-22 1998-09-08 International Business Machines Corporation Zero force heat sink
US6064111A (en) * 1996-07-31 2000-05-16 Hitachi Company, Ltd. Substrate for holding a chip of semi-conductor package, semi-conductor package, and fabrication process of semi-conductor package
US6011694A (en) * 1996-08-01 2000-01-04 Fuji Machinery Mfg. & Electronics Co., Ltd. Ball grid array semiconductor package with solder ball openings in an insulative base
JP2828053B2 (ja) 1996-08-15 1998-11-25 日本電気株式会社 半導体装置
WO1998013876A1 (fr) 1996-09-26 1998-04-02 Samsung Electronics Co., Ltd. Circuit integre hybride et a frequences micro-ondes
US5856911A (en) * 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
JP2933036B2 (ja) * 1996-11-29 1999-08-09 日本電気株式会社 中空パッケージ
US5866949A (en) * 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US5736785A (en) * 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
JP3032964B2 (ja) 1996-12-30 2000-04-17 アナムインダストリアル株式会社 ボールグリッドアレイ半導体のパッケージ及び製造方法
US5986885A (en) 1997-04-08 1999-11-16 Integrated Device Technology, Inc. Semiconductor package with internal heatsink and assembly method
US6084777A (en) 1997-04-23 2000-07-04 Texas Instruments Incorporated Ball grid array package
US6617193B1 (en) 1997-04-30 2003-09-09 Hitachi Chemical Company, Ltd. Semiconductor device, semiconductor device substrate, and methods of fabricating the same
US6011304A (en) * 1997-05-05 2000-01-04 Lsi Logic Corporation Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
US6160705A (en) 1997-05-09 2000-12-12 Texas Instruments Incorporated Ball grid array package and method using enhanced power and ground distribution circuitry
FI972040A (fi) * 1997-05-13 1998-11-14 Nokia Telecommunications Oy Menetelmä pakettivälitteiseen tiedonsiirtoon
US5907189A (en) * 1997-05-29 1999-05-25 Lsi Logic Corporation Conformal diamond coating for thermal improvement of electronic packages
US5889321A (en) * 1997-06-17 1999-03-30 International Business Machines Corporation Stiffeners with improved adhesion to flexible substrates
US5895967A (en) * 1997-07-07 1999-04-20 Texas Instruments Incorporated Ball grid array package having a deformable metal layer and method
JPH1131751A (ja) 1997-07-10 1999-02-02 Sony Corp 中空パッケージとその製造方法
US5972734A (en) 1997-09-17 1999-10-26 Lsi Logic Corporation Interposer for ball grid array (BGA) package
US5835355A (en) 1997-09-22 1998-11-10 Lsi Logic Corporation Tape ball grid array package with perforated metal stiffener
US6166434A (en) 1997-09-23 2000-12-26 Lsi Logic Corporation Die clip assembly for semiconductor package
US5949137A (en) 1997-09-26 1999-09-07 Lsi Logic Corporation Stiffener ring and heat spreader for use with flip chip packaging assemblies
US5901041A (en) * 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
JP3087709B2 (ja) 1997-12-08 2000-09-11 日本電気株式会社 半導体装置およびその製造方法
US6114761A (en) 1998-01-20 2000-09-05 Lsi Logic Corporation Thermally-enhanced flip chip IC package with extruded heatspreader
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US6552264B2 (en) * 1998-03-11 2003-04-22 International Business Machines Corporation High performance chip packaging and method
US6333565B1 (en) 1998-03-23 2001-12-25 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US5889324A (en) * 1998-03-30 1999-03-30 Nec Corporation Package for a semiconductor device
TW430959B (en) * 1998-04-22 2001-04-21 World Wiser Electronics Inc Thermal enhanced structure of printed circuit board
US6140707A (en) 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
US5903052A (en) * 1998-05-12 1999-05-11 Industrial Technology Research Institute Structure for semiconductor package for improving the efficiency of spreading heat
US6002169A (en) 1998-06-15 1999-12-14 Lsi Logic Corporation Thermally enhanced tape ball grid array package
US6060777A (en) * 1998-07-21 2000-05-09 Intel Corporation Underside heat slug for ball grid array packages
US5977626A (en) 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6092281A (en) 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
US6117797A (en) 1998-09-03 2000-09-12 Micron Technology, Inc. Attachment method for heat sinks and devices involving removal of misplaced encapsulant
US6084297A (en) 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6077724A (en) * 1998-09-05 2000-06-20 First International Computer Inc. Multi-chips semiconductor package and fabrication method
TW383908U (en) 1998-09-22 2000-03-01 Caesar Technology Inc Structure used for increasing heat-dissipation of micro-electronic apparatus
TW418511B (en) * 1998-10-12 2001-01-11 Siliconware Precision Industries Co Ltd Packaged device of exposed heat sink
AU2467599A (en) * 1998-10-14 2000-05-01 Minnesota Mining And Manufacturing Company Tape ball grid array with interconnected ground plane
JP2000133672A (ja) * 1998-10-28 2000-05-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2000138262A (ja) 1998-10-31 2000-05-16 Anam Semiconductor Inc チップスケ―ル半導体パッケ―ジ及びその製造方法
US6313521B1 (en) 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
JP2000150730A (ja) 1998-11-17 2000-05-30 Fujitsu Ltd 半導体装置及びその製造方法
US6069407A (en) * 1998-11-18 2000-05-30 Vlsi Technology, Inc. BGA package using PCB and tape in a die-up configuration
US5999415A (en) 1998-11-18 1999-12-07 Vlsi Technology, Inc. BGA package using PCB and tape in a die-down configuration
US5982621A (en) 1998-11-23 1999-11-09 Caesar Technology Inc. Electronic device cooling arrangement
US6057601A (en) * 1998-11-27 2000-05-02 Express Packaging Systems, Inc. Heat spreader with a placement recess and bottom saw-teeth for connection to ground planes on a thin two-sided single-core BGA substrate
KR100960739B1 (ko) * 1999-02-26 2010-06-01 텍사스 인스트루먼츠 인코포레이티드 열적으로 향상된 반도체 볼 그리드 어레이 디바이스 및 그제조 방법
US6162659A (en) 1999-03-05 2000-12-19 International Business Machines Corporation Method for manufacturing a package structure having a heat spreader for integrated circuit chips
JP2000286294A (ja) 1999-03-30 2000-10-13 Hitachi Ltd 半導体装置およびその製造方法
US6133064A (en) 1999-05-27 2000-10-17 Lsi Logic Corporation Flip chip ball grid array package with laminated substrate
US6229702B1 (en) * 1999-06-02 2001-05-08 Advanced Semiconductor Engineering, Inc. Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability
US6242279B1 (en) * 1999-06-14 2001-06-05 Thin Film Module, Inc. High density wire bond BGA
TW417219B (en) 1999-07-22 2001-01-01 Siliconware Precision Industries Co Ltd Ball grid array package having leads
US6122171A (en) 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
SG87046A1 (en) * 1999-08-17 2002-03-19 Micron Technology Inc Multi-chip module with stacked dice
US6294839B1 (en) 1999-08-30 2001-09-25 Micron Technology, Inc. Apparatus and methods of packaging and testing die
US6184580B1 (en) * 1999-09-10 2001-02-06 Siliconware Precision Industries Co., Ltd. Ball grid array package with conductive leads
US6380623B1 (en) * 1999-10-15 2002-04-30 Hughes Electronics Corporation Microcircuit assembly having dual-path grounding and negative self-bias
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6163458A (en) 1999-12-03 2000-12-19 Caesar Technology, Inc. Heat spreader for ball grid array package
DE29922576U1 (de) 1999-12-22 2000-03-16 Orient Semiconductor Elect Ltd Wärmesenke einer Kunststoffkugel-Gittermatrix auf einer IC-Chipoberfläche
TW452956B (en) * 2000-01-04 2001-09-01 Siliconware Precision Industries Co Ltd Heat dissipation structure of BGA semiconductor package
US6559525B2 (en) 2000-01-13 2003-05-06 Siliconware Precision Industries Co., Ltd. Semiconductor package having heat sink at the outer surface
US6400016B2 (en) 2000-01-14 2002-06-04 I-Ming Chen Method for mounting a semiconductor chip on a substrate and semiconductor device adapted for mounting on a substrate
US6246111B1 (en) * 2000-01-25 2001-06-12 Siliconware Precision Industries Co., Ltd. Universal lead frame type of quad flat non-lead package of semiconductor
US6541832B2 (en) * 2000-01-31 2003-04-01 Texas Instruments Incorporated Plastic package for micromechanical devices
TW478119B (en) * 2000-06-26 2002-03-01 Siliconware Precision Industries Co Ltd Semiconductor package having heat sink which can be anchored on the substrate
JP2002026044A (ja) 2000-07-05 2002-01-25 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6432742B1 (en) 2000-08-17 2002-08-13 St Assembly Test Services Pte Ltd. Methods of forming drop-in heat spreader plastic ball grid array (PBGA) packages
SG102638A1 (en) * 2000-09-15 2004-03-26 Samsung Techwin Co Ltd Lead frame, semiconductor package having the same, and semiconductor package manufacturing method
TW462121B (en) * 2000-09-19 2001-11-01 Siliconware Precision Industries Co Ltd Heat sink type ball grid array package
US6278613B1 (en) 2000-09-27 2001-08-21 St Assembly Test Services Pte Ltd Copper pads for heat spreader attach
TW457663B (en) * 2000-11-08 2001-10-01 Advanced Semiconductor Eng Substrate structure of heat spreader and its package
EP1346411A2 (en) * 2000-12-01 2003-09-24 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US6664617B2 (en) 2000-12-19 2003-12-16 Convergence Technologies, Ltd. Semiconductor package
US20020079572A1 (en) 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US6906414B2 (en) 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
US7161239B2 (en) * 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US7132744B2 (en) * 2000-12-22 2006-11-07 Broadcom Corporation Enhanced die-up ball grid array packages and method for making the same
US6348726B1 (en) 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
TW473962B (en) 2001-01-20 2002-01-21 Siliconware Precision Industries Co Ltd Cavity down ball grid array package and its manufacturing process
US20020096767A1 (en) 2001-01-25 2002-07-25 Cote Kevin J. Cavity down ball grid array package with EMI shielding and reduced thermal resistance
US6853070B2 (en) 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
US6528869B1 (en) * 2001-04-06 2003-03-04 Amkor Technology, Inc. Semiconductor package with molded substrate and recessed input/output terminals
US6614102B1 (en) * 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
US7259448B2 (en) 2001-05-07 2007-08-21 Broadcom Corporation Die-up ball grid array package with a heat spreader and method for making the same
US6537848B2 (en) 2001-05-30 2003-03-25 St. Assembly Test Services Ltd. Super thin/super thermal ball grid array package
US6472741B1 (en) 2001-07-14 2002-10-29 Siliconware Precision Industries Co., Ltd. Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same
US6528892B2 (en) * 2001-06-05 2003-03-04 International Business Machines Corporation Land grid array stiffener use with flexible chip carriers
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
US7015072B2 (en) * 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
JP3607655B2 (ja) 2001-09-26 2005-01-05 株式会社東芝 マウント材、半導体装置及び半導体装置の製造方法
US6657870B1 (en) 2001-10-01 2003-12-02 Lsi Logic Corporation Die power distribution system
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6879039B2 (en) 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US7156161B2 (en) 2002-01-24 2007-01-02 The United States Of America As Represented By The Secretary Of The Navy Lightweight thermal heat transfer apparatus
US6552430B1 (en) * 2002-01-30 2003-04-22 Texas Instruments Incorporated Ball grid array substrate with improved traces formed from copper based metal
US6825108B2 (en) 2002-02-01 2004-11-30 Broadcom Corporation Ball grid array package fabrication with IC die support structures
US7550845B2 (en) 2002-02-01 2009-06-23 Broadcom Corporation Ball grid array package with separated stiffener layer
US6861750B2 (en) * 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
US7245500B2 (en) 2002-02-01 2007-07-17 Broadcom Corporation Ball grid array package with stepped stiffener layer
DE60217059T2 (de) 2002-02-18 2007-06-21 Stmicroelectronics S.R.L., Agrate Brianza Montagekonstruktion für eine elektronische integrierte Leistungsschaltung, die auf einem Halbleiterchip gebildet ist, sowie ein entsprechendes Herstellungsverfahren
JP2003258141A (ja) 2002-02-27 2003-09-12 Nec Compound Semiconductor Devices Ltd 電子部品及びその製造方法
US6876553B2 (en) * 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US20030178719A1 (en) 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US6614660B1 (en) 2002-04-30 2003-09-02 Ultratera Corporation Thermally enhanced IC chip package
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
JP2006501677A (ja) 2002-09-30 2006-01-12 アドバンスド インターコネクト テクノロジーズ リミテッド ブロック成形集成体用の耐熱強化パッケージ
US6775140B2 (en) 2002-10-21 2004-08-10 St Assembly Test Services Ltd. Heat spreaders, heat spreader packages, and fabrication methods for use with flip chip semiconductor devices
US6724080B1 (en) * 2002-12-20 2004-04-20 Altera Corporation Heat sink with elevated heat spreader lid
TWI273680B (en) 2003-03-27 2007-02-11 Siliconware Precision Industries Co Ltd Semiconductor package with embedded heat spreader abstract of the disclosure
US7443693B2 (en) * 2003-04-15 2008-10-28 Wavezero, Inc. Electromagnetic interference shielding for a printed circuit board
US7057277B2 (en) 2003-04-22 2006-06-06 Industrial Technology Research Institute Chip package structure
US6852574B1 (en) * 2003-08-11 2005-02-08 Semiconductor Components Industries, L.L.C. Method of forming a leadframe for a semiconductor package
US7026711B2 (en) * 2003-12-16 2006-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)
US7880282B2 (en) * 2003-12-18 2011-02-01 Rf Module & Optical Design Ltd. Semiconductor package with integrated heatsink and electromagnetic shield
US7198987B1 (en) 2004-03-04 2007-04-03 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated EMI and RFI shield
US7432586B2 (en) 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US7482686B2 (en) 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US7411281B2 (en) 2004-06-21 2008-08-12 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US20060091542A1 (en) 2004-11-03 2006-05-04 Broadcom Corporation Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same
US7271479B2 (en) 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
MY139795A (en) * 2004-11-09 2009-10-30 Freescale Semiconductor Inc Leadframe for a semiconductor device
US20060156080A1 (en) * 2004-12-10 2006-07-13 Texas Instruments Incorporated Method for the thermal testing of a thermal path to an integrated circuit
US7015379B2 (en) * 2005-01-31 2006-03-21 Pioneer Hi-Bred International, Inc. Soybean variety XB57T05
US7598606B2 (en) * 2005-02-22 2009-10-06 Stats Chippac Ltd. Integrated circuit package system with die and package combination
US7566591B2 (en) 2005-08-22 2009-07-28 Broadcom Corporation Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US20070200210A1 (en) 2006-02-28 2007-08-30 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US9299634B2 (en) 2006-05-16 2016-03-29 Broadcom Corporation Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages
US20070273023A1 (en) 2006-05-26 2007-11-29 Broadcom Corporation Integrated circuit package having exposed thermally conducting body
US7808087B2 (en) 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US9013035B2 (en) 2006-06-20 2015-04-21 Broadcom Corporation Thermal improvement for hotspots on dies in integrated circuit packages

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223739A (en) * 1989-09-14 1993-06-29 Kabushiki Kaisha Toshiba Plastic molded semiconductor device having waterproof cap
US5482898A (en) * 1993-04-12 1996-01-09 Amkor Electronics, Inc. Method for forming a semiconductor device having a thermal dissipator and electromagnetic shielding
US5486720A (en) * 1994-05-26 1996-01-23 Analog Devices, Inc. EMF shielding of an integrated circuit package

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