TWI388047B - 積體電路器件封裝體及其裝配方法 - Google Patents

積體電路器件封裝體及其裝配方法 Download PDF

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Publication number
TWI388047B
TWI388047B TW96117389A TW96117389A TWI388047B TW I388047 B TWI388047 B TW I388047B TW 96117389 A TW96117389 A TW 96117389A TW 96117389 A TW96117389 A TW 96117389A TW I388047 B TWI388047 B TW I388047B
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Taiwan
Prior art keywords
die
cap
package
lead frame
leads
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TW96117389A
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English (en)
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TW200814276A (en
Inventor
Sam Ziqun Zhao
Rezaur Rahman Khan
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Broadcom Corp
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Publication of TW200814276A publication Critical patent/TW200814276A/zh
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Publication of TWI388047B publication Critical patent/TWI388047B/zh

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Description

積體電路器件封裝體及其裝配方法
本發明涉及積體電路(IC)器件封裝技術，更具體地說，涉及IC器件無引線封裝中的提高散熱性能和電磁干擾(EMI)遮罩性能的裝置及方法。
積體電路(IC)半導體晶片或晶粒(die)一般封裝在封裝體內或其上，該封裝體與印刷電路板(PCB)或印刷線路板(PWB)相連。通常將在封裝體裝配過程中用於貼裝半導體晶粒的結構框架稱為導線架(leadframe)，其一般由金屬或其他導電材料製成。導線架廣泛地應用于IC封裝中，作為IC晶粒的載體並可作為晶粒和PCB/PWB電子電路之間的互連裝置。導線架包括用於安裝多個IC晶粒的位置。晶粒連接到導線架之後，採用金屬線將IC晶粒的接合焊盤(bond pad)連接到導線架的接合焊盤，接合焊盤有時也稱為接合手指(bond finger)。接著，用塑封料(molding compound)，如熱固性環氧塑膠，將導線架中晶粒所在的位置密封。塑封之後，將密封好的晶片從導線架的支撐框上機械地分離出。如果導線架的一部分從封裝體中露出，則該封裝稱為有引線封裝。相反，如果封裝體引線並未從導線架覆蓋區(footprint)露出，則該封裝稱為無引線導線架式封裝或簡稱為無引線封裝。在無引線封裝中，直線引線或彎曲引線向下和/或往內彎曲，以安裝在PCB/PWB基板上。
一種無引線導線架式封裝體中帶有外露的晶粒託盤(die attach pad，簡稱為DAP)。該外露DAP具有與晶粒貼裝表面相對的可焊接外表面，用於與PCB/PWB焊接在一 起。另一種可選的無引線封裝稱為薄體陣列塑膠封裝(thin array plastic package，簡稱為TAPP)，該封裝體具有多排用於線焊(wire bonding)的外部引線。
目前業內已開發了各種帶有或不帶有導線架的封裝體，並且電氣工業聯盟(electronic industries alliance，簡稱為EIA)、電子器件工業聯合委員會(Joint Electron Device Engineering Council，簡稱為JEDEC)和日本電氣工業聯盟(electronic industries alliance of Japan，簡稱為EIAJ)已針對各封裝系列的要點(outlines)制定了標準。
然而，目前商用的無引線封裝，其散熱性能有限且EMI遮罩較差。因此，有必要在積體電路封裝中降低EMI敏感性，同時提高散熱和電性能。另外，積體電路封裝中還希望提高環境防護性能。
本發明涉及一種在IC封裝中增強散熱性能和EMI遮罩的方法和裝置。
本發明一方面提供了一種IC器件封裝體，其中包括具有彼此相對的第一和第二表面的封帽(cap)。封帽第二表面的第一部分內部形成一空腔(cavity)。封帽第二表面的平面第二部分連接到DRP。DAP包括中心部(central pirtion)以及連接到DAP中心部的多個連接杆(tie bar)。IC晶粒貼裝在DRA的中心部。封帽和DAP形成密圍結構，以將IC晶粒完全包圍。
本發明另一方面提出了一種IC器件封裝的裝配方法。形成專用于無引線封裝的導線架。將IC晶粒連接到導線架的晶粒託盤的中心部。通過焊線(wire bond)連接IC晶粒和 導線架。將封帽安裝到導線架上。封帽的第二表面內包括空腔。封帽和DAP形成密圍結構，以將IC晶粒完全包圍。採用塑封材料(molding material)密封IC晶粒。切除(trim)導線架的周界支撐環。將引線的一部分打彎，以便於引線到電路板的連接。在工作過程中，該密圍結構將IC晶粒產生的熱量散發出去。此外，該密圍結構可遮罩IC晶粒發出的EMI，同時可遮罩封裝體外部向IC晶粒輻射的EMI。
根據本發明的一方面，提供一種積體電路(IC)器件封裝體，包括：帶有接合焊盤(bond pad)的IC晶粒；包圍IC晶粒的密圍結構，其包括：帶有平坦中心部的晶粒託盤，所述中心部具有彼此相對的第一和第二表面；與晶粒託盤中心部相連且從中心部向外延伸的多個連接杆(tie bar)；其中IC晶粒貼裝在晶粒託盤中心部的第一表面；以及帶有空腔和圍繞該空腔的平整邊緣(rim)的封帽，當封帽邊緣連接到晶粒託盤時，空腔面向IC晶粒，從而將IC晶粒包圍；帶有線焊用引線手指的多條引線，所述引線圍繞晶粒託盤周圍至少排列一排；以及塑封材料，用於密封IC晶粒且至少部分地填充所述空腔。
優選地，所述封裝體為晶粒朝上(die-up)或晶粒朝下(die-down)配置。
優選地，所述密圍結構將IC晶粒工作期間產生的熱量向外散發。
優選地，所述密圍結構遮罩IC晶粒發出的電磁干擾，同時遮罩封裝體外部向IC晶粒輻射的電磁干擾。
優選地，所述晶粒託盤和多條引線連接在一起形成導線架，其中有一個或多個周界支撐環或堤壩(dam bar)在結構上連接各引線。
優選地，所述引線以一排以上的陣列方式排列。
優選地，其特徵在於，所述封裝體進一步包括一個或多個與晶粒託盤周圍的連接杆相連的內插導電環(interposer conducting ring)。
優選地，所述晶粒託盤、內插環(interposer ring)和多條引線連接在一起形成導線架，其中有一個或多個周界支撐環或堤壩在結構上連接各引線。
優選地，所述封帽邊緣包括從包圍IC晶粒的空腔向外擴伸的完全平坦的周邊(lip)部分。
優選地，所述封帽與至少一條引線電、熱接觸。
優選地，所述封帽與多條引線中的任意引線電絕緣。
優選地，所述封帽的平坦邊緣的至少一部分被絕緣材料覆蓋。
優選地，與所述封帽相連的晶粒託盤的至少一部分被絕緣材料覆蓋。
優選地，所述多個連接杆中有至少一個連接杆要寬於所述多個連接杆中的其他連接杆。
優選地，所述多條引線中有至少一條引線要寬於所述多條引線中的其他引線。
優選地，所述封帽與至少一個連接杆電、熱接觸。
優選地，所述多個連接杆和所述多條引線位於第一平面(plane)。
優選地，所述多個連接杆位於第一平面(plane)，而所述多條引線位於第二平面。
優選地，所述封帽的平坦邊緣部分通過導熱和導電粘結劑(adhesive)連接到晶粒託盤。
優選地，所述封裝體進一步包括：晶粒託盤上敷有至少一個導電鍍層區(plated area)，且所述導電鍍層區與所述封帽的平坦邊緣部分相接觸。
優選地，所述封帽與所述晶粒託盤電絕緣。
優選地，所述封帽連接到地電位(ground potential)。
優選地，所述封帽連接到電源電位(power potential)。
優選地，所述封裝體進一步包括：從封帽平坦邊緣部分伸出的至少一個突出部(tab)；和在晶粒託盤表面形成的對應於至少一個突出部的至少一個匹配座(receptacle)，其中至少一個突出部與至少一個對應匹配座相連，從而大大提高封帽和晶粒託盤的結構連接性。
優選地，所述多個連接杆和所述多條引線位於第一平面(plane)。
優選地，所述多個連接杆位於第一平面(plane)，而所述多條引線位於第二平面。
優選地，所述封帽的平坦邊緣部分通過導熱和導電粘結劑(adhesive)連接到晶粒託盤。
優選地，所述封裝體進一步包括：晶粒託盤上敷有至少一個導電鍍層區(plated area)，且所述導電鍍層區與所述封帽的平坦邊緣部分相接觸。
優選地，所述封帽與所述晶粒託盤電絕緣。
優選地，所述封帽連接到地電位(ground potential)。
優選地，所述封帽連接到電源電位(power potential)。
優選地，所述封裝體進一步包括：從封帽平坦邊緣部分伸出的至少一個突出部(tab)；和在晶粒託盤表面形成的對應於至少一個突出部的至少一個匹配座(receptacle)，其中至少一個突出部與至少一個對應匹配座相連，從而大大提高封帽和晶粒託盤的結構連接性。
優選地，所述封裝體進一步包括：所述至少一個匹配座中的導熱和導電粘結劑。
優選地，所述至少一個突出部為圓錐形或平截頭形(frustum)或橫向細條形(laterally elongated shape)。
優選地，所述突出部位於所述平坦邊緣部分的角上。
優選地，所述至少一個對應匹配座有通孔、凹孔或邊緣切口的配置方式。
優選地，所述至少一個突出部和至少一個對應匹配座被配置為便於將封帽在預定方向上連接到晶粒託盤。
優選地，所述封裝體進一步包括：至少一條焊線，用於將IC晶粒上的至少一個接合焊盤連接到所述密圍結構，由此所述密圍結構連接到一個電位。
優選地，所述至少一個接合焊盤為接地焊盤(ground pad)，由此所述密圍結構連接到地電位。
優選地，所述封帽具有背向背向空腔的外表面，其中所述外表面的第一部分被塑封材料覆蓋，而所述封帽外表面的第二部分未被塑封材料覆蓋。
優選地，所述塑封材料進一步密封背向空腔的封帽外表面。
優選地，所述封帽具有背向空腔的外表面，其中所述封帽進一步包括：穿透所述封帽的至少一個開口，所述開口在外表面開設並連接到空腔。
優選地，所述穿透封帽的至少一個開口被配置為便於塑封材料流入空腔。
優選地，所述穿透封帽的至少一個開口被配置為便於釋放密封結構內部的空氣壓力。
優選地，所述封帽的周界尺寸與外排引線包圍的平坦區域的周界尺寸完全一致。
優選地，所述封帽的周界尺寸小於外排引線包圍的平坦區域的周界尺寸。
優選地，所述封帽的周界尺寸大於外排引線包圍的平坦區域的周界尺寸。
優選地，所述封帽具有背向空腔的外表面，進一步包括：連接在封帽外表面的散熱器。
優選地，所述封帽具有背向空腔的外表面，其中封帽外表面被配置為連接到基板上，所述基板包括印刷電路板(PCB)和印刷線路板(PWB)。
優選地，所述封裝體進步一步包括用於將封帽外表面連接到基板上的導熱和導電粘結劑。
優選地，所述晶粒託盤的中心部的第二表面暴露在外，以連接到基板上，所述基板包括印刷電路板和印刷線路板的。
優選地，所述封裝體進一步包括用於將晶粒託盤連接到基板上的導熱和導電粘結劑。
優選地，所述封裝體進一步包括：散熱塊，其第一表面連接到晶粒託盤中心部的外露第二表面，其第二表面被配置為連接到基板上，所述基板包括印刷電路板和印刷線路板。
優選地，所述密圍結構和塑封材料為IC晶粒提供環境防護。
優選地，所述密圍結構和塑封材料提供減緩機械衝擊和搖動。
優選地，所述封帽和晶粒託盤由相同材料製成，所述材料包括金屬、金屬合金、鐵磁材料和金屬化聚合體在內。
優選地，所述封帽和晶粒託盤由不同材料製成。
根據本發明的一方面，提供一種裝配積體電路(IC)器件封裝體的方法，其特徵在於，其中包括：(a)採用導電板料形成導線架，該導線架包括：位於其中部的晶粒託盤，所述晶粒託盤包括帶有彼此相對的第一和第二表面的平坦中心部，以及與所述中心部相連並從其中向外延伸的多個連接杆；圍繞晶粒託盤周圍排列成一排或多排的多條引線，其中連接杆將晶粒託盤連接到一條或多條引線；及對應于每排引線的周界支撐環，其將各引線橫向連接在一起；(b)將IC晶粒貼裝到晶粒託盤的中心部；(c)通過形成焊線將IC晶粒的接合焊盤連接到導線架；(d)連接封帽，該封帽具有面向導線架的空腔，將圍繞著空腔的封帽的平坦邊緣部分連接到導線架上，使封帽和導線架形成密圍結構，以將IC 晶粒包圍；(e)使用塑封材料至少將IC晶粒密封；及(f)從導線架上切除周界支撐環。
優選地，同時執行步驟(d)和(e)，並進一步包括：(g1)在步驟(d)之前，將封帽和導線架放到模具中。
優選地，所述方法進一步包括：(g2)在步驟(d)之前，在導線架的部分表面塗敷導熱導電粘結劑。
優選地，所述方法進一步包括：(g3)在步驟(d)之前，在導線架的部分表面塗敷導電材料。
優選地，步驟(d)包括：將封帽的平坦邊緣部分上的突出部連接到導線架上的對應匹配座中，從而大大提高封帽和導線架的連接性。
優選地，步驟(c)包括：連接IC晶粒焊盤和導線架之間的焊線，由此將所述密圍結構電連接到某一電位。
優選地，所述焊盤為接地焊盤，由此將所述密圍結構電連接到地電位。
優選地，步驟(e)進一步包括：利用塑封材料來密封封帽外表面的第一部分，而封帽外表面的第二部分未被塑封材料覆蓋。
優選地，步驟(e)進一步包括：利用塑封材料來密封封帽的外表面。
優選地，步驟(e)進一步包括：利用塑封材料密封導線架的一部分，而導線架表面暴露在外的部分將與封帽相連。
優選地，該方法進一步包括：(g4)形成穿透封帽的開口，該開口開設在封帽的外表面和空腔表面。
優選地，步驟(e)包括：通過所述開口將塑封材料注入到空腔中。
優選地，該方法進一步包括：允許通過開口釋放密圍結構內部的空氣壓力。
優選地，該方法進一步包括：(g5)將散熱器連接到封帽外表面。
優選地，所述密圍結構提供了下述一項或多項功能：在IC晶粒工作期間向外擴散來自IC晶粒的熱量、遮罩IC晶粒發出的電磁干擾(EMI)並遮罩封裝體外部向IC晶粒輻射的EMI、為IC晶粒提供環境防護、以及減緩機械衝擊和搖動。
優選地，步驟(a)進一步包括：形成一個或多個連接到晶粒託盤的連接杆的導體環。
從下面對本發明的具體描述中可更清楚地瞭解其各種優點和創新特徵。請注意，概述和摘要部分提出了一個或多個典型實施例，但並未說明發明者所預期的所有實施例。
本發明涉及在積體電路(IC)封裝中提高散熱性能和電磁干擾(EMI)遮罩性能的方法和裝置。IC晶粒貼裝在DAP上。IC晶粒可按晶粒朝上(die-up)的方式貼裝，即晶粒連接到DRA中遠離基板(如PCB)的那面上。IC晶粒也可按晶粒朝下(die-down)的方式安裝，即晶粒貼裝在DAP朝向基板的那面上。採用焊線(wire bond)將晶粒上的接合焊盤(bond pad)電連接到DAP周圍的引線手指(lead finger)上。請注意，與焊線相連的引線根部區域(base region)稱為“引線手指(lead finger)”。
在無引線IC封裝中，引線並未從其各自根部區域(base region)完全伸出。引線向下彎曲，以便安裝到PCB/PWB 上，進而得到封裝後IC晶粒的緻密足迹(compact footprint)，有時也稱為“IC晶片”。這種類型的封裝稱為“晶片級封裝(Chip Scale Package)”或CSP。CSP可以基於導線架，其中DAP和引線連接在一起形成導線架，且有一個或多個周界支撐環(perimeter support ring)或堤壩(dam bar)在結構上將各引線連接在一起。這種類型的封裝稱為無引線導線架式封裝。無引線導線架式封裝的典型實例包括無引線塑膠晶片載體(Leadless Plastic Chip Carrier或LPCC)和微型導線架封裝(Micro Leadframe Package或MLP)，其中一般只有單排週邊端子(peripheral terminal)。
非導線架式CSP的一個實例為TAPP封裝，其中有多排用於焊線的外部引線。TAPP封裝採用慮及多排外部輸出以及接地或電源內插環的獨特過程來裝配。該封裝體非常薄，平均厚度為0.7mm，且輸入/輸出(I/O)密度與精密球柵陣列(fine pitch Ball Grid Array，簡稱為fpBGA)封裝相當。請注意，可採用適當設計的帶有多排外部引線的導線架來裝配TAPP類型封裝的修改版本，其中每排引線有一個對應的周界支撐環。還可有一個或多個內插(interposer)接地/電源環連接到DAP。
金屬封帽與DAP相連接(如，電連接、結構連接和/或熱連接)，形成密圍結構。採用或不採用導熱和/或導電粘結劑(諸如含有金屬顆粒或薄片的焊料或環氧樹脂)均可實現連接。在一實施例中，封帽與貼裝在導線架上的一條或多條引線上的連接杆相連接。連接杆焊接或熔接到引線上。在另一實施例中，封帽直接連接在引線上。在又一實施例中，封帽連接在DAP上。封帽可連接於DAP、引線和連接 杆中的任意一種、二種或三種之上。封帽上的突出部(tab)與一個或多個熔接引線和/或連接杆上的匹配座(matching receptacle)緊密配合，以改善連接強度和整個結構的強度。
由封帽和導線架形成的密圍結構近似於等電位表面或法拉第籠(Faraday Cage)，其包圍著晶粒和互連導線。密圍結構材料一般是非常好的導熱體且具有相對較強的剛度(例如銅或銅合金C151)。這種密圍結構可以改善EMI遮罩性能、改善IC晶粒的散熱性能、增強封裝剛性、提高對環境(例如機械震動、搖動、衝撞、壓力、溫度、濕度、腐蝕等)的防護性能。
在一實施例中，晶粒和焊線密封在塑封材料中，以提高對環境的防護性能。塑封料可以將封帽全部覆蓋住。在另一實施例中，封帽被塑封材料部分覆蓋，或者也可以不覆蓋。
在C.A.HARPER，Electronic Packaging and Interconnection Handbook,3rd edition,McGraw-Hill,NewYork,pp.7.61-7.67,2000中討論了不同系列的基於導線架的有引線封裝和無引線封裝，在本申請中全文引用。
一般用塑膠塑封材料密封的導線架式封裝體(其中一個實例就是塑膠方形扁平封裝(Plastic Quad Flat Pack，簡稱為PQFP))表現出較差的散熱性能，因為在DAP和引線之間沒有連續的散熱路徑。IC晶粒的活動表面所產生的熱量主要通過封裝體的上表面和下表面散出。導線架將部分熱量傳導到與封裝體相連的PCB/PWB。密封IC晶粒的塑封材料通過各種對流路徑或輻射路徑將部分熱量傳送到周圍環境中。一般塑封材料的導熱係數較低，如介於0.2~0.9 W/m.K 之間或左右。因此，傳統導線架式封裝中的塑封材料就成了將熱量從晶粒散出到封裝體外表面和熱引線的主要瓶頸。
通過將DAP暴露在塑封材料的底面之外，可以改進有引線和無引線導線架式封裝體的散熱性能。
圖1A和1B分別是帶有外露DAP的有引線PQFP封裝體100的側視圖和仰視圖。封裝體100包括IC晶粒150、DAP 140、焊線130、塑封材料120、粘結劑170和封裝引線180。DAP 140和封裝引線180可作為導線架的一部分。利用粘結劑170將IC晶粒150貼裝在DAP 140上。塑封材料120密封IC晶粒150和焊線130。焊線130將IC晶粒150上的接合焊盤(bond pad)連接到封裝體引線180。如圖1所示，其他焊線130位於IC晶粒和DAP 140之間，以及位於DAP 140和引線180之間。DAP 140至少有一部分外表面暴露在外。包覆在DAP 140外露表面的導熱焊料/粘結劑將封裝體100接合到PCB/PWB 160。PCB/PWB 160作為該封裝體的散熱器，因為在晶粒150活動表面產生的熱量將散出到具有極低熱阻的PCB/PWB 160中。這種類型的封裝稱為“託盤外露薄體四方扁平封裝(Exposed Pad Thin Quad Flat Pack，簡稱為eTQFP)”。
圖2A和2B分別是帶有外露DAP的無引線導線架式封裝體200的側視圖和仰視圖。封裝體200包括IC晶粒150、DAP 140、焊線130、塑封材料120、粘結劑170和封裝引線280。DAP 140和封裝引線280可作為導線架的一部分。利用粘結劑170將IC晶粒150貼裝在DAP 140上。塑封材料120密封IC晶粒150和焊線130。包覆在DAP 140的至 少一部分外表面的導熱焊料/粘結劑將封裝體200接合到PCB/PWB 160。這種類型的封裝稱為“微型導線架封裝(Micro Leadframe Package，簡稱為MLP)”，還可稱為“四方扁平無引線”或QFN封裝，因為封裝體導線280並未露在封裝體外面。封裝引線280在DAP 140四周。一般地，在無引線封裝中，如封裝體200，只有一排外部引線。焊線130將引線280連接到IC晶粒150的接合焊盤(bond pad)。DAP 140可連接到地電位(接地)或特定電位。
圖3A和3B分別是帶有外露DAP 140的無引線TAPP型封裝體300的側視圖和仰視圖。封裝體300包括IC晶粒150、DAP 140、焊線130、塑封材料120、粘結劑170、內插環(interposer ring)390和封裝引線385。包覆在DAP 140外表面的導熱焊料或粘結劑將封裝體300接合到PCB/PWB 160。引線385以多於一排的方式圍繞在DAP 140四周，形成了輸出引線陣列。焊線130將引線385連接到IC晶粒150的對應接合焊盤(bond pad)。多排封裝引線增強了封裝電路的I/O密度。此外，封裝體中可包括一個或多個內插環390。內插環390一般連接到地電位(接地)。請注意，內插環390並不是必須接地，它也可連接到特定電位。TAPP封裝具有獨特的裝配過程。不過，如前所述，如果導線架設計修改為包括內插環和多排外部引線，則TAPP類型的封裝可以基於導線架的裝配過程。
儘管上述封裝在散熱性能方面有所增強，但它們的電磁干擾(EMI)遮罩性能仍然較差。導體中承載的電流在發生變化時將產生電磁波輻射。這些電磁波以光速在空間傳播，如果這些電磁波是不希望有的，則稱為EMI。電流變 化率相對較低時，將輻射出少量的長波低頻電磁波。而當電流變化率相對較高時，將輻射出大量的短波高頻電磁波。這些不希望有的高頻電磁輻射有時稱為射頻干擾(RFI)，但為了簡便起見，本申請中將所有不希望有的電磁輻射都稱為EMI，而不管其頻率高低。
IC晶粒150更容易受到較高頻EMI的影響。因為高頻EMI的能量更大，它們可能在IC晶粒的金屬線路上產生較大的電壓波動。由於現在的IC門尺寸很小，並且用低信號電壓進行操作。因此，高頻EMI產生的信號線電壓波動可能導致其邏輯狀態的變化，從而導致電子器件的定時和邏輯錯誤。
塑封材料120對電磁輻射而言通常是透明的。如圖1A所示，晶粒150產生的電磁輻射會泄漏出封裝體100並可能干擾鄰近元件的操作。相反地，鄰近元件的EMI也將進入封裝體100，且可能干擾晶粒150的操作。
為了解決散熱和EMI問題，已經考慮了各種封裝配置。圖4給出了BGA封裝的實例示意圖，該封裝提高了散熱性能，並在EMI遮罩方面略有改進。圖4給出了BGA封裝體400的橫截面視圖，其中IC晶粒150通過粘結劑170貼裝在印刷電路基板410上。焊線130和IC晶粒150被塑封材料120所密封。IC晶粒150通過焊球(solder ball)430與PCB/PWB 160電連接。BGA封裝體400包括內裝式散熱器(drop-in heat spreader)425，用於加快塑封材料120內的熱量散出。不過，封裝體400中不允許IC晶粒150與散熱器425直接接觸。相應地，IC晶粒150產生的熱量必須通過塑封材料120才能到達散熱器425，因此可能有部分熱 量殘留在BGA封裝體400中。此外，如果有遮罩作用，內裝式散熱器425也只能提供有限的EMI遮罩。例如，BGA封裝體400外部產生的EMI可能穿過印刷電路基板410並干擾IC晶粒150的操作。同樣地，IC晶粒150產生的EMI也可能通過印刷電路基板410中的金屬開口或缺口泄漏出BGA封裝體400。
在各種參考文獻中討論了不同類型的散熱器設計。如專利號為5,977,626，名稱為“Thermally and Electrically Enhanced PBGA Package”，發明人為Wang等的美國專利，專利號為6,552,428，名稱為“Semiconductor Package Having An Exposed Heat Spreader”，發明人為Huang等的美國專利，公開號為20030057550-A1，名稱為“Ball Grid Array Package Enhanced with a Thermal and Electrical Connector”的美國專利，公開號為2005-0280127 A1，名稱為“Apparatus And Method For Thermal And Electromagnetic Interference(EMI)Shielding Enhancement In Die-Up Array Packages”的美國專利，所有這些參考文獻都在本申請中全文引用。
各種參考文獻中也提出了多種EMI遮罩設計。如U.S.Patent專利號為5,294,826，名稱為”Integrated Circuit Package and Assembly Thereof for Thermal and EMI Management”的美國專利和專利號為5,650,659，名稱為”Semiconductor Component Package Assembly Including an Integral RF/EMI Shield”的美國專利，這兩個參考文獻都可在本申請中全文引用。
商用的導線架式封裝體中的集成散熱器，或者是安裝 在正對著DAP的背面(如內裝式散熱器MQFP封裝)，或者是移去導線架中的DAP並將其替換成可貼裝IC晶粒的集成散熱器。IC晶粒與集成散熱器一起封裝。這些集成散熱器在提高散熱性能時，卻無法提供針對電磁干擾(EMI)的保護。此外，集成散熱器在結構上完全位於晶粒背面。為了將集成散熱器暴露在封裝體頂部以連接外部散熱器，必須使用晶粒朝下的導線架式封裝。如果IC晶粒最初按照傳統的晶粒朝上的方式封裝，而隨後又要添加暴露在封裝體頂部的內裝式散熱器，為了能與管腳輸出匹配，就必須重新設計IC晶粒。因此，需要有一種健壯的內裝式散熱器集成方法，為IC晶粒提供EMI遮罩並可用於晶粒朝上和晶粒朝下這兩種導線架式封裝。
本發明將內裝式散熱器很容易地集成到基於導線架的無引線封裝和TAPP型無引線封裝中，僅可採用晶粒朝上也可採用晶粒朝下配置。在下面部分，將詳細討論無引線封裝中的主要部件，如封帽以及無引線導線架。
本部分將討論改進後的散熱器封帽的結構實施例。從其中的啟示得出其他實施例對本領域技術人員而言是顯而易見的。在此所述的封帽結構實施例的各部件可按任何方式進行組合。
根據本發明實施例，圖5A示出了封帽510的橫截面示意圖。圖5B示出了封帽510的仰視圖。封帽510可集成到各種積體電路封裝體中，如圖7A-7F所示，下文將對其進行詳細說明。該封裝體可集成導線架，如圖6A-6C所示，下面將對其進行詳細說明。
封帽510包括頂部590、側壁592和沿著封帽510底部 的四周向外延伸的邊緣594。應注意，“頂部”和“底部”的說法只是為了便於說明，而不是說本發明將限於某特定空間方向。
側壁592將頂部590和邊緣594連接(如，電連接、結構連接和熱連接)在一起。此外，側壁592從頂部590開始向外傾斜。儘管圖5A中所示的頂部590為平面形，頂部590也可為非平面形的(如，為曲面、凹面、凸面、球面或其他形狀)。此外，儘管圖5A和5B示出了向外傾斜的側壁592，側壁592也可為垂直的或從頂部590向內傾斜。此外，側壁592的橫截面不限於直線形，如本領域的技術人員應當知曉，也可以是其他的橫截面形狀，諸如向內彎或向外彎的曲線形。
封帽510進一步包括第一表面580(外表面)和第二表面585(內表面)。第二表面585構成封帽510的底部中的空腔(cavity)570的上邊界。邊緣594圍繞著空腔570。圖5A所示的空腔570的橫截面為梯形，但也可為其他形狀(如，正方形、長方形、不規則形狀等)。儘管圖5B所示空腔570為圓形，空腔570還可為其他形狀。另外，封帽510可以為各種形狀，諸如圓形、矩形、方形、橢圓形、卵形或其他任何形狀。
在封帽510中，邊緣594的周邊部分是完全平坦的。邊緣594周邊(lip)部分的底面設有一個或多個突出部515a-e。突出部515a-e可為任何形狀。例如，圖5A和5B示出了平截頭形突出部515a、圓錐形突出部515b、圓錐形突出部515c和515d形成的突出部對517和長方形突出部515e。封帽510並不限於所示突出部515的形狀、尺寸、 位置或數量。封帽510可具有零個或多個任意形狀、任意尺寸、位於任意位置的突出部。
優選地，封帽510的週邊尺寸等於或小於外排引線所包圍的平坦區域的週邊尺寸，以便於檢查與PCB/PWB相連的引線。在另一實施例中，封帽510的週邊尺寸超出外排引線所包圍的平坦區域的週邊。從製造角度考慮，封帽510的週邊尺寸最好小於導線架周界支撐環630的尺寸(如，請參見圖6A，下面將進行說明)。儘管所示封帽510具有特定尺寸，本領域技術人員應知曉，可採用其他尺寸的封帽。
在一實施例中，封帽510可配置為安裝有外部散熱器。在另一實施例中，封帽510可配置為熱連接和/或電連接到PCB/PWB。
封帽510可由導熱材料和/或導電材料製成，如金屬。例如，用於製造封帽510的材料可包括銅、銅合金(如，C194、C151、C7025或EFTEC 64T)、鋁、鋁合金、鐵磁性材料、銅箔或鐵箔等。還可使用其他金屬或金屬/合金組合物，或其他導熱和導電材料(如，陶瓷、鍍金屬塑膠、覆有金屬箔的塑膠或陶瓷等)。封帽510和DAP 140可由相同或不同的材料製成。當封帽510由相同材料製成時，或者由熱膨脹係數相同的材料製成時，可提高結構完整性，如減小晶粒(夾在封帽和導線架中間)上的熱應力。此外，封帽510的厚度根據具體應用而定，可以是任意厚度。例如，封帽厚度可介於0.1-0.5mm。可選地，封帽510的厚度可小於1.0mm。
邊緣594周邊部分的底面或部分底面塗敷或壓制有絕緣材料層(如，阻焊層(solder mask)、絕緣膜等)。這樣，可避免封裝體在裝配後發生引線短路。
在一實施例中，封帽具有貫穿第一表面580和第二表面585的開口。例如，圖5C和5D示出了封帽511，其中在側壁592形成了開口或狹槽520。儘管圖5C和5D所示的側壁592中的狹槽520為方形或梯形，狹槽520還可為其他形狀。
在另一實施例中，圖5E示出了封帽512在頂部590具有洞孔/開口530。封帽512可開設任意數量的洞孔。此外，洞孔530可為任意形狀。
在製造過程中，封帽512中的洞孔530和封帽511中的狹槽520允許塑封材料120流入空腔570中。另外或者可選地，狹槽520和洞孔530可釋放在空腔570中形成(在製造中或製造後)的壓力。由於較小的洞孔530和狹槽520需要更高的壓力將塑封材料120流入或注入空腔570，因此，從製造角度出發就希望有較大的洞孔530和狹槽520。然而，為了降低EMI的穿透，則希望能限制洞孔530和狹槽520的尺寸。洞孔530和狹槽520的尺寸可介於0.5-3.0mm的範圍。直徑為1.5mm的洞孔可遮罩10GHz左右的最高諧波頻率的EMI。封帽510的外表面可完全或部分密封在塑封材料120中，或者不用塑封材料120覆蓋。
如圖5F所示，封帽510+ 的內表面(第二表面585)可連接有導熱塊586，用於減小散熱器封帽和IC晶粒150頂部表面之間的距離。導熱塊586還可連接到IC晶粒150的頂部表面的中心區域，並離開IC晶粒150的週邊接合焊盤。 導熱塊可為任何形狀，且可由包括銅、鋁、金屬合金、矽等材料在內的任意材料製成。當封帽510+ 由連接到IC晶粒150的導熱塊586支撐時，封帽510+ 可懸挂著而不與DAP、DAP擴展部(如連接杆(tie bar))或封裝引線相連。
本部分說明導線架結構的實施例。如前所述，無引線封裝可基於導線架也可不基於導線架。從其中的啟示得出其他實施例對本領域技術人員而言是顯而易見的。在此所述的導線架實施例的各部件可按任何方式進行組合。
圖6A-6C示出了各種導線架結構。圖6A給出了導線架600，其中包括具有中心部605的DAP 604和多個連接杆(tie bar)620。導線架600還包括多條引線607和周界支撐環630。DAP中心部605類似於圖1A中的外露DAP 140。圖6A中，導線架600為矩形，圍繞其週邊的是矩形周界支撐環630。周界支撐環630包括相互連接為矩形環的第一周界邊緣或堤壩(dam bar)634a，第二周界邊緣或堤壩634b，第三周界邊緣或堤壩634c和第四周界邊緣或堤壩634d。請注意，堤壩634a-634b可為單獨橫條(bar)，可以連接成環狀也可不連接成環狀。DAP中心部605位於導線架600的中心。DAP中心部605可為方形。在圖6A實施例中，連接杆(tie bar)620從DAP中心部605的四個角上向外延伸。
引線607從周界支撐環630向內垂直延伸。引線607a-7連接到連接杆620。引線607a連接在導線架600的邊緣634a和連接杆620a之間。引線607b連接在導線架600的邊緣634a和連接杆620b之間。引線607c連接在導線架600的邊緣634b和連接杆620b之間。引線607d連接在導線架600的邊緣634b和連接杆620c之間。引線607e連接 在導線架600的邊緣634c和連接杆620c之間。引線607f連接在導線架600的邊緣634c和連接杆620d之間。引線607g連接在導線架600的邊緣634d和連接杆620d之間。引線607h連接在導線架600的邊緣634d和連接杆620a之間。引線607由導線架600中的周界支撐環630支撐。引線607(除了引線607a-h之外)可能有一部分位於周界支撐環630中，與導線架600的中心成放射狀角度。
儘管圖6A-6C示出的導線架、DAP中心部605和周界支撐環630均為方形，但還可使用其他形狀(如，矩形、圓形、橢圓、曲線矩形(curvilinear rectangle)等)。此外，引線607的數量也並不限於圖6A所示，導線架可有任意數量的引線607。
圖6B示出了導線架600實施例601。可加寬連接杆620，且可位於沿著DAP中心部605的其他位置，如圖6B所示。連接杆上可熔接任意數量的引線607，這將進一步地有效加寬連接杆。圖6B給出了連接在DAP中心部605和第一及第二引線607x及607y之間的連接杆640。導線架601可有一個或多個熔接連接杆引線620、加寬熔接引線640，或者兩者兼而有之。可選地，導線架601可以既沒有加寬熔接引線640也沒有熔接連接杆引線620。此外，如圖6B所示，導線架601可有一個或多個未連接引線607的連接杆610。
在圖6C所示的另一實施例602中，連接杆602a-d上設有匹配座615。匹配座615對應于封帽中形成的突出部515(如圖5A所示)。匹配座615包括矩形匹配座615a，圓錐形匹配座615b和615c形成的匹配座對617、圓形匹配座 615d和615e形成的匹配座對619和圓形匹配座615f。不過，匹配座615並不限於這些形狀和形狀、數量、位置或尺寸的組合。匹配座615可以是凹孔(未完全穿透導線架602)，也可以是通孔(完全穿透導線架602)。導線架602可以有任意數量的具有任意尺寸、形狀和位置的匹配座615。導線架602中的匹配座615被配置為與封帽510中的突出部515相連，以增強結構強度，同時增強熱連接和電連接。
導線架的材料包括金屬，如銅、銅合金(如，C194、C151、C7025或EFTEC 64T)、鋁、鋁合金、鐵磁性材料、其他金屬或金屬/合金組合物，或其他導熱和導電材料。封帽510和導線架600可由相同或不同的材料製成。根據應用的不同，導線架600可為任意厚度。例如，導線架600的厚度可介於0.05mm到0.5mm之間。在另一實施例中，導線架600的厚度小於1.17mm。
在一實施例中，導線架600為IC封裝體提供了加強(stiffening)和/或結構支撐。在另一實施例中，導線架600為IC封裝體提供了熱擴散渠道。在又一實施例中，導線架600具有導電性，可作為IC封裝體的電源平面(power plane)或接地平面(ground plane)。根據特定應用的要求，導線架600可配置為可提供加強、散熱和導電的任何組合。
本部分說明IC封裝體的實施例。從其中的啟示得出其他實施例對本領域技術人員而言是顯而易見的。在此所述的導線架實施例的各部件可按任何方式進行組合。
圖7A示出了安裝在PCB/PWB上的IC封裝體702。封裝體702包括IC晶粒150、焊線130、塑封材料120、粘結劑170、導線架600和封帽510。導線架600包括DAP中 心部605、連接杆620(圖中未示出)和引線607。貼裝在DAP中心部605的IC晶粒150採用晶粒朝上的配置方式。封帽510正對著晶粒150。導線架600和封帽510形成了完全包覆IC晶粒150的密圍結構720，增強了結構完整性、EMI遮罩性能、散熱性能和環境(如機械撞擊、搖動、腐蝕、濕度和輻射)防護性能。請注意，DAP中心部605還可連接更多的IC晶粒和/或其他電子器件。
封帽510和導線架600可由銅或銅合金製成。銅的熱傳導係數(大約為390W/m.K)遠大於一般的塑封材料120(0.2-0.9 W/m.K)。因此，晶粒150產生的熱量通過粘結劑170傳到DAP中心部605，並通過連接杆620(圖7A中未示出)、封裝引線607和封帽510傳到封裝體外部。另外，由於封帽510和導線架600電連接在一起，它們可形成近似等電位表面，這樣該密圍結構就近似於理想“法拉第籠(Faraday Cage)”。在這種情況下，晶粒150與外部EMI隔離。此外，還可為外部設備遮罩晶粒150產生的EMI。由於與塑封材料120使用的一般固化塑封材料(大約為25GPa)相比，銅和銅合金具有高得多的彈性係數(大約為125GPa)，本發明的實施例採用銅，可提供更好的結構剛性和環境防護性能。
在一實施例中，封帽510和導線架600不採用突出部和匹配座而連接在一起。在另一實施例中，如圖7A所示，封帽510具有適合導線架600中的對應匹配座(類似於匹配座615，圖中未示出)的突出部515。突出部515和導線架600中的對應匹配座有助於將封帽510鎖緊到導線架600中。進一步地，突出部515和導線架600中對應匹配座的 配置方式使得封帽510只能在一個方向正確裝配到導線架上，以便於裝配。請注意，在可選實施例中，封帽510中可有與導線架600中的突出部互鎖的匹配座。
導熱和/或導電粘結劑材料(如，填充有銀薄片或其他傳導微粒的環氧樹脂)可用于加強封帽510和導線架600之間的連接性。粘結劑材料可用於粘合突出部515和導線架600中的對應匹配座。可選地，粘附材料可用于封帽510與導線架600相接觸的地方。通過諸如焊料塗敷和回流焊，或焊料絲網印刷和回流焊等工藝(through processes such as solder plating and reflow or screen printing of solder paste and reflow)，可採用錫焊料或銀焊料來連接封帽510和導線架600。在另一實施例中，可採用焊接或其他金屬連接方式將封帽510接合到導線架600。
導線架600可鍍上一層傳導材料以增強熱連接和電連接。在一實施例中，封帽510安裝在導線架600的DAP中心部605上。在另一實施例中，封帽510安裝在連接DAP中心部605和封裝引線607的連接杆620上。在又一實施例中，如圖7A所示，封帽510安裝在一個或多個引線607上。封帽510可安裝在DAP中心部605、連接杆620和引線607的任何組合上。此外，封帽510邊緣594的部分底面或全部底面可塗敷有絕緣材料層(如，阻焊層、絕緣膜等)，以避免與一條或多條引線607短路。在一個實施例中，封帽510可能與導線架600沒有物理上的接觸。在另一實施例中，當採用焊接或其他金屬連接方法來接合封帽510和導線架600時，封帽510和導線架600間的接觸面完全平坦且光滑。
導線架600的引線607被製造成一定形狀以連接到PCB/PWB 160。例如，從封裝體702延伸出的引線607外面部分向下彎曲，使引線607與PCB/PWB 160接觸。
在密圍結構中填充塑封材料，如圓頂封裝體(glob top)或塑封料，可增強IC封裝體的結構剛性和平整性。例如，塑封材料和密圍結構的組合可以降低IC晶粒裂化和分層。在密圍結構中填充塑封材料還可提高環境防護性能。例如，集成封裝體可對機械壓力、撞擊、搖動、化學腐蝕、濕度、熱照(heat exposure)、輻射等進行防護。
此外，將IC晶粒直接連接到密圍結構可增加晶粒支撐力度(mass)，同時有助於降低微噪效應(microphonics)。IC晶粒的金屬痕量(trace)具有電阻、電容和電感。進行IC封裝並將封裝體裝配到PCB/PWB之後，該IC晶粒處於機械應力之下。搖動、機械撞擊或溫度的突然變化可能導致IC晶粒內的應力分佈發生變化，從而改變電容和電阻，進而產生電壓波動或漂移，這一現象稱為微噪效應。將半導體晶粒直接連接到密圍結構上，可增加該力度，有助於減緩這些機械撞擊和搖動，進而降低微噪效應。
一般的塑封材料，如塑膠塑封材料，其熱傳導係數較低(如，約為0.2-0.9 W/m.K)，因此成為傳統IC封裝體中的散熱瓶頸。該密圍結構通過提供從IC晶粒底面到封裝體外表面的熱傳導路徑，可消除這一瓶頸。此外，該密圍結構可由具有較高熱傳導係數(如，約為390 W/m.K的銅)的材料支撐，因此可加快散熱。
由封帽510和導線架600形成的密圍結構可用許多不同的配置方式集成到IC封裝體中。圖7A-7F示出了本發 明的幾個實施例，每個實施例給出了一種密圍結構。例如，在圖7A中，封帽510與導線架600相連以形成密圍結構720。密圍結構720完全包覆IC晶粒150。在圖7A-7F所示的封裝體中，至少有一條焊線130將IC晶粒150表面的至少一個接合焊盤(bond pad)(圖中未示出)連接到導線架600。連接到導線架600的IC接合焊盤可為接地焊盤(ground pad)。
如圖7A所示，封帽510的頂部表面590從密封封裝體702的塑封材料120中露出。因此，塑封材料120並沒有完全覆蓋第一表面580(封帽510的外表面)。第二表面585(封帽510的內表面)被塑封材料120覆蓋。
圖7B中的封裝體704和圖7C中的封裝體706與圖7A中的封裝體702類似，不過給出了與導線架600中的引線607相關的連接杆620的相對位置(圖7A中未示出)。圖7B示出的導線架600中連接杆620與引線607處於同一平面。連接杆也可位於與引線不同的平面上。如圖7C所示，連接杆621位於引線607上。
圖7D示出了與圖7A中封裝體702類似的IC封裝體708。不過，在IC封裝體708中，封帽510被配置成安裝有外部散熱器。導線架600和封帽510提供了一條供熱量從晶粒150傳導到散熱器701的路徑，進而可散出到封裝體708外。在封裝體708中，封帽510的第一和第二表面580和585都未被塑封材料120覆蓋。在IC封裝體708中，在裝配過程中，使用了塑封材料120之後才將封帽510添加到封裝體中。
與封裝體702類似，封裝體710可包括封帽511，而不 是不帶開口的封帽510。如圖7E所示，封帽511有一個或多個開口(如，狹槽520)。這些開口可作為塑封材料入口，以使塑封材料120流入或注入到空腔570中。在封裝體710中，封帽511的第一表面580和第二表面585均被塑封材料120覆蓋。
圖7F示出了封裝體712，它是圖7A所示封裝體702的等價TAPP版本。由於TAPP類型封裝的特性，引線385可按陣列方式圍繞著DAP 140排列，其中多排而不是單排。焊線130用於將IC晶粒150的接合焊盤連接到引線385。帶有突出部515的封帽510可連接到最外一排引線385。DAP 140周圍可有一個或多個插入環390。封帽510和DAP 140可為包覆IC晶粒150的密圍結構的一部分。在一個實施例中，DAP 140、插入環390和引線385可相互連接構成導線架。接合圖7B-7E所述的各種封裝結構也適用于TAPP封裝體712。
本發明的實施例並不限於晶粒朝上的配置。根據本發明實施例，封裝體可配置為晶粒朝下。與圖7A中的封裝體702相比，封帽510的表面580可暴露在封裝體的底面外。圖7A-7F示出的實施例所反映的特徵也適用於晶體朝下的配置。在晶粒朝下的封裝體中，封帽510的外露表面580可用導熱和/或導電接合劑或焊料連接到PCB/PWB 160中。這樣，從IC晶粒150傳出的熱量通過導線架600和封帽510傳導出封裝體進入PCB/PWB 160。封帽510的表面580可電連接到PCB/PWB 160的電源焊盤(power pad)，以提高EMI遮罩和來自封裝體的電傳輸(power delivery)。可選地，封帽510的表面580可電連接到PCB/PWB 160的接 地焊盤(ground pad)，以改進EMI遮罩和從封裝體返回的電流。在晶粒朝下的配置中，封帽510的外表面580可連接熱和/或電連接器，諸如導熱塊，其中該導熱塊將封裝體連接到PCB/PWB。
根據本發明的一個實施例，圖8給出了圖7A所示導線架式封裝體702的裝配步驟流程圖800。本領域技術人員應知曉，可採用這些裝配流程來裝配任意實施例，包括圖7A-7F所示的那些實施例。根據該教導，相關領域技術人員應知曉，圖8中的步驟並不必須按照其顯示順序進行，根據下面的討論，其他操作和結構實施例對於相關領域技術人員是顯而易見的。出於解釋說明的目的，下面將結合圖9A-9G詳細描述這些步驟。圖9A-9D給出了裝配中不同階段的俯視圖，而圖9E-9G給出了截面圖。
流程圖800開始於步驟805。在步驟805中，用板料加工成導線架。導線架材料實例和特性在本文其他地方已經討論。
在步驟810中，將至少一個IC晶粒安裝到導線架的DAP中。
在步驟815中，將各焊線相互連接。
在步驟820中，將封帽安裝到導線架。
在步驟825中，密封該封裝體。
在步驟830中，切除導線架的周界支撐環。
在步驟870中，形成單個封裝體，即，將封裝體從導線架板中切開。
圖9A給出了單個導線架600的視圖。請注意，圖9A-9G中的導線架600具有導線架實施例601和602中所述的特徵。
圖9B示出了包含導線架600陣列的導線架板900的實例。導線架板900中的導線架600通過蝕刻或衝壓工藝製成。
圖9C示出了已完成部分裝配的封裝體910。至少一個IC晶粒150連接到DAP中心部605。焊線130用於將IC晶粒150的接合焊盤連接到導線架600，從而提供了從IC晶粒150到引線607、連接杆620和/或DAP中心部605的電連接。封帽510連接到導線架600。導電和/或導熱粘結材料用於增強封帽510和導線架600直接的連接。封帽510和導線架600連接在一起形成密圍結構，以完全包覆IC晶粒150。封帽510的空腔尺寸應足夠大，以避免封帽510與焊線接觸。
圖9D示出了已完成部分裝配的導線架板920中的部分裝配後的封裝體910。
圖9E示出了在完成流程圖800中的步驟815之後的部分裝配後的封裝體的截面圖。
圖9F示出了在完成流程圖800中的步驟820之後，圖9D的部分裝配的導線架板920的截面圖。
圖9G示出了在完成流程圖800中的步驟825之後，密封導線架板930的導線架式封裝體的截面圖。在步驟825中，密封封裝體。在該步驟中，使用塑封材料密封部分裝配的封裝體910。封裝體910被夾在模具(mold chase)上，使密封該封裝體的塑封料成型。如本文其他地方所述，封 帽的外部周界尺寸小於周界支撐環630的周界尺寸。從而防止塑封材料通過引線607間的缺口溢出。在轉移成型處理期間，支撐環630還可提供夾緊的模具間的氣密性(sealing)。
在步驟830中，切除導線架周界支撐環630進。引線607已經形成電路板安裝的接觸引腳，導線架式封裝體已裝配完畢。例如，從封裝體向外延伸的引線607外側部分可向下彎曲，以允許它們接觸PCB/PWB。
在步驟870中，從導線架板中切下單個封裝體，如圖7A的封裝體702。
根據本發明的另一實施例，圖10示出了積體電路封裝體的形成步驟的流程圖1000。步驟805、810和815與圖8所示的流程圖800相同。不過，步驟1055(將導線架放在模具中)，步驟1060(將封帽放在模具中)和步驟1070(完成密封)與流程圖800不相同。
根據流程圖1000中所示的裝配流程圖，不是在模具外面將封帽510連接到導線架600上，而是在步驟1055和1060中將導線架600和封帽510放在模具中。導線架600夾在上模具和下模具之間，通過將導線架與封帽夾緊，使得到放置在模具中的封帽和導線架上的連接杆或熔接引線相接觸。為了加強封帽和導線架之間的電接觸，在夾緊模具上的部件前，可在導線架的接觸塊上預先放置導電粘結劑(adhesive)，如含有銀片/粉的環氧樹脂。
在步驟1065中，完成封裝體密封。
流程圖1000中的後續裝配步驟與流程圖800類似。
在步驟830中，切除導線架周界支撐環630，在步驟 870中，形成(singulate)單個封裝體，即，從導線架板中切開。
圖11A-11C給出了根據不同於流程圖800和1000中所述的另一裝配處理過程如何裝配封裝體1101(與圖7D中的封裝體708類似，不過沒有外部散熱器701)的示意圖。在該處理過程中，成型步驟之後將封帽510連接到DAP中心部605。圖11A是完全裝配後單個封裝體1101的截面圖。圖11B示出了多個未分開的導線架在同時成型後形成的成型條1103。成型後，各封裝體的部分DAP暴露在外，如四個角上的連接杆。圖11C示出了單個導線架式封裝體1102經過成型處理後且安裝封帽510之前的俯視圖。圖11C示出了單一封裝體1102的外露連接杆。封帽510連接到外露連接杆以形成密圍結構。封帽表面580和585均未被塑封材料120覆蓋。
請注意，當使用包括連接到連接杆或熔接引線的接地/電源內插環的TAPP型導線架時而不是傳統導線架時，可利用類似的裝配處理。
除了前述優點，連接有集成導熱和導電封帽的晶粒託盤提供了各種優點。其中包括：當封帽連接到IC或PCB上的對應接合焊盤時，可容易連接到封裝體的等電位平面(包括地電位)；在非密封塑膠封裝中，減少濕氣對IC表面的影響；可靈活增加或移除集成封帽，而無需更改導線架或TAPP型封裝設計。
儘管上文描述了本發明的各種實施例，但應明白，這些實施例僅為示例而非限制。本領域技術人員應知曉，在不脫離本發明的精神和範圍的情況下，可以對這些特徵和 實施例進行各種改變或等效替換。因此，本發明不受此處所公開的具體實施例的限制，所有落入本申請的權利要求範圍內的實施例都屬於本發明的保護範圍。
100‧‧‧封裝體
120‧‧‧塑封材料
130‧‧‧焊線
140‧‧‧無引線導線架式封裝體中帶有外露的 晶粒託盤(die attach pad，簡稱為DAP)
150‧‧‧積體電路(IC)晶粒
160‧‧‧印刷電路板/印刷線路板(PCB/PWB)
170‧‧‧粘結劑
180‧‧‧封裝引線
200‧‧‧無引線導線架式封裝體
280‧‧‧封裝引線
300‧‧‧無引線TAPP型封裝體
385‧‧‧封裝引線
390‧‧‧內插環(interposer ring)
400‧‧‧球柵陣列(BGA)封裝體
410‧‧‧印刷電路基板
425‧‧‧內裝式散熱器(drop-in heat spreader)
430‧‧‧焊球(solder ball)
510‧‧‧封帽
511‧‧‧封帽
512‧‧‧封帽
515a‧‧‧平截頭形突出部
515b‧‧‧圓錐形突出部
515c、515d‧‧‧圓錐形突出部
515e‧‧‧長方形突出部
517‧‧‧突出部對
520‧‧‧狹槽
530‧‧‧洞孔/開口
570‧‧‧空腔(cavity)
580‧‧‧第一表面
585‧‧‧第二表面
586‧‧‧導熱塊
590‧‧‧頂部
592‧‧‧側壁
594‧‧‧邊緣
600‧‧‧導線架
601‧‧‧導線架
602‧‧‧導線架
604‧‧‧DAP
605‧‧‧中心部
607‧‧‧引線
610‧‧‧連接杆
615a‧‧‧矩形匹配座
615b、615c‧‧‧圓錐形匹配座
615d、615e‧‧‧圓形匹配座
615f‧‧‧圓形匹配座
617‧‧‧匹配座對
619‧‧‧匹配座對
620‧‧‧連接杆(tie bar)
630‧‧‧周界支撐環
634a‧‧‧第一周界邊緣或堤壩(dam bar)
634b‧‧‧第二周界邊緣或堤壩
634c‧‧‧第三周界邊緣或堤壩
634d‧‧‧第四周界邊緣或堤壩
640‧‧‧加寬熔接引線
702‧‧‧密封封裝體
704‧‧‧封裝體
706‧‧‧封裝體
708‧‧‧IC封裝體
710‧‧‧封裝體
712‧‧‧薄體陣列塑膠封裝(thin array plastic package，簡稱為TAPP)封裝體
720‧‧‧密圍結構
900‧‧‧導線架板
910‧‧‧封裝體
920‧‧‧導線架板
930‧‧‧導線架板
圖1A、1B、2A、2B、3A和3B是各種用於提高散熱性能的DAP外露的IC封裝體的橫截面視圖和仰視圖。
圖4是球柵陣列(BGA)IC封裝的示意圖。
圖5A-5F是根據本發明實施例的封帽的示意圖。
圖6A-6C是根據本發明實施例的導線架的俯視圖。
圖7A-7F是根據本發明實施例的帶有集成散熱器封帽的IC封裝體的橫截面視圖。
圖8是根據本發明實施例的導線架式IC封裝體的裝配步驟流程圖。
圖9A-9D是根據本發明實施例，在裝配過程中導線架式IC封裝體的俯視圖。
圖9E-9G是根據本發明實施例，在裝配過程中導線架式IC封裝體的側視圖。
圖10是不同於圖8所示的導線架式IC封裝體的另一裝配步驟流程圖。
圖11A-11C示出了密封後再將封帽連接到導線架的示意圖。
120‧‧‧塑封材料
130‧‧‧焊線
150‧‧‧積體電路(IC)晶粒
160‧‧‧印刷電路板/印刷線路板(PCB/PWB)
170‧‧‧粘結劑
510‧‧‧封帽
515‧‧‧突出部對
580‧‧‧第一表面
585‧‧‧第二表面
592‧‧‧側壁
594‧‧‧邊緣
600‧‧‧導線架
605‧‧‧中心部
607‧‧‧引線
702‧‧‧密封封裝體
710‧‧‧封裝體

Claims (10)

  1. 一種積體電路(IC)器件封裝體，其特徵在於，包括：帶有接合焊盤的IC晶粒；包圍IC晶粒的密圍結構，其包括：導線架，所述導線架包含：帶有平坦中心部的晶粒託盤，所述中心部具有彼此相對的第一和第二表面；其中IC晶粒貼裝在晶粒託盤中心部的第一表面；多個連接杆，每一連接杆與晶粒託盤相連，其中多個連接杆中之一個連接杆包含至少一個匹配座；以及多個引線從IC晶粒向外延伸，每一引線連接至多個接合焊盤之一個接合焊盤，其中多個連接杆之一個連接杆連接至多個引線之至少兩引線；以及帶有空腔和圍繞該空腔的平整邊緣的封帽，當封帽邊緣連接到晶粒託盤時，空腔面向IC晶粒，從而將IC晶粒包圍；其中所述封帽連接至所述導線架，其中所述封帽從平整邊緣包含至少一個突出部，且其中至少一突出部對具有至少一個匹配座；以及塑封材料，用於密封IC晶粒且至少部分地填充所述空腔。
  2. 如申請專利範圍第1項所述的IC器件封裝體，其中，所述封裝體為晶粒朝上或晶粒朝下配置。
  3. 如申請專利範圍第1項所述的IC器件封裝體，其中，所述密圍結構將IC晶粒工作期間產生的熱量向外散發。
  4. 如申請專利範圍第1項所述的IC器件封裝體，其中，所述密圍結構遮罩IC晶粒發出的電磁干擾，同時遮罩封裝體外部向IC晶粒輻射的電磁干擾。
  5. 如申請專利範圍第1項所述的IC器件封裝體，其中，所述晶粒託盤和多條引線連接在一起形成導線架，其中有一個或多個周界支撐環或堤壩在結構上連接各引線。
  6. 如申請專利範圍第1項所述的IC器件封裝體，其中，所述引線以一排以上的陣列方式排列。
  7. 如申請專利範圍第6項所述的IC器件封裝體，其中，所述封裝體進一步包括一個或多個與晶粒託盤周圍的連接杆相連的內插導電環。
  8. 一種裝配如申請專利範圍第1至7項所述的IC器件封裝體之積體電路(IC)器件封裝體的方法，其特徵在於，其中包括：(a)採用導電板料形成導線架，該導線架包括：位於其中部的晶粒託盤，所述晶粒託盤包括帶有彼此相對的第一和第二表面的平坦中心部，以及與所述中心部相連並從其中向外延伸的多個連接杆；圍繞晶粒託盤周圍排列成一排或多排的多條引線，其中連接杆將晶粒託盤連接到一條或多條引線；及對應于每排引線的周界支撐環，其將各引線橫向連接在一起；(b)將IC晶粒貼裝到晶粒託盤的中心部；(c)通過形成焊線將IC晶粒的接合焊盤連接到導線架；(d)連接封帽，該封帽具有面向導線架的空腔，將圍繞著空腔的封帽的平坦邊緣部分連接到導線架上，使封帽和導線架形成密圍結構，以將IC晶粒包圍；(e)使用塑封材料至少將IC晶粒密封；及(f)從導線架上切除周界支撐環。
  9. 如申請專利範圍第8項所述的方法，其中，同時執行步驟(d) 和(e)，並進一步包括：(g1)在步驟(d)之前，將封帽和導線架放到模具中。
  10. 如申請專利範圍第8項所述的方法，其中，所述方法進一步包括：(g2)在步驟(d)之前，在導線架的部分表面塗敷導熱導電粘結劑。
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US20070267734A1 (en) 2007-11-22
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US8183680B2 (en) 2012-05-22

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