CN112530907A - 一种无源器件堆叠的多芯片封装结构和方法 - Google Patents
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Abstract
本发明提出一种无源器件堆叠的多芯片封装结构和方法,包括金属层、粘接材料、裸芯片、导电金属块、金属过孔、再布线层、外引脚、无源器件、导电粘接材料、环氧模塑料;金属层用于连接无源器件;裸芯片通过粘接材料与金属层粘接;导电金属块设置在裸芯片的有源区表面;再布线层与导电金属块相连;再布线层通过金属过孔或导电金属块与相邻的再布线层、金属层或封装外引脚相连;无源器件包封在环氧模塑料内;导电粘接材料用于实现无源器件与再布线层或金属层的电气信号连接。本发明通过逐层制作再布线层和金属过孔,在环氧塑封料内部进行三维布线,并埋入多颗裸芯片,有利于在单颗封装体内实现更高集成度,外形尺寸更小的设计。
Description
技术领域
本发明涉及芯片设计技术领域,尤其涉及一种无源器件堆叠的多芯片封装结构和方法。
背景技术
随着半导体集成电路关键尺寸的不断缩小,越来越接近硅材料的技术极限,摩尔定律能否得以延续受到了很大的挑战。通过封装技术进行异质集成是延续摩尔定律的途径之一。同时,电子产品的小型化和日益紧张的产品开发周期,对集成电路的小型化和易用性提出了需求。
如传统的电源管理电路里除了直流转直流升降压芯片(DC-DC)和低压差线性稳压器(LDO)以外,还需要外围器件,如:输入、输出电容、电感、调压电阻等。为了进一步降低电源管理电路的物理尺寸,封装体内集成必要外围无源器件的芯片就变得尤为关键。同理,其他电路模块中也有相关类似的需求。
目前业界已有一些无源器件集成技术,如将无源器件埋入到预制的有机基板内,但受制于基板加工工艺的限制,元器件的电参数范围受限。此外,这一技术方案给基板生产厂家从设备投入和技术方面都提出很高的要求。
发明内容
本发明的目的是提供一种半导体集成电路多芯片封装的技术,尤其涉及一种多颗裸芯片共面放置且无源器件层堆叠放置的封装结构和方法。
具体而言本发明提供了一种无源器件堆叠的多芯片封装结构,其特征在于,所述封装结构包括金属层、粘接材料、裸芯片、导电金属块、金属过孔、再布线层、外引脚、无源器件、导电粘接材料、环氧模塑料;
所述金属层通过临时表面设置,用于连接所述无源器件;
所述裸芯片通过所述粘接材料与所述金属层粘接;
所述导电金属块设置在所述裸芯片的有源区表面;
所述再布线层与所述导电金属块相连;同时,所述再布线层通过层间所述金属过孔或导电金属块与相邻的所述再布线层、金属层或封装外引脚相连;
所述无源器件包封在所述环氧模塑料内;
所述导电粘接材料用于实现所述无源器件与所述再布线层或金属层的电气信号连接;
所述环氧模塑料为所述封装结构内各所述再布线层间的介电材料。
更进一步地,所述封装结构包括多个所述裸芯片,所述裸芯片均平铺共面放置。
更进一步地,所述封装结构包括多个所述无源器件,所述无源器件均平铺共面放置。
更进一步地,所述无源器件未包封在所述环氧模塑料内,用于增强散热能力。
还提供了一种无源器件堆叠的多芯片封装方法,其特征在于,所述封装方法包括以下步骤:
步骤S101:在临时支撑平板表面制作一层金属层;
步骤S102:将所述金属层图形的空隙处填充环氧模塑料,并研磨平坦;
步骤S103:在所述金属层上涂覆粘接材料,将裸芯片粘贴到指定的区域;
步骤S104:将所述裸芯片及其有源区表面的导电金属块埋入到所述环氧模塑料内;
步骤S105:在需要制作过孔的位置进行开孔,露出所述金属层;
步骤S106:在所述开孔内镀互连金属,形成金属过孔,并研磨抛光露出所述导电金属块;
步骤S107:在所述导电金属块表面制作再布线层;
步骤S108:将所述再布线层埋入所述环氧模塑料内;
步骤S109:再次在需要制作过孔的位置进行再次开孔,露出所述再布线层;
步骤S110:在所述再次开孔内镀互连金属,形成所述金属过孔;
步骤S111:在表面制作所述再布线层或外引脚;
步骤S112:将所述外引脚埋入到所述环氧模塑料内,并研磨露出所述外引脚的表面;
步骤S113:拆除所述临时支撑平板,通过导电粘接材料将无源器件装配到电所述金属层表面;
步骤S114:将所有器件都包裹到所述环氧模塑料内,进行切割获得无源器件堆叠多芯片封装结构。
更进一步地,在步骤S103中,所述金属层上能够设置多个所述裸芯片,所述裸芯片均平铺共面放置。
更进一步地,在步骤S113中,所述金属层上能够设置多个所述无源器件,所述无源器件均平铺共面放置。
本发明的有益效果是:
本发明的有益效果可以在于,本发明实施例所提供的无源器件堆叠多芯片封装结构,可通过逐层制作再布线层和金属过孔,在环氧塑封料内部进行三维布线,并埋入多颗裸芯片,使得无源器件的堆叠集成得以实现。有利于在单颗封装体内实现更高集成度,外形尺寸更小的设计。
本发明采用临时基板进行封装,最终完成的芯片为无基板封装结构,芯片内部材料仅有塑封料、硅芯片和铜布线;相比现有技术中采用基板进行支撑和封装的芯片结构,最终将基板封装入芯片中的封装结构,解决了由于基板封装结构的内部基板与封装料采用不同材料导致界面分层的问题,提高了封装的可靠性。
附图说明
图1是本发明实施例提供的一种无源器件堆叠的多芯片封装结构的示意图;
图2是本发明实施例提供的一种无源器件堆叠的多芯片封装方法的步骤示意图;
图3至图16是本发明实施例提供的一种无源器件堆叠的多芯片封装方法的流程示意图;
图17是本发明实施例提供的传统引线框架封装体的引线键合区域的超声扫描示意图;
图18是本发明实施例提供的一种无源器件堆叠的多芯片封装结构的超声扫描示意图。
其中,0-临时支撑平板、1-金属层、2-粘接材料、3-裸芯片、4-导电金属块、5-金属过孔、6-再布线层、8-外引脚、9-无源器件、10-导电粘接材料、11-环氧模塑料。
具体实施方式
下面通过实施例,并结合附图1-16,对本发明的技术方案作进一步具体的说明。
如附图1所示,本发明提供一种无源器件堆叠的多芯片封装结构,该封装结构包括:金属层1、粘接材料2、裸芯片3、导电金属块4、金属过孔5、再布线层6、外引脚8、无源器件9、导电粘接材料10、环氧模塑料11;该封装结构采用了以环氧模塑料11为层间介电材料,封装结构内埋入了一颗或多颗集成电路裸芯片3。
其中,金属层1在临时支撑平板0表面通过光刻/电镀/显影去膜等工艺制作;裸芯片3通过粘接材料2与金属层1粘接;导电金属块4设置在裸芯片3的有源区表面;再布线层6与裸芯片3表面的导电金属块4相连,同时,再布线层6通过层间金属过孔5或导电金属块4与相邻的再布线层6、金属层1或封装外引脚8相连;无源器件9集成于封装结构内,该封装结构内至少包含一颗无源器件9(电阻、电容或电感);导电粘接材料10用于实现无源器件9与再布线层6或金属层1的电气信号连接;环氧模塑料11作为封装结构内各金属层1和再布线层6间的介电材料,同时也作为包封无源器件9的重要材料。
在一种实施例中,在无源器件9堆叠的多芯片封装结构中,封装介电材料为环氧模塑料11;封装结构内的所有裸芯片3均平铺共面放置;导电金属块4材质为铜,高度为30μm~70μm;粘接材料2为导电胶、非导电胶或装片膜;封装结构可有多层再布线层6,再布线层6的材质为铜,厚度可为25~100μm;封装结构内的所有无源器件9可以是电阻、电容和电感等器件,它们均共面平铺放置;无源器件9与再布线层6或金属层1之间的导电粘接材料10为锡膏焊料或导电银胶等;无源器件9与裸芯片3之间相对叠层放置,有利于在封装结构内集成更多器件,缩小最终产品的外形尺寸;在无源器件堆叠的多芯片封装结构中,裸芯片3所在的层位于无源器件9与封装结构的底部外引脚层8之间;再布线层间金属过孔5或导电金属块4的材质通常为铜,它们与诸多再布线层共同在塑封体构成了三维多层布线结构。
在另一种实施例中,与上文实施例相比,无源器件9未被环氧模塑料11包封,对于功率器件(尤其是电感)以利于增强散热能力。
如附图2所示,本发明还提供了一种用于提高集成度的无源器件堆叠的多芯片封装结构的制作方法,其包括下列步骤:
如附图3所示,步骤S101:在临时支撑平板0上通过光刻/电镀/显影去膜等工艺在其表面制作一层金属层1,金属层1的图案通过光刻工艺时从掩膜转移而来的,其厚度可通过光刻的厚度及电镀工艺来控制。示意图里该层金属层1有但不限于:无源器件的电气连接焊盘和裸芯片3的装片焊盘等。
如附图4所示,步骤S102:通过第一次模塑封工艺在将金属层1图形的空隙处填充环氧模塑料11,并通过机械研磨工艺进行平坦化。
如附图5所示,步骤S103:在金属层1上装片区域内涂覆粘接材料2,然后通过装片设备将第一个裸芯片3、……、第N个裸芯片3分别粘贴到指定的区域,并固化;封装结构内的所有裸芯片3均平铺共面放置。裸芯片3的表面预制有互连导电金属块4,导电金属块4有多种方式:铜钉、铜柱、金柱等。粘接材料2可以采用导电银胶、非导电胶或装片膜。
如附图6所示,步骤S104:进行第二次模塑封工艺,将裸芯片3及其有源区表面的导电金属块4埋入到环氧模塑料11内。
如附图7所示,步骤S105:通过激光打孔工艺在需要制作过孔的位置进行激光开孔,去除环氧模塑料11,露出过孔位置的金属层1区域。
如附图8所示,步骤S106:通过电镀工艺在孔内镀互连金属,形成金属过孔5。再通过机械研磨抛光进行平坦化,直至完全露出所有裸芯片3上的所有导电金属块4,便于后续工序的开展。
如附图9所示,步骤S107:通过采用与步骤S101中相同的方法,在表面制作一层金属图形,作为再布线层6。
如附图10所示,步骤S108:进行第三次模塑封工艺,从而把第一层再布线层6埋入到环氧模塑料11内。
如附图11所示,步骤S109:通过激光打孔工艺在需要制作过孔的位置再次进行激光开孔,去除环氧模塑料11,露出再次开孔位置的金属区域。
如附图12所示,步骤S110:通过电镀工艺在再次开孔内镀互连金属,形成金属过孔5。
如附图13所示,步骤S111:通过采用与步骤S101中相同的方法,在表面制作一层金属图形,作为第二层再布线层6或外引脚8。根据需要,通过重复步骤S108至步骤S111,可继续增加再布线层6的层数。
如附图14所示,步骤S112:再进行模塑封工艺,从而把外引脚8埋入到环氧模塑料11内,再通过研磨工艺露出所有外引脚8的表面。
如附图15所示,步骤S113:拆除临时支撑平板0,从而得到一个埋入多颗裸芯片3的部分封装结构。通过表面贴装工艺(SMT)用焊料或导电粘接材料10将无源器件9装配到电气连接焊盘所在的金属层1表面,实现与部分封装结构内裸芯片3的堆叠;部分封装结构内的所有无源器件9可以是电阻、电容和电感等器件,它们均共面平铺放置。
如附图16所示,步骤S114:再进行最后一次模塑封工艺,从而把所有器件都包裹在环氧模塑料11内,最终经过切割工序即可完成本发明的无源器件堆叠多芯片封装结构。
本发明中提供的多芯片封装结构采用电镀、塑封、研磨等工艺组合制备采用环氧塑封料作为介电材料的“基板”,与传统封装工艺相比,现有技术中基于BT有机基板或引线框架的产品在塑封工序过程中,由于基板或引线框架表面材质和状态的差异,易形成有空洞或分层缺陷的界面;本发明中提供的多芯片封装结构中“基板”介电材料与塑封体材质相同,更有利于获得无缺陷的基板/塑封体界面;同时,本发明中提供的多芯片封装结构的热膨胀系数(CTE)匹配程度更高,有利于降低芯片的热应力水平,提高封装结构完整性和抗温度循环/热冲击可靠性。
如附图17-18所示,以某款电源管理芯片为例,对分别采用传统引线框架引线键合工艺和本发明中提供的多芯片封装结构的两组样品进行预处理(JESD22-A113,MSL-3)和温度循环(GJB548B方法1010.1试验条件C)50次后,利用超声扫描检测对两组样品内部分层状况进行确认。传统引线框架封装体的引线键合区域发现明显分层(不良率100%),该分层会在温度循环的热应力作用下不断扩展,不利于键合丝的电气连接,影响芯片正常工作;对本发明中提供的多芯片封装结构进行超声扫描检查,在裸芯片互连区域未发现分层。
虽然本发明已经以较佳实施例公开如上,但实施例并不是用来限定本发明的。在不脱离本发明之精神和范围内,所做的任何等效变化或润饰,同样属于本发明之保护范围。因此本发明的保护范围应当以本申请的权利要求所界定的内容为标准。
Claims (7)
1.一种无源器件堆叠的多芯片封装结构,其特征在于,所述封装结构包括金属层(1)、粘接材料(2)、裸芯片(3)、导电金属块(4)、金属过孔(5)、再布线层(6)、外引脚(8)、无源器件(9)、导电粘接材料(10)、环氧模塑料(11);
所述金属层(1)通过临时表面设置,用于连接所述无源器件(9);
所述裸芯片(3)通过所述粘接材料(2)与所述金属层(1)粘接;
所述导电金属块(4)设置在所述裸芯片(3)的有源区表面;
所述再布线层(6)与所述导电金属块(4)相连;同时,所述再布线层(6)通过层间所述金属过孔(5)或导电金属块(4)与相邻的所述再布线层(6)、金属层(1)或封装外引脚(8)相连;
所述无源器件(9)包封在所述环氧模塑料(11)内;
所述导电粘接材料(10)用于实现所述无源器件(9)与所述再布线层(6)或金属层(1)的电气信号连接;
所述环氧模塑料(11)为所述封装结构内各所述再布线层(6)间的介电材料。
2.根据权利要求1所述封装结构,其特征在于,所述封装结构包括多个所述裸芯片(3),所述裸芯片(3)均平铺共面放置。
3.根据权利要求1所述封装结构,其特征在于,所述封装结构包括多个所述无源器件(9),所述无源器件(9)均平铺共面放置。
4.根据权利要求1所述封装结构,其特征在于,所述无源器件(9)未包封在所述环氧模塑料(11)内,用于增强散热能力。
5.一种无源器件堆叠的多芯片封装方法,其特征在于,所述封装方法包括以下步骤:
步骤S101:在临时支撑平板(0)表面制作一层金属层(1);
步骤S102:将所述金属层(1)图形的空隙处填充环氧模塑料(11),并研磨平坦;
步骤S103:在所述金属层(1)上涂覆粘接材料(2),将裸芯片(3)粘贴到指定的区域;
步骤S104:将所述裸芯片(3)及其有源区表面的导电金属块(4)埋入到所述环氧模塑料(11)内;
步骤S105:在需要制作过孔的位置进行开孔,露出所述金属层(1);
步骤S106:在所述开孔内镀互连金属,形成金属过孔(5),并研磨抛光露出所述导电金属块(4);
步骤S107:在所述导电金属块(4)表面制作再布线层(6);
步骤S108:将所述再布线层(6)埋入所述环氧模塑料(11)内;
步骤S109:再次在需要制作过孔的位置进行再次开孔,露出所述再布线层(6);
步骤S110:在所述再次开孔内镀互连金属,形成所述金属过孔(5);
步骤S111:在表面制作所述再布线层(6)或外引脚(8);
步骤S112:将所述外引脚(8)埋入到所述环氧模塑料(11)内,并研磨露出所述外引脚(8)的表面;
步骤S113:拆除所述临时支撑平板(0),通过导电粘接材料(10)将无源器件(9)装配到电所述金属层(1)表面;
步骤S114:将所有器件都包裹在所述环氧模塑料(11)内,进行切割获得无源器件堆叠多芯片封装结构。
6.根据权利要求5所述封装方法,其特征在于,在步骤S103中,所述金属层(1)上能够设置多个所述裸芯片(3),所述裸芯片(3)均平铺共面放置。
7.根据权利要求5所述封装方法,其特征在于,在步骤S113中,所述金属层(1)上能够设置多个所述无源器件(9),所述无源器件(9)均平铺共面放置。
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