CN105552065A - 一种t/r组件控制模块的系统级封装结构及其封装方法 - Google Patents

一种t/r组件控制模块的系统级封装结构及其封装方法 Download PDF

Info

Publication number
CN105552065A
CN105552065A CN201610077040.5A CN201610077040A CN105552065A CN 105552065 A CN105552065 A CN 105552065A CN 201610077040 A CN201610077040 A CN 201610077040A CN 105552065 A CN105552065 A CN 105552065A
Authority
CN
China
Prior art keywords
chip
substrate
package structure
control module
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610077040.5A
Other languages
English (en)
Inventor
马强
王波
唐亮
陈兴国
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 38 Research Institute
Original Assignee
CETC 38 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 38 Research Institute filed Critical CETC 38 Research Institute
Priority to CN201610077040.5A priority Critical patent/CN105552065A/zh
Publication of CN105552065A publication Critical patent/CN105552065A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种T/R组件控制模块的系统级封装结构及其封装方法，具体为通过多种封装手段，将一组用于相控阵T/R组件电压和波形控制的裸芯片，以及若干无源器件进行三维高密度集成的系统级封装结构和封装方法。在封装基板上表面，通过对两个芯片采用金凸点倒装焊和金丝键合的方法进行三维堆叠及塑封，在封装基板的下表面侧，采用低弧度金丝键合对芯片进行连接和塑封，最后在封装基板下表面的四周进行BGA植球。通过该封装结构和封装方法所获得的封装体，能够有效地减小T/R收发组件的尺寸，有利于相控阵雷达的小型化。

Description

一种T/R组件控制模块的系统级封装结构及其封装方法
技术领域
本发明涉及T/R组件结构及封装技术领域，具体来说是一种T/R组件控制模块的系统级封装结构的封装方法。
背景技术
系统级封装是指通过对数字信号、射频、光学、MEMS的协同设计和制造，将多芯片和分立器件等集成于一个单塑封体中，并使该单塑封体具备系统级的功能。
相控阵雷达T/R收发组件的封装方法一般采用MCM(多芯片组件)的结构设计和组装方式进行系统集成。即在LTCC基板表面贴装或引线键合各种有源或无源器件，从而组成一个射频收发系统。这种MCM封装模式对T/R组件的小型化起到了促进作用。然而，这种将有源和无源器件以二维平铺的方式组装于LTCC基板上的封装方法，已经很难使T/R组件的组装密度进一步提高，尺寸进一步缩小。
随着电子技术的迅猛发展，电子设备进一步实现高性能和小型化的主要制约已经不再是元器件本身，而是组装与封装方式。T/R组件作为雷达、通信中关键的分系统，体积、重量、性能、成本和可靠性直接决定了电子整机各个相关指标。基于超大规模集成电路、3D互连、高性能组装和封装技术的快速发展，三维系统级封装将成为未来T/R组件小型化新的驱动力。通过对裸芯片及其相关的无源器件进行高密度的三维堆叠和集成，并形成一个具有系统级功能的小型封装体的做法，可以更加有效地减小器件所占用的MCM基板面积，从而有利于相控阵T/R组件的进一步小型化。
发明内容
本发明针对有源相控阵T/R组件控制电路模块，提出一种高密度的三维堆叠封装结构和封装方法，通过这种系统级封装设计，为相控阵雷达T/R组件的小型化提出了一个可行的实施路径。
本发明是通过以下技术方案来实现上述技术目的：
一种T/R组件控制模块的系统级封装结构，包括基板；所述基板的上表面倒装有第一芯片；在所述第一芯片的两侧的基板上分别焊接有无源器件，所述第一芯片的背面粘接有第二芯片；所述第二芯片与所述基板电性连接；所述基板的下表面粘接有第三芯片；所述第三芯片与所述基板电性连接。其中，芯片与无源器件的个数根据实际情况而定，不局限图1中所示出的个数。
优选的，所述第一芯片采用金凸点倒装焊接在所述基板上。
优选的，所述第二芯片通过引线键合连接至所述基板的上表面。
优选的，所述第三芯片通过引线键合连接至所述基板的下表面。
优选的，对所述基板上表面所堆叠的第一芯片、第二芯片、无源器件进行封装。
优选的，对所述第三芯片进行封装。
优选的，在所述基板下表面四周的焊盘位置，进行BGA植球；BGA焊球高度高于所述第三芯片的封装高度。
一种T/R组件控制模块的系统级封装结构的封装方法，包括以下步骤：
1)在第一芯片的焊盘上进行金凸点植球，并通过超声热压倒装焊设备，将芯片倒装焊接至基板4所对应的焊盘位置；然后对倒装的第一芯片，进行底部填胶保护；
2)通过SMT回流焊，将无源器件焊接在基板表面所对应的焊盘上；
3)采用堆叠芯片胶带，将第二芯片粘接于第一芯片的背面，并通过金丝键合设备，将第二芯片与基板的焊盘进行连接；
4)采用环氧塑封料，通过塑封模具和注塑设备，对基板上表面所堆叠的第一芯片、第二芯片以及无源器件进行注塑，形成上塑封体；
5)通过芯片粘接胶带，将第三芯片粘接与基板的下表面，并通过引线键合，使第三芯片与基板形成互连；
6)采用环氧塑封料，通过塑封模具和注塑设备，对第三芯片进行注塑，形成下塑封体；
7)在基板下表面四周的焊盘位置，进行BGA植球。
优选的，所述步骤5)中采用低弧度金丝键合方法，以此获得较薄的塑封高度。
优选的，所述步骤7)中的BGA焊球高度要高于第三芯片的塑封高度。
本发明与现有技术相比，具有以下有益效果：
本发明针对有源相控阵T/R组件控制电路模块，提出一种高密度的三维堆叠封装结构以及封装方法，通过这种系统级封装设计，为相控阵雷达T/R组件的小型化提出了一个可行的实施路径，且封装结构简单，操作方便。
附图说明
图1为本发明一种T/R组件控制模块的系统级封装结构的结构示意图。
具体实施方式
为使对本发明的结构特征及所达成的功效有更进一步的了解与认识，用以较佳的实施例及附图配合详细的说明，说明如下：
请参见图1，一种T/R组件控制模块的系统级封装结构，包括基板1、第一芯片2、第二芯片3、第三芯片4。在该封装结构中，第一芯片2采用金凸点倒装焊，固定在基板的上表面。第一芯片2两侧的基板1上焊接有无源器件5。第二芯片3则采用芯片粘接胶带，正面朝上，粘接与第一芯片2的背面，并通过引线a键合连接至封装基板1表面。第三芯片4，则直接胶接在基板14的下表面，并通过引线a键合与封装基板1相连。为了对芯片提供保护，对基板1上表面所堆叠的第一芯片2、第二芯片3、无源器件5进行封装，形成上塑封体11，对第三芯片4进行封装，形成下塑封体12。最后在基板1的下表面进行BGA植球。这个过程中要求BGA焊球13的直径要高于下塑封体12的高度。
对于上的T/R组件控制模块的系统级封装结构，其封装方法包括以下步骤：
步骤1.在第一芯片2的焊盘上进行金凸点植球，并通过超声热压倒装焊设备，将芯片倒装焊接至基板14所对应的焊盘位置；然后对倒装的第一芯片2，进行底部填胶保护；
步骤2.通过SMT回流焊，将无源器件5焊接在基板1表面所对应的焊盘上；
步骤3.采用堆叠芯片胶带，将第二芯片3粘接于第一芯片2的背面，并通过金丝键合设备，将第二芯片3与基板1的焊盘进行连接；
步骤4.采用环氧塑封料，通过塑封模具和注塑设备，对基板1上表面所堆叠的第一芯片2、第二芯片3以及无源器件5进行注塑，形成上塑封体11，从而对芯片形成保护；
步骤5.通过芯片粘接胶带，将第三芯片4粘接与基板1的下表面，并通过引线31键合，使第三芯片4与基板1形成互连；
步骤6.采用环氧塑封料，通过塑封模具和注塑设备，对第三芯片4进行注塑，形成下塑封体12，对第三芯片4形成保护；
步骤7.芯片堆叠和塑封完成以后，在基板1下表面四周的焊盘位置，进行BGA植球。
其中，步骤5中采用低弧度金丝键合方法，以此获得较薄的塑封高度。
其中，步骤7中的BGA焊球13高度要高于第三芯片4的塑封高度。
以上显示和描述了本发明的基本原理、主要特征和本发明的优点。本行业的技术人员应该了解，本发明不受上述实施例的限制，上述实施例和说明书中描述的只是本发明的原理，在不脱离本发明精神和范围的前提下本发明还会有各种变化和改进，这些变化和改进都落入要求保护的本发明的范围内。本发明要求的保护范围由所附的权利要求书及其等同物界定。

Claims (10)

1.一种T/R组件控制模块的系统级封装结构，包括基板；其特征在于：所述基板的上表面倒装有第一芯片；在所述第一芯片的两侧的基板上分别焊接有无源器件；所述第一芯片的背面粘接有第二芯片；所述第二芯片与所述基板电性连接；所述基板的下表面粘接有第三芯片；所述第三芯片与所述基板电性连接。
2.根据权利要求1所述的一种TR组件控制模块的系统级封装结构，其特征在于：所述第一芯片采用金凸点倒装焊接在所述基板上。
3.根据权利要求1所述的一种TR组件控制模块的系统级封装结构，其特征在于：所述第二芯片通过引线键合连接至所述基板的上表面。
4.根据权利要求1所述的一种TR组件控制模块的系统级封装结构，其特征在于：所述第三芯片通过引线键合连接至所述基板的下表面。
5.根据权利要求1所述的一种TR组件控制模块的系统级封装结构，其特征在于：对所述基板上表面所堆叠的第一芯片、第二芯片、无源器件进行封装。
6.根据权利要求1所述的一种TR组件控制模块的系统级封装结构，其特征在于：对所述第三芯片进行封装。
7.根据权利要求7所述的一种TR组件控制模块的系统级封装结构，其特征在于：在所述基板下表面四周的焊盘位置，进行BGA植球；BGA焊球高度高于所述第三芯片的封装高度。
8.根据权利要求1所述的一种TR组件控制模块的系统级封装结构的封装方法，其特征在于：包括以下步骤：
1)在第一芯片的焊盘上进行金凸点植球，并通过超声热压倒装焊设备，将芯片倒装焊接至基板4所对应的焊盘位置；然后对倒装的第一芯片，进行底部填胶保护；
2)通过SMT回流焊，将无源器件焊接在基板表面所对应的焊盘上；
3)采用堆叠芯片胶带，将第二芯片粘接于第一芯片的背面，并通过金丝键合设备，将第二芯片与基板的焊盘进行连接；
4)采用环氧塑封料，通过塑封模具和注塑设备，对基板上表面所堆叠的第一芯片、第二芯片以及无源器件进行注塑，形成上塑封体；
5)通过芯片粘接胶带，将第三芯片粘接与基板的下表面，并通过引线键合，使第三芯片与基板形成互连；
6)采用环氧塑封料，通过塑封模具和注塑设备，对第三芯片进行注塑，形成下塑封体；
7)在基板下表面四周的焊盘位置，进行BGA植球。
9.根据权利要求8所述的一种TR组件控制模块的系统级封装结构的封装方法，其特征在于：所述步骤5)中采用低弧度金丝键合方法，以此获得较薄的塑封高度。
10.根据权利要求8所述的一种TR组件控制模块的系统级封装结构的封装方法，其特征在于：所述步骤7)中的BGA焊球高度要高于第三芯片的塑封高度。
CN201610077040.5A 2016-02-01 2016-02-01 一种t/r组件控制模块的系统级封装结构及其封装方法 Pending CN105552065A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610077040.5A CN105552065A (zh) 2016-02-01 2016-02-01 一种t/r组件控制模块的系统级封装结构及其封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610077040.5A CN105552065A (zh) 2016-02-01 2016-02-01 一种t/r组件控制模块的系统级封装结构及其封装方法

Publications (1)

Publication Number Publication Date
CN105552065A true CN105552065A (zh) 2016-05-04

Family

ID=55831158

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610077040.5A Pending CN105552065A (zh) 2016-02-01 2016-02-01 一种t/r组件控制模块的系统级封装结构及其封装方法

Country Status (1)

Country Link
CN (1) CN105552065A (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107622996A (zh) * 2017-09-25 2018-01-23 华进半导体封装先导技术研发中心有限公司 三维高密度扇出型封装结构及其制造方法
CN107946282A (zh) * 2017-11-27 2018-04-20 上海先方半导体有限公司 三维扇出型封装结构及其制造方法
CN109459728A (zh) * 2018-12-12 2019-03-12 中国电子科技集团公司第三十八研究所 一种t/r模块结构及具有该结构的液冷板插件
CN111128994A (zh) * 2019-12-27 2020-05-08 华为技术有限公司 一种系统级封装结构及其封装方法
CN112530907A (zh) * 2020-12-02 2021-03-19 中国电子科技集团公司第十四研究所 一种无源器件堆叠的多芯片封装结构和方法
CN113130454A (zh) * 2021-04-12 2021-07-16 长沙新雷半导体科技有限公司 一种芯片封装装置、电子模组及电子设备
US20220270999A1 (en) * 2021-02-25 2022-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Die attached leveling control by metal stopper bumps
CN113130454B (zh) * 2021-04-12 2024-07-05 长沙新雷半导体科技有限公司 一种芯片封装装置、电子模组及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050087852A1 (en) * 2003-04-22 2005-04-28 Kai-Chi Chen Chip package structure and process for fabricating the same
CN101411077A (zh) * 2006-03-31 2009-04-15 英特尔公司 单封装无线通信装置
US20100270661A1 (en) * 2008-06-04 2010-10-28 Stats Chippac, Ltd. Semiconductor Device Having Electrical Devices Mounted to IPD Structure and Method of Shielding Electromagnetic Interference
CN104183555A (zh) * 2013-05-28 2014-12-03 矽品精密工业股份有限公司 半导体封装件及其制法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050087852A1 (en) * 2003-04-22 2005-04-28 Kai-Chi Chen Chip package structure and process for fabricating the same
CN101411077A (zh) * 2006-03-31 2009-04-15 英特尔公司 单封装无线通信装置
US20100270661A1 (en) * 2008-06-04 2010-10-28 Stats Chippac, Ltd. Semiconductor Device Having Electrical Devices Mounted to IPD Structure and Method of Shielding Electromagnetic Interference
CN104183555A (zh) * 2013-05-28 2014-12-03 矽品精密工业股份有限公司 半导体封装件及其制法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
吴燕红等: "《无线传感网3D-MCM封装结构的设计与实现》", 《功能材料与器件学报》 *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107622996A (zh) * 2017-09-25 2018-01-23 华进半导体封装先导技术研发中心有限公司 三维高密度扇出型封装结构及其制造方法
CN107622996B (zh) * 2017-09-25 2020-10-02 华进半导体封装先导技术研发中心有限公司 三维高密度扇出型封装结构及其制造方法
CN107946282A (zh) * 2017-11-27 2018-04-20 上海先方半导体有限公司 三维扇出型封装结构及其制造方法
CN107946282B (zh) * 2017-11-27 2020-09-01 上海先方半导体有限公司 三维扇出型封装结构及其制造方法
CN109459728A (zh) * 2018-12-12 2019-03-12 中国电子科技集团公司第三十八研究所 一种t/r模块结构及具有该结构的液冷板插件
CN109459728B (zh) * 2018-12-12 2021-04-09 中国电子科技集团公司第三十八研究所 一种t/r模块结构及具有该结构的液冷板插件
CN111128994A (zh) * 2019-12-27 2020-05-08 华为技术有限公司 一种系统级封装结构及其封装方法
CN112530907A (zh) * 2020-12-02 2021-03-19 中国电子科技集团公司第十四研究所 一种无源器件堆叠的多芯片封装结构和方法
US20220270999A1 (en) * 2021-02-25 2022-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Die attached leveling control by metal stopper bumps
US11923331B2 (en) * 2021-02-25 2024-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. Die attached leveling control by metal stopper bumps
CN113130454A (zh) * 2021-04-12 2021-07-16 长沙新雷半导体科技有限公司 一种芯片封装装置、电子模组及电子设备
CN113130454B (zh) * 2021-04-12 2024-07-05 长沙新雷半导体科技有限公司 一种芯片封装装置、电子模组及电子设备

Similar Documents

Publication Publication Date Title
CN105552065A (zh) 一种t/r组件控制模块的系统级封装结构及其封装方法
US6492726B1 (en) Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
CN102867800B (zh) 将功能芯片连接至封装件以形成层叠封装件
US5977640A (en) Highly integrated chip-on-chip packaging
US7429786B2 (en) Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides
US7429787B2 (en) Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides
US7719094B2 (en) Semiconductor package and manufacturing method thereof
US8873245B2 (en) Embedded chip-on-chip package and package-on-package comprising same
US20060043556A1 (en) Stacked packaging methods and structures
US20060284299A1 (en) Module Having Stacked Chip Scale Semiconductor Packages
US20040140552A1 (en) Semiconductor device
US20080237833A1 (en) Multi-chip semiconductor package structure
CN113725153B (zh) 多层多芯片扇出型三维集成封装方法及结构
CN103219324A (zh) 堆叠式半导体芯片封装结构及工艺
CN212303661U (zh) 小型化高密度高效三维系统级封装电路
CN101789420A (zh) 一种半导体器件的系统级封装结构及其制造方法
KR100855887B1 (ko) 스택형 반도체 패키지 및 그 스택 방법
US20060065958A1 (en) Three dimensional package and packaging method for integrated circuits
CN201655787U (zh) 半导体封装结构
CN105304598A (zh) 垂直叠封的多芯片晶圆级封装结构及其制作方法
CN208608194U (zh) 一种半导体双面封装结构
CN104867913A (zh) 多芯片混合集成的三维封装结构及加工方法
CN105742276A (zh) 一种采用三维集成封装的t/r组件的电源调制模块及其封装方法
CN206893608U (zh) 高密度系统级封装结构
KR100729502B1 (ko) 멀티 칩 패키지용 캐리어, 멀티 칩 캐리어 및 그 제작방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160504