CN104183555A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN104183555A
CN104183555A CN201310213682.XA CN201310213682A CN104183555A CN 104183555 A CN104183555 A CN 104183555A CN 201310213682 A CN201310213682 A CN 201310213682A CN 104183555 A CN104183555 A CN 104183555A
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China
Prior art keywords
wiring board
semiconductor package
bearing part
radio frequency
frequency chip
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CN201310213682.XA
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CN104183555B (zh
Inventor
邱志贤
蔡宗贤
杨超雅
陈嘉扬
郑志铭
朱育德
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件，包括：线路板、设于该线路板上的承载件、设于该承载件上的射频芯片、电性连接该电极垫与该线路板的多个高位焊线、以及包覆该承载件、高位焊线与射频芯片的绝缘层。藉由架高该射频芯片，以利于在该线路板上置放组件及高频布线，而达到高度整合无线系统级封装模块的目的。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件的制法，尤指一种能提升产品可靠度的半导体封装件的制法。
背景技术
由于电子产业的蓬勃发展，大部分的电子产品均不断朝小型化、轻量化和高速化的目标迈进，其中更有不少电子产品必须使用射频芯片，例如将射频芯片与数字IC、射频芯片与数字讯号处理器（DigitalSignal Processor,DSP）、或射频芯片与基频芯片（Base Band,BB）等整合在一起，藉以达到小型化或高速化的目标。
现有多芯片封装构造已有许多型态，为达到较小表面接合面积，一般以堆栈方式将多个芯片相互堆栈于一基板上，当采用打线接合的方式电性连接该些芯片与该基板时，将该些芯片的主动面朝上堆栈，以利多个焊线的连接，例如，将一虚芯片（dummy die）设于两相邻芯片之间，或者，以一胶状粘着剂（paste adhesive）或胶膜间隔两相邻的芯片，以提供该些焊线足够的线弧高度。
图1为现有半导体封装件1的剖面示意图。如图1所示，该半导体封装件1包含一线路板10、设于该线路板10上的一射频芯片12、设于该射频芯片12上的一虚芯片11、设于该虚芯片11上的一半导体芯片14、电性连接该半导体芯片14与该线路板10的多个第一焊线140、电性连接该射频芯片12与该线路板10的多个第二焊线13及包覆该虚芯片11、半导体芯片14、第一焊线140、射频芯片12及第二焊线13的封装胶体16，其中，该虚芯片11可提供一间距，以使该第二焊线13具有足够的线弧高度。
然而，该射频芯片12的射频电路为敏感区域（尤其当该射频芯片12为高频率芯片或无线射频芯片时），所以会有干扰（interference）、热量（thermal）等因素影响效能，因而限制布线的灵活度与组件的摆放空间，致使无法实现高整合的无线（wireless）系统级（System inPackage,SiP）封装模块。
此外，该射频芯片12与该半导体芯片14的堆栈会使两者间讯号互相干扰而产生噪声，尤其当该射频芯片12为高频率芯片或无线射频芯片时，对于该半导体芯片14的干扰程度更为严重。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的为提供一种半导体封装件及其制法，以达到高度整合无线系统级封装模块的目的。
本发明的半导体封装件，包括：一线路板；承载件，其设于该线路板上；射频芯片，其设于该承载件上，该射频芯片具有相对的主动面与非主动面，该主动面上具有多个电极垫，且该非主动面结合至该承载件上；多个高位焊线，其电性连接该电极垫与该线路板；以及绝缘层，其设于该线路板上，以包覆该承载件、高位焊线与射频芯片。
本发明还提供一种半导体封装件的制法，包括：提供一线路板，该线路板上具有承载件；设置射频芯片于该承载件上，该射频芯片具有相对的主动面与非主动面，该主动面上具有多个电极垫，且该非主动面结合至该承载件上；形成多个高位焊线于该电极垫上，以令该些高位焊线电性连接该电极垫与该线路板；以及形成绝缘层于该线路板上，以包覆该承载件、高位焊线与射频芯片。
前述的半导体封装件及其制法中，该承载件为功能性芯片、虚芯片、散热片或绝缘体。
前述的半导体封装件及其制法中，该射频芯片的宽度大于该承载件的宽度，以于该射频芯片与该线路板之间形成容置空间。此外还包括至少一半导体组件，其设于该线路板上，例如，位于该容置空间中或位于该承载件的周围。
前述的半导体封装件及其制法中，该射频芯片藉由结合层固定于该承载件上。
另外，前述的半导体封装件及其制法中，还包括形成多个低位焊线于该承载件上，以令该低位焊线连接该承载件与该线路板，且该射频芯片藉由结合层固定于该承载件上，且该结合层包覆该低位焊线的部分线段。例如，该低位焊线电性连接该承载件与该线路板；或者，接地层形成于该射频芯片的非主动面上，且该低位焊线接触该接地层，使该承载件接地至该线路板。
由上可知，本发明的半导体封装件及其制法，其藉由将该射频芯片间隔设于该线路板上，以利于在该线路板与该射频芯片之间产生空间，以供置放组件或高频布线，而达到高度整合无线系统级封装模块的目的。
附图说明
图1为现有半导体封装件的剖视示意图；以及
图2A至图2D为本发明的半导体封装件的制法的剖视示意图；其中，图2C’为图2C的其中一种实施例，图2D’及图2D”为图2D的其它实施例。
符号说明
1,2,2’,2” 半导体封装件
10,20       线路板
11          虚芯片
12,22       射频芯片
13          第二焊线
14          半导体芯片
140         第一焊线
16          封装胶体
200         粘着层
201,201’   第一焊垫
202         第二焊垫
21          承载件
210,210’   低位焊线
23          高位焊线
22a         主动面
22b         非主动面
220         电极垫
24          半导体组件
25          结合层
26          绝缘层
27          接地层
S           容置空间
W,d         宽度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“高位”、“低位”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2D为本发明的半导体封装件2的制法的剖面示意图。
如图2A所示，提供一线路板20，该线路板20上具有一承载件21，且设置多个半导体组件24于该线路板20上。
于本实施例中，该线路板20具有第一焊垫201与第二焊垫202，且藉由粘着层200固定该承载件21。
此外，该承载件21为功能性芯片、虚芯片（dummy die）、散热片或绝缘体。
又，该些半导体组件24为电阻、电容或电感等，其位于该承载件21的周围。
如图2B所示，形成多个低位焊线210于该承载件21上，以令该低位焊线210电性连接该承载件21与该线路板20的第一焊垫201。
如图2C所示，设置一射频芯片22于该承载件21上，该射频芯片22具有相对的主动面22a与非主动面22b，该主动面22a上具有多个电极垫220，且该非主动面22b结合至该承载件21上。
接着，形成多个高位焊线23于该电极垫220上，以令该些高位焊线23电性连接该电极垫220与该线路板20的第二焊垫202。
于本实施例中，该射频芯片22为高频率芯片或无线射频芯片，且该射频芯片22的宽度W大于该承载件21的宽度d，以于该射频芯片22与该线路板20之间形成一容置空间S，且该半导体组件24位于该容置空间S中，该容置空间S的高度至少0.2㎜。
此外，该射频芯片22藉由一结合层25固定于该承载件21上，且利用胶膜包线（Film over Wire,FOW）技术，使该结合层25包覆该低位焊线210的部分线段，以达轻薄短小的目的，且可避免该低位焊线210跨越及触碰至该射频芯片22而发生短路的问题，且可降低打线作业的困难度。
又，如图2C’所示，本实施例先形成该结合层25于该射频芯片22的非主动面22b上，再将该射频芯片22以该结合层25结合至该承载件21上；于其它实施例中，亦可先形成该结合层25于该承载件21上，再将该射频芯片22以其非主动面22b结合至该结合层25上。
如图2D所示，形成一绝缘层26于该线路板20上，以包覆该承载件21、射频芯片22、低位焊线210及高位焊线23。
于本实施例中，该绝缘层26为模压制程用的封装胶体，但于其它实施例中，该绝缘层26也可为例如压合制程用的薄膜或印刷制程用的胶材等，所以该绝缘层26的材质或形成方式并无特别限制。
本发明将该射频芯片22架高至一适当高度，以形成一容置空间S，供置放组件（如半导体组件24）及高频布线（如线路板20上的线路），所以能提升布线的灵活度与组件的摆放空间，而达到高度整合无线（wireless）系统级（System in Package,SiP）封装模块的目的。
此外，利用架高该射频芯片22，能避免该射频芯片22与半导体组件24（或线路板20的线路）发生干扰。
又，如图2D’所示，也可于该射频芯片22的非主动面22b上形成一接地层27，且该低位焊线210’接触该接地层27，使该承载件21藉由该低位焊线210’仅接地至该线路板20的第一焊垫201’，所以该承载件21无电性功能。
另外，如图2D”所示，该承载件21也可藉由部分该低位焊线210’接地至该线路板20的第一焊垫201’，且藉由部分该低位焊线210电性连接该线路板20的第一焊垫201，所以该承载件21具电性功能。
本发明提供一种半导体封装件2,2’,2”，包括：一线路板20、设于该线路板20上的一承载件21、设于该承载件21上的一射频芯片22、电性连接该电极垫220与该线路板20的多个高位焊线23、以及设于该线路板20上的一绝缘层26。
所述的承载件21为功能性芯片、虚芯片、散热片或绝缘体。
所述的射频芯片22具有相对的主动面22a与非主动面22b，该主动面22a上具有多个电极垫220，且该非主动面22b结合至该承载件21上。
所述的绝缘层26包覆该承载件21、高位焊线23与射频芯片22。
于一实施例中，该射频芯片22的宽度W大于该承载件21的宽度d，以于该射频芯片22与该线路板20之间形成一容置空间S。还包括设于该线路板20上的至少一半导体组件24，其位于该承载件21的周围或位于该容置空间S中。
于一实施例中，该射频芯片22藉由一结合层25固定于该承载件21上，且藉由多个低位焊线210电性连接该承载件21与该线路板20，令该结合层25包覆该低位焊线210的部分线段。
于一实施例中，该射频芯片22的非主动面22b上具有一接地层27，且多个低位焊线210’接触该接地层27，使该承载件21仅接地至该线路板20。或者，该承载件21藉由部分该低位焊线210’接地至该线路板20，且藉由部分该低位焊线210电性连接该线路板20。
综上所述，本发明的半导体封装件及其制法中，藉由架高该射频芯片，以利于在该线路板上置放组件及高频布线，而达到高度整合无线系统级封装模块的目的。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (24)

1.一种半导体封装件，其包括：
一线路板；
承载件，其设于该线路板上；
射频芯片，其设于该承载件上，该射频芯片具有相对的主动面与非主动面，该主动面上具有多个电极垫，且该非主动面结合至该承载件上；
多个高位焊线，其电性连接该电极垫与该线路板；以及
绝缘层，其形成于该线路板上，以包覆该承载件、高位焊线与射频芯片。
2.根据权利要求1所述的半导体封装件，其特征在于，该承载件为功能性芯片、虚芯片、散热片或绝缘体。
3.根据权利要求1所述的半导体封装件，其特征在于，该射频芯片的宽度大于该承载件的宽度，以于该射频芯片与该线路板之间形成容置空间。
4.根据权利要求3所述的半导体封装件，其特征在于，该半导体分装件还包括至少一半导体组件，其设于该线路板上并位于该容置空间中。
5.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括至少一设于该线路板上的半导体组件。
6.根据权利要求5所述的半导体封装件，其特征在于，该半导体组件位于该承载件的周围。
7.根据权利要求1所述的半导体封装件，其特征在于，该射频芯片藉由结合层固定于该承载件上。
8.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括多个低位焊线，其连接该承载件与该线路板，且该射频芯片藉由结合层固定于该承载件上。
9.根据权利要求8所述的半导体封装件，其特征在于，该低位焊线电性连接该承载件与该线路板。
10.根据权利要求9所述的半导体封装件，其特征在于，该结合层包覆该低位焊线的部分线段。
11.根据权利要求8或10所述的半导体封装件，其特征在于，该射频芯片的非主动面上具有接地层，且该低位焊线接触该接地层，使该承载件接地至该线路板。
12.根据权利要求11所述的半导体封装件，其特征在于，该承载件藉由部分该低位焊线接地至该线路板，且藉由部分该低位焊线电性连接该线路板。
13.一种半导体封装件的制法，其包括：
提供一线路板，该线路板上具有承载件；
设置射频芯片于该承载件上，其中，该射频芯片具有相对的主动面与非主动面，该主动面上具有多个电极垫，且该非主动面结合至该承载件上；
形成多个高位焊线于该电极垫上，以令该些高位焊线电性连接该电极垫与该线路板；以及
形成绝缘层于该线路板上，以包覆该承载件、高位焊线与射频芯片。
14.根据权利要求13所述的半导体封装件的制法，其特征在于，该承载件为功能性芯片、虚芯片、散热片或绝缘体。
15.根据权利要求13所述的半导体封装件的制法，其特征在于，该射频芯片的宽度大于该承载件的宽度，以于该射频芯片与该线路板之间形成容置空间。
16.根据权利要求15所述的半导体封装件的制法，其特征在于，该制法还包括设置至少一半导体组件于该线路板上，且令该半导体组件位于该容置空间中。
17.根据权利要求13所述的半导体封装件的制法，其特征在于，该制法还包括设置至少一半导体组件于该线路板上。
18.根据权利要求17所述的半导体封装件的制法，其特征在于，该半导体组件位于该承载件的周围。
19.根据权利要求13所述的半导体封装件的制法，其特征在于，该射频芯片藉由结合层固定于该承载件上。
20.根据权利要求13所述的半导体封装件的制法，其特征在于，该制法还包括形成多个低位焊线于该承载件上，以令该低位焊线连接该承载件与该线路板，且该射频芯片藉由结合层固定于该承载件上。
21.根据权利要求20所述的半导体封装件的制法，其特征在于，该低位焊线电性连接该承载件与该线路板。
22.根据权利要求21所述的半导体封装件的制法，其特征在于，该结合层包覆该低位焊线的部分线段。
23.根据权利要求20所述的半导体封装件的制法，其特征在于，该射频芯片的非主动面上形成有接地层，供该低位焊线接触该接地层，以使该承载件接地至该线路板。
24.根据权利要求23所述的半导体封装件的制法，其特征在于，该承载件藉由部分该低位焊线接地至该线路板，且藉由部分该低位焊线电性连接该线路板。
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