CN104064530A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN104064530A
CN104064530A CN201310115674.1A CN201310115674A CN104064530A CN 104064530 A CN104064530 A CN 104064530A CN 201310115674 A CN201310115674 A CN 201310115674A CN 104064530 A CN104064530 A CN 104064530A
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electric contact
semiconductor package
contact mat
substrate
conductive layer
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CN104064530B (zh
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林邦群
程协仁
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件包括具有线路的基板、覆盖该线路的绝缘层、形成于该绝缘层上的导电层以及设于该基板上的半导体组件，该基板还具有转接垫及第一电性接触垫，使该线路位于该转接垫与第一电性接触垫之间，且该导电层延伸至该转接垫与第一电性接触垫上，而该半导体组件以多条焊线电性连接该转接垫。通过该导电层取代现有短焊线，以连接该转接垫与第一电性接触垫，所以能减少焊线数量，以避免该些焊线相接触而造成短路的问题。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，尤指一种利于轻薄短小化的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，随着半导体工艺技术的进步，使更多电子组件整合于半导体芯片中，且芯片的效能也更好，因而芯片上所设置的输入/输出连接端（I/O connections）数目渐多。于现今封装技术发展趋势下，封装件朝轻、薄、短、小的技术发展，因而承载芯片用的基板上需密集地布设多个与该等输入/输出连接端电性连通的打线垫作为芯片的外接电性连接点，如图1A所示的半导体封装件1。
如图1A所示，一基板10上承载一半导体芯片13，且该半导体芯片13的电极垫130以多条焊线14电性连接该基板10的打线垫102，再形成封装胶体15于该基板10上，以包覆该半导体芯片13与焊线14。
然而，于轻、薄、短、小的需求下，需减缩该基板10于芯片周围的空间以设置符合该电极垫130的数目的该些打线垫102，致使布线极为困难，且于如此密集的打线垫102的布设区域中，该些焊线14间极容易相互接触k而造成短路。
为避免发生上述因焊线接触而造成短路的问题，因而发展出一种利用转接方式，其将半导体芯片的电极垫与转接组件经第一组焊线连接，再利用第二组焊线连接该转接组件与基板的打线垫，如图1B及图1B’所示的半导体封装件1’。
如图1B所示，一基板10包含一绝缘保护层10b及埋设于该绝缘保护层10b中的线路层10a，该线路层10a具有转接垫100、第一与第二打线垫101,102’、及位于该转接垫100与第一打线垫101之间的线路103。将一半导体芯片13结合于该基板10上，且该半导体芯片13的部分电极垫130以第一短焊线14a连接该转接垫100，该转接垫100再以第二短焊线14b连接该第一打线垫101，而另一部分电极垫130以多条焊线14电性连接该第二打线垫102’。接着，形成封装胶体15于该基板10上，以包覆该半导体芯片13、第一及第二短焊线14a,14b、焊线14、转接垫100、第一与第二打线垫101,102’。之后，形成如焊球的导电组件16于该线路层10a的下表面外露处。
然而，现有半导体封装件1’中，该第二短焊线14b具有一定弧高，所以该第二短焊线14b与该焊线14容易相互接触k，因而造成短路。
此外，为了避免该第二短焊线14b与该焊线14之间因相互接触k而短路，所以增加该焊线14的弧高，却因而使该半导体封装件1’的整体结构高度增加，致使该半导体封装件1’无法满足薄化的需求。
又，现有半导体封装件1’中，当仅有单层线路层10a时，布局空间将大幅受限而难以弹性化，致使许多线路103仅能于平面上进行布设，而无法制作多层线路，因而无法经由上、下层的绕线方式进行回避。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的在于提供一种半导体封装件及其制法，以避免该些焊线相接触而造成短路的问题。
本发明的半导体封装件，包括：基板，其具有多个转接垫、多个第一电性接触垫及多个置于该转接垫与第一电性接触垫之间的线路；绝缘层，其覆盖该线路；导电层，其设于该绝缘层上，且该导电层延伸至该转接垫与第一电性接触垫上；以及半导体组件，其设于该基板上，且该半导体组件以多条焊线电性连接该转接垫。
前述的半导体封装件中，该基板还具有绝缘保护层，供该转接垫与第一电性接触垫埋设于该绝缘保护层中，并令该转接垫与第一电性接触垫外露于该绝缘保护层。
本发明还提供一种半导体封装件的制法，其包括：提供一基板，该基板具有多个转接垫、多个第一电性接触垫及多条置于该转接垫与第一电性接触垫之间的线路；覆盖绝缘层于该线路上；形成导电层于该绝缘层上，且该导电层延伸至该转接垫与第一电性接触垫上；以及设置半导体组件于该基板上，并以多个焊线电性连接该半导体组件及该转接垫。
前述的半导体封装件及其制法中，该基板还具有多个第二电性接触垫，以供该半导体组件以该些焊线电性连接该第二电性接触垫。
前述的半导体封装件及其制法中，该线路相对凸出该基板表面。
前述的半导体封装件及其制法中，该转接垫、导电层与第一电性接触垫成为导电路径。
前述的半导体封装件及其制法中，该转接垫、线路与第一电性接触垫上具有表面处理层。
前述的半导体封装件及其制法中，该绝缘层为胶体，例如，以喷墨或涂布方式形成之。
前述的半导体封装件及其制法中，该导电层为胶体、喷墨形成的金属层或经由涂布形成的导电迹线。
另外，前述的半导体封装件及其制法中，还包括形成封装胶体于该基板上，以包覆该半导体组件、焊线、转接垫、导电层与第一电性接触垫。
由上可知，本发明的半导体封装件及其制法，通过该导电层连接该转接垫与第一电性接触垫，且该导电层的高度远低于焊线弧高，所以以该导电层取代现有短焊线，长焊线于打线工艺中不会接触该导电层，因而可避免短路，使本发明不仅能避免产品失效，且能降低长焊线的线弧，以减低该封装胶体的厚度，而利于薄化该半导体封装件。
此外，当基板仅有单层线路层时，利用该转接垫与第一电性接触垫之间的空间作为布线区，以形成该绝缘层与导电层，使该导电层作为线路结构，所以能增加布线空间，以使线路布局更具弹性化。
附图说明
图1A为现有半导体封装件的剖视示意图；
图1B为现有半导体封装件的剖视示意图；
图1B’为图1B的局部上视示意图；
图2A至图2C为本发明的半导体封装件的制法的剖视示意图；
图2A’为图2A的另一实施例；以及
图2C’为图2C的局部上视示意图。
符号说明
1,1’,2 半导体封装件
10,20 基板
10a,20a 线路层
10b,20b 绝缘保护层
100,200 转接垫
101 第一打线垫
102 打线垫
102’ 第二打线垫
103,203 线路
13 半导体芯片
130,230 电极垫
14,24,24’ 焊线
14a 第一短焊线
14b 第二短焊线
15,25 封装胶体
16,26 导电组件
200b 开孔
201 第一电性接触垫
202 第二电性接触垫
204 置晶垫
205 植球垫
21 绝缘层
22 导电层
23 半导体组件
231 粘着材
27 表面处理层
h 凸出高度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2C为本发明的半导体封装件2的制法的剖面示意图。
如图2A所示，提供一基板20，该基板20包含一绝缘保护层20b及嵌埋于该绝缘保护层20b中的线路层20a，该线路层20a的上侧具有转接垫200、第一与第二电性接触垫201,202、置晶垫204、及位于该转接垫200与第一电性接触垫201之间的线路203，而该线路层20a的下侧具有多个植球垫205。
于本实施例中，该基板20为单层的线路结构，该绝缘保护层20b为封装胶体，且该线路203相对凸出该绝缘保护层20b，而该线路203的凸出高度h为5至15um。
此外，该转接垫200、第一与第二电性接触垫201,202、线路203及置晶垫204外露于该绝缘保护层20b的上侧，而该植球垫205外露于该绝缘保护层20b的下侧，例如，该绝缘保护层20b具有多个开孔200b，以外露该植球垫205。
又，该第一与第二电性接触垫201,202、线路203及置晶垫204电性连接该植球垫205。
另外，如图2A’所示，可形成一表面处理层27于该转接垫200、第一与第二电性接触垫201,202、线路203与置晶垫204上。其中，该表面处理层27为镍金层或有机保焊剂（Organic SolderabilityPreservative,OSP）。
如图2B所示，形成一绝缘层21于该基板20上以覆盖该线路203，再形成一导电层22于该绝缘层21上，且该导电层22延伸至该转接垫200与该第一电性接触垫201上，使该转接垫200、导电层22与第一电性接触垫201成为一导电路径。该线路203与该导电层22之间通过该绝缘层21而电性隔绝，以防止该线路203与该导电层22因相接触而短路。
于本实施例中，该绝缘层21可为胶体，且以喷墨、涂布或点胶方式形成，且该导电层22可为金属层经由网印、喷墨或其它方式形成，或经由涂布形成的导电迹线；该导电层22亦可为一胶体，经由涂布、点胶、喷墨或其它方式形成。
如图2C及图2C’所示，通过粘着材231结合一具有多个电极垫230的半导体组件23于该基板20的置晶垫204上，且该半导体组件23的电极垫230以多条焊线24,24’电性连接该转接垫200及该第二电性接触垫202。换言之，该半导体组件23的部分电极垫230以该焊线24连接该转接垫200，再经由该转接垫200、导电层22与第一电性接触垫201连接至植球垫205所构成的导电路径，以令该半导体组件23电性连接至外部。
接着，形成封装胶体25于该基板20上，以包覆该半导体组件23、焊线24,24’、转接垫200、导电层22、第一与第二电性接触垫201,202。之后，形成如焊球的导电组件26于该植球垫205上。
本发明的半导体封装件2的制法中，以该导电层22连接该转接垫200与第一电性接触垫201，且该导电层22的高度远低于焊线弧高，所以以该导电层22取代现有短焊线，该较长焊线24’于打线工艺中不会接触该导电层22，因而可避免短路。因此，本发明的制法不仅能避免产品失效，且能降低该较长焊线24’的线弧，以减低该封装胶体25的厚度，有利于该半导体封装件2朝轻、薄、短、小的技术发展。
此外，当基板20仅有单层线路层20a时，利用该转接垫200与第一电性接触垫201之间的空间作为布线区，以形成该绝缘层21与导电层22，使该导电层22作为线路结构，所以藉该导电层22的设计，能增加布线空间，以使线路布局更具弹性化，致使许多线路203与该导电层22能经由上、下层的绕线方式进行回避。
本发明提供一种半导体封装件2，包括：一基板20、形成于该基板20上的一绝缘层21、形成于该绝缘层21上的一导电层22、设于该基板20上的一半导体组件23以及形成于该基板20上的封装胶体25。
所述的基板20具有转接垫200、第一电性接触垫201及位于该转接垫200与第一电性接触垫201之间的线路203。
于一实施例中，该基板20还具有绝缘保护层20b，令该转接垫200与第一电性接触垫201埋设于该绝缘保护层20b中，且令该转接垫200与第一电性接触垫201外露于该绝缘保护层20b。
于一实施例中，该线路203相对凸出该基板20表面（或该绝缘保护层20b表面）。
所述的绝缘层21覆盖该线路203，且该绝缘层21可为胶体。
所述的导电层22延伸至该转接垫200与第一电性接触垫201上，且该导电层22可为胶体、金属层或线路。
所述的半导体组件23以多条焊线24电性连接该转接垫200，且该转接垫200、导电层22与第一电性接触垫201成为一导电路径。
于一实施例中，该基板20还具有第二电性接触垫202，且该半导体组件23以另一焊线24’直接电性连接该第二电性接触垫202。
所述的封装胶体25包覆该半导体组件23、焊线24,24’、转接垫200、导电层22与第一电性接触垫201。
于一实施例中，该转接垫200、线路203与第一电性接触垫201上具有表面处理层36。
综上所述，本发明的半导体封装件及其制法，主要通过该导电层取代现有短焊线，以作为连接该转接垫与第一电性接触垫的转接组件，而能避免该焊线相互接触所造成的短路问题，所以能提升产品的可靠度，且利于该半导体封装件朝轻、薄、短、小的技术发展。
此外，于该转接垫与第一电性接触垫之间的线路上形成线路结构（即该绝缘层与导电层），所以能增加布线空间，以达到线路布局弹性化的目的。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种半导体封装件，包括：
基板，其具有多个转接垫、多个第一电性接触垫及多个置于该转接垫与第一电性接触垫之间的线路；
绝缘层，其覆盖该线路；
导电层，其形成于该绝缘层上，且该导电层延伸至该转接垫与第一电性接触垫上；以及
半导体组件，其设于该基板上，且该半导体组件以多条焊线电性连接该转接垫。
2.根据权利要求1所述的半导体封装件，其特征在于，该基板还具有多个第二电性接触垫，以供该半导体组件以该些焊线电性连接该第二电性接触垫。
3.根据权利要求1所述的半导体封装件，其特征在于，该基板还具有绝缘保护层，供该转接垫与第一电性接触垫埋设于该绝缘保护层中，并令该转接垫与第一电性接触垫外露于该绝缘保护层。
4.根据权利要求1所述的半导体封装件，其特征在于，该线路相对凸出该基板表面。
5.根据权利要求1所述的半导体封装件，其特征在于，该转接垫、导电层与第一电性接触垫成为导电路径。
6.根据权利要求1所述的半导体封装件，其特征在于，该转接垫、线路与第一电性接触垫上具有表面处理层。
7.根据权利要求1所述的半导体封装件，其特征在于，该绝缘层为胶体。
8.根据权利要求1所述的半导体封装件，其特征在于，该导电层为胶体或金属层。
9.根据权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括封装胶体，其形成于该基板上，以包覆该半导体组件、焊线、转接垫、导电层与第一电性接触垫。
10.一种半导体封装件的制法，其包括：
提供一基板，该基板具有多个转接垫、多个第一电性接触垫及多个置于该转接垫与第一电性接触垫之间的线路；
覆盖绝缘层于该线路上；
形成导电层于该绝缘层上，且该导电层延伸至该转接垫与第一电性接触垫上；以及
设置半导体组件于该基板上，并以多条焊线电性连接该半导体组件及该转接垫。
11.根据权利要求10所述的半导体封装件的制法，其特征在于，该基板还具有多个第二电性接触垫，以供该半导体组件以该些焊线电性连接该第二电性接触垫。
12.根据权利要求10所述的半导体封装件的制法，其特征在于，该线路相对凸出该基板表面。
13.根据权利要求10所述的半导体封装件的制法，其特征在于，该转接垫、导电层与第一电性接触垫成为导电路径。
14.根据权利要求10所述的半导体封装件的制法，其特征在于，该转接垫、线路与第一电性接触垫上形成有表面处理层。
15.根据权利要求10所述的半导体封装件的制法，其特征在于，该绝缘层为胶体。
16.根据权利要求10所述的半导体封装件的制法，其特征在于，该绝缘层的形成以喷墨或涂布方式为之。
17.根据权利要求10所述的半导体封装件的制法，其特征在于，该导电层为金属层经由喷墨或网印方式形成或为胶体经由涂布、点胶或喷墨方式形成的导电迹线。
18.根据权利要求10所述的半导体封装件的制法，其特征在于，该制法还包括形成封装胶体于该基板上，以包覆该半导体组件、焊线、转接垫、导电层与第一电性接触垫。
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