CN103943620A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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CN103943620A
CN103943620A CN201310047475.1A CN201310047475A CN103943620A CN 103943620 A CN103943620 A CN 103943620A CN 201310047475 A CN201310047475 A CN 201310047475A CN 103943620 A CN103943620 A CN 103943620A
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passive component
substrate
semiconductor chip
semiconductor package
radio frequency
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CN103943620B (zh
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蔡宗贤
朱恒正
林建成
邱志贤
钟兴隆
朱育德
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种半导体封装件及其制法，该半导体封装件包括：一表面上形成有多个电性连接垫与多个围绕该等电性连接垫的打线垫的基板；多个设置于该基板的电性连接垫上的被动组件；形成于该基板的该表面上的绝缘层，令部份该被动组件嵌埋于其中；设于该绝缘层的顶面上的半导体芯片，该半导体芯片在垂直基板方向的投影区域部分涵盖最外侧的该被动组件；多个电性连接该半导体芯片与该打线垫的焊线；形成于该基板的该表面上的封装胶体，使该绝缘层、焊线及半导体芯片嵌埋于其中。本发明通过将半导体芯片设置于嵌埋有被动组件的绝缘层上，能有效提升被动组件的设置密度。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，尤指一种打线型式的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，市面上的电子产品多以轻量、小型、高速及多功能为诉求。电子产品能否达到轻、薄、短、小、快的理想境界，取决于IC组件在高记忆容量、高操作频率及低电压需求的发展，但是IC组件能否持续提高记忆容量与操作频率并降低电压需求，端视IC组件上电子电路与电子组件积体化的程度、以及作为提供电子电路信号与电源传递媒介所用的输入／输出接脚(I/O Connector)密度而定。
为了在一个半导体装置中容纳较多电子组件(ElectronicComponents)（如电容器、电阻器、电感器、振荡器(RF passive device)等的被动组件）以符合业界的需求，遂发展出球栅数组(BGA)半导体装置。
然而，某些半导体应用装置，例如通信或射频（RF）半导体装置中，常需要将电阻器、电感器、电容器及振荡器等多个被动组件电性连接至所封装的半导体芯片，以使该半导体芯片具有特定的电流特性。以BGA半导体装置为例，多个被动组件虽安置于基板表面，但是为了避免该等被动组件阻碍半导体芯片与多个电性连接垫(Bonding Fingers)间的电性连结及配置，传统上多将该等被动组件安置于基板角端位置或半导体芯片接置区域以外的基板的额外布局面积上。
然而，限定被动组件的设置位置将缩小基板线路布局(Routability)的灵活性，且电性连接垫位置更会导致该等被动组件布设数量受到局限，不利半导体装置高度集成化的发展趋势。此外，被动组件的布设数量随着半导体封装件高性能的要求而相对地遽增，如采用现有方法，该基板表面必须同时容纳多个半导体芯片以及较多被动组件，而造成封装基板面积加大，进而迫使封装件体积增大，也不符合半导体封装件轻薄短小的发展潮流。
请参阅图1，基于上述问题，现有半导体封装件1将多个被动组件11接置于半导体芯片13与电性连接垫100之间的区域上。然而，随着半导体装置内单位面积上的输出／输入连接端数量的增加，焊线14数量也随之提升，且一般被动组件11的高度(0.8毫米)高于半导体芯片13(0.55毫米)，因此为避免焊线14触及被动组件11而造成短路，焊线14需拉高并横越该被动组件11的正上方，提升焊接困难度，也使得线弧(Wire Loop)长度增加。又，焊线14本身具有重量，拉高的焊线14若缺乏支撑，易因本身重力崩塌(Sag)触及被动组件11而产生短路，且焊线14本身由金、铝材质制成，故此法不仅增加工艺复杂性，且增长焊线14的线弧长度将明显提升焊线14成本。
因此，如何避免上述现有技术中的种种问题，实已成为目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺点，本发明的主要目的在于提供一种半导体封装件及其制法，能有效提升被动组件的设置密度。
本发明的半导体封装件包括：基板，其一表面上形成有多个电性连接垫与多个围绕该等电性连接垫的打线垫；多个被动组件，其设置于该基板的电性连接垫上；绝缘层，其形成于该基板的该表面上，以令部份该被动组件嵌埋于其中；半导体芯片，其设于该绝缘层的顶面上，该半导体芯片在垂直基板方向的投影区域部分涵盖最外侧的该被动组件；多个焊线，其电性连接该半导体芯片与该打线垫；以及封装胶体，其形成于该基板的该表面上，以使该绝缘层、焊线及半导体芯片嵌埋于其中。
本发明还提供一种半导体封装件的制法，其包括：提供一表面上形成有多个电性连接垫与多个围绕该等电性连接垫的打线垫的基板；设置并电性连接多个被动组件于该电性连接垫上；于该基板的该表面上形成绝缘层，使部分该被动组件嵌埋于其中；于该绝缘层的顶面上设置半导体芯片，并通过多个焊线使该半导体芯片电性连接至该打线垫，该半导体芯片在垂直基板方向的投影区域部分涵盖最外侧的该被动组件；以及于该基板的该表面上形成封装胶体，以使该绝缘层、焊线及半导体芯片嵌埋于其中。
于本发明的半导体封装件的一实施例中，该半导体芯片在垂直基板方向的投影区域部分涵盖最外侧的该被动组件，并使其突出该投影区域边缘0.1至1.5毫米，以避免现有焊线易触及被动组件所造成的短路问题。
于本发明的半导体封装件中，该被动组件包括非射频被动组件及射频被动组件。
由上可知，本发明的半导体封装件及其制法通过将半导体芯片设置于嵌埋有被动组件的绝缘层上，以克服现有技术中将被动组件设置于基板角端或额外布局于基板上的缺点，可有效提升被动组件的设置密度。
此外，本发明的半导体封装件及其制法更通过使该半导体芯片在垂直基板方向的投影区域完全或部分涵盖最外侧的该被动组件，能降低工艺复杂性，且有效降低焊线的线弧长度。
附图说明
图1为现有半导体封装件的剖面示意图。
图2A至图2D为本发明的半导体封装件的制法的第一实施例的剖面示意图。
图3为本发明的半导体封装件的第二实施例的剖面示意图。
符号说明
1、2、3  半导体封装件    100、200a  电性连接垫
200b     打线垫          11、21     被动组件
13、23   半导体芯片      14、24     焊线
20       基板            21a        射频被动组件
21b      非射频被动组件  22         绝缘层
25       封装胶体        D          距离。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“围绕”、“顶”、“突出”、“投影区域”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
第一实施例
图2A至图2D为本发明的半导体封装件2的制法的第一实施例的剖面示意图。
如图2A所示，提供一表面上形成有多个电性连接垫200a与多个围绕该等电性连接垫200a的打线垫200b的基板20，于该电性连接垫200a上设置并电性连接多个被动组件21，该等被动组件21包括至少一射频被动组件21a(例如石英振荡器、T/R开关或滤波器)及多个非射频被动组件21b(例如电阻、电容或电感)，该等非射频被动组件21b围绕于该射频被动组件21a的外围。
如图2B所示，于该基板20的该表面上形成绝缘层22，以令该射频被动组件21a嵌埋于其中。
于本实施例中，对于该绝缘层22的形成方式与材料并未有特殊限制，于此不再赘述。
如图2C所示，于该绝缘层22的顶面上设置半导体芯片23，并使该半导体芯片23通过焊线24电性连接至该基板20的打线垫200b，部分该非射频被动组件21b突出于该半导体芯片23在垂直基板20方向的投影区域一段距离D，即该半导体芯片23在垂直基板20方向的投影区域部分涵盖最外侧的该被动组件21。
如图2D所示，形成封装胶体25于该基板20的该表面上，以包覆该绝缘层22、半导体芯片23、非射频被动组件21b及焊线24，而制得本发明的半导体封装件2。
于本实施例中，有关封装胶体25的形成方式及材料，在此不再赘述。
本实施例经实际测试后，发现该距离D于介于0.1至1.5毫米之间时，能有效防止用以电性连接该半导体芯片23与打线垫200b的焊线24触及非射频被动组件21b而短路的问题。
第二实施例
图3为本发明的半导体封装件3的第二实施例的剖面示意图，本实施例大致相同于前一实施例，主要不同之处在于该绝缘层22包覆该等被动组件21，最外侧的该被动组件21突出于该半导体芯片23在垂直基板20方向的投影区域一段距离D，且该距离D介于0.1至1.5毫米之间。至于本实施例的详细制法为所属技术领域具有通常知识者依本说明书与图式所能了解者，故不再赘述。
于本实施例中，该被动组件21可为非射频被动组件或射频被动组件，其中，该非射频被动组件包括但不限于电阻、电容及电感；该射频被动组件包括但不限于石英振荡器、T/R开关及滤波器。
本发明提供一种半导体封装件2,3，包括：基板20，其一表面上形成有多个电性连接垫200a与多个围绕该等电性连接垫200a的打线垫200b；多个被动组件21，其设置于该基板20的电性连接垫200a上；绝缘层22，其形成于该基板20的该表面上，以令部份该被动组件21嵌埋于其中；半导体芯片23，其设于该绝缘层22的顶面上，该半导体芯片23在基板20的投影区域部分涵盖最外侧的该被动组件21；多个焊线24，其电性连接该半导体芯片23与该打线垫200b；以及封装胶体25，其形成于该基板20的该表面上，以使该绝缘层22、焊线24及半导体芯片23嵌埋于其中。
于前述实施例中，最外侧的该被动组件21突出于该半导体芯片23在基板20的投影区域一段距离D，该距离D介于0.1至1.5毫米之间。
前述的半导体封装件中，该等被动组件21包括多个非射频被动组件21b及一射频被动组件21a。
于一实施例中，该射频被动组件21a被该绝缘层22所覆盖，且该等非射频被动组件21b围绕于该射频被动组件21a的外围。
综上所述，本发明的半导体封装件及其制法先将被动组件设置于基板上，再将半导体芯片设置于该等被动组件上方，不仅能克服现有半导体封装件将被动组件设置于基板角端位置或基板的额外布局面积上的缺点，并可有效提升被动组件的设置密度，此外，本发明的半导体封装件及其制法更通过使该半导体芯片在垂直基板方向的投影区域完全或部分涵盖最外侧的该被动组件，以避免现有焊线易触及被动组件所造成的短路问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种半导体封装件，包括：
基板，其一表面上形成有多个电性连接垫与多个围绕该等电性连接垫的打线垫；
多个被动组件，其设置于该基板的电性连接垫上；
绝缘层，其形成于该基板的该表面上，以令部份该被动组件嵌埋于其中；
半导体芯片，其设于该绝缘层的顶面上，该半导体芯片在垂直基板方向的投影区域部分涵盖最外侧的该被动组件；
多个焊线，其电性连接该半导体芯片与该打线垫；以及
封装胶体，其形成于该基板的该表面上，以使该绝缘层、焊线及半导体芯片嵌埋于其中。
2.根据权利要求1所述的半导体封装件，其特征在于，最外侧的该被动组件突出该投影区域边缘0.1至1.5毫米。
3.根据权利要求1所述的半导体封装件，其特征在于，该等被动组件包括多个非射频被动组件及至少一射频被动组件。
4.根据权利要求3所述的半导体封装件，其特征在于，该射频被动组件被该绝缘层所覆盖。
5.根据权利要求3所述的半导体封装件，其特征在于，该等非射频被动组件围绕于该射频被动组件的外围。
6.一种半导体封装件的制法，其包括：
提供一表面上形成有多个电性连接垫与多个围绕该等电性连接垫的打线垫的基板；
设置并电性连接多个被动组件于该电性连接垫上；
于该基板的该表面上形成绝缘层，使部分该被动组件嵌埋于其中；
于该绝缘层的顶面上设置半导体芯片，并通过多个焊线使该半导体芯片电性连接至该打线垫，该半导体芯片在垂直基板方向的投影区域部分涵盖最外侧的该被动组件；以及
于该基板的该表面上形成封装胶体，以使该绝缘层、焊线及半导体芯片嵌埋于其中。
7.根据权利要求6所述的半导体封装件的制法，其特征在于，最外侧的该被动组件突出该投影区域边缘0.1至1.5毫米。
8.根据权利要求6所述的半导体封装件的制法，其特征在于，该等被动组件包括多个非射频被动组件及至少一射频被动组件。
9.根据权利要求8所述的半导体封装件的制法，其特征在于，该射频被动组件被该绝缘层所覆盖。
10.根据权利要求8所述的半导体封装件的制法，其特征在于，该等非射频被动组件围绕于该射频被动组件的外围。
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CN103943620B (zh) 2017-08-11
US20140203395A1 (en) 2014-07-24
TW201431009A (zh) 2014-08-01
US9997477B2 (en) 2018-06-12
TWI499013B (zh) 2015-09-01
US20160225728A1 (en) 2016-08-04

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