CN105742260A - 电子封装件 - Google Patents
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- 230000005291 magnetic effect Effects 0.000 claims abstract description 85
- 239000004020 conductor Substances 0.000 claims abstract description 35
- 238000012856 packing Methods 0.000 claims description 55
- 239000011159 matrix material Substances 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 13
- 238000005538 encapsulation Methods 0.000 claims description 12
- 239000000084 colloidal system Substances 0.000 claims description 11
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 229910000859 α-Fe Inorganic materials 0.000 claims description 4
- 230000004907 flux Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 description 22
- 230000001939 inductive effect Effects 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011469 building brick Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 239000000411 inducer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- -1 metallic plate Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004899 motility Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
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- H01F27/02—Casings
- H01F27/022—Encapsulation
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
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- H01F27/24—Magnetic cores
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2809—Printed windings on stacked layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
一种电子封装件,包括:基体、嵌埋于该基体中的导磁件、以及设于该导磁件周围的导体结构,使该结构产生较高磁通量,进而增加电感量。
Description
技术领域
本发明涉及一种电子封装件,尤指一种具导磁件(ferromagneticmaterial)的电子封装件。
背景技术
随着电子产业的蓬勃发展,电子产品也逐渐迈向多功能、高性能的趋势。为了满足半导体封装件微小化(miniaturization)的封装需求,朝降低承载芯片的封装基板的厚度发展。电子产品能否达到轻、薄、短、小、快的理想境界,取决于芯片在高记忆容量,宽带及低电压化需求的发展,惟芯片能否持续提高记忆容量与操作频率并降低电压需求,端视芯片上电子电路与积体化的程度,以及作为提供电子电路讯号与电源传递媒介所用的输入/输出接脚(I/OConnector)密度而定。
一般半导体应用装置,例如通讯或高频半导体装置中,常需要将电阻器、电感器、电容器及振荡器(oscillator)等多数射频(radiofrequency)被动组件电性连接至所封装的半导体芯片,以使该半导体芯片具有特定的电流特性或发出讯号。
以球栅数组(BallGridArray,简称BGA)半导体装置为例,多数被动组件虽安置于基板表面,而为了避免该等被动组件阻碍半导体芯片与多数焊垫间的电性连结及配置,传统上多将该等被动组件安置于基板角端位置或半导体芯片接置区域以外基板的额外布局面积上。
然而,限定被动组件的位置将缩小基板线路布局(Routability)的灵活性;同时此举需考虑焊垫位置会导致该等被动组件布设数量受到局限,不利半导体装置高度集积化的发展趋势;甚者,被动组件布设数量随着半导体封装件高性能的要求而相对地遽增,如采现有方法该基板表面必须同时容纳多数半导体芯片以及较多被动组件而造成封装基板面积加大,进而迫使封装件体积增大,也不符合半导体封装件轻薄短小的发展潮流。
基于上述问题,遂将该多数被动组件制作成集总组件(如芯片型电感)整合至半导体芯片与焊垫区域间的基板区域上。如图1所示的半导体封装件1,其于一具有线路层11的基板10上设置一半导体芯片13及多个电感组件12,且该半导体芯片13藉由多个焊线130电性连接该线路层11的焊垫110。
然而,随着半导体装置内单位面积上输出/输入连接端数量的增加,焊线130的数量也随之提升,且一般电感组件12的高度(0.8毫米)高于该半导体芯片13的高度(0.55毫米),所以焊线130容易碰触该电感组件12而造成短路。
此外,若欲避免上述短路问题,需将该焊线130的弧度拉高并横越该电感组件12的上方,但此方式将提高焊接的困难度并增加制程复杂性,且增加该焊线130的弧线(WireLoop)的长度,所以将大幅提升该焊线130的制作成本,且该焊线130本身具有重量,若拉高的焊线130缺乏支撑,易因该焊线130本身重力崩塌(Sag)而碰触该电感组件12,因而导致短路。
又,该电感组件12为芯片型,所以其所需体积大,特别是电源电路所需的电感组件12,且寄生(parasitic)效应随着该电感组件12远离该半导体芯片13而增加。
另外,以线圈型电感12’取代该电感组件12,如图1’所示,以避免上述问题,但该线圈型电感12’仅设在该基板10上,使该线圈型电感12’所产生的电感模拟值为17nH(于2.0㎜×1.25㎜的面积上),致使该线圈型电感12’的电感值过小而不符合需求。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失,本发明为提供一种电子封装件,使该结构产生较高磁通量,进而增加电感量。
本发明的电子封装件,包括:基体,其具有相对的第一侧与第二侧;导磁件,其嵌埋于该基体中,且该导磁件具有与该第一侧同向的第一表面、相对该第一表面的第二表面、及邻接该第一与第二表面的侧面;以及导体结构,其设于该导磁件周围。
前述的电子封装件中,该基体包含具有开口的芯板,且该导磁件位于该开口中。
前述的电子封装件中,该基体包含封装胶体,使该导磁件嵌埋于该封装胶体中。
前述的电子封装件中,该导磁件为铁素体。
前述的电子封装件中,该导体结构为回状线圈,使该导磁件位于该回状线圈中。例如,该回状线圈的路径为依序经过该导磁件的第一表面、侧面、第二表面及侧面;或者,该回状线圈的路径为环绕该导磁件的侧面。
前述的电子封装件中,该导体结构具有分别设于该第一侧与第二侧上的金属层、及连通该第一侧与第二侧并连接该金属层的多个导电柱。
前述的电子封装件中,该导体结构接触该导磁件。例如,该导体结构包含形成于该导磁件上的多个导电迹线。
前述的电子封装件中,该导磁件外包覆有封装材,且该封装材嵌埋于该基体中。
另外,前述的电子封装件中,该导体结构为迹线层,且设于该导磁件的第一表面上方及/或第二表面上方,而未设于该导磁件的侧面上。
由上可知,本发明的电子封装件中,主要藉由该导体结构环绕该导磁件,使该导磁件与该导体结构产生的磁通量增加,以增加电感量,而增加电感值。
此外,藉由该导磁件的设计,可增加单一线圈的电感值,所以相较于现有无导磁件的线圈型电感,本发明可用较少的线圈数量达到相同的电感值,因而能微小化电感的体积。
附图说明
图1及图1’为现有半导体封装件的剖视示意图;
图2A为本发明的电子封装件的第一实施例的剖视示意图;其中,图2A’为图2A的局部立体图;
图2B为本发明的电子封装件的第二实施例的剖视示意图;其中,图2B’为图2B的局部立体分解图;
图3为本发明的电子封装件的第三实施例的剖视示意图;其中,图3’为图3的局部立体图,且图3”为图3的局部上视图;
图4为本发明的电子封装件的第四实施例的剖视示意图;以及
图5A及图5B为本发明的电子封装件的第五实施例的不同例的剖视示意图;其中,图5A’为图5的局部上视图。
主要组件符号说明
1半导体封装件
10基板
11线路层
110焊垫
12电感组件
12’线圈型电感
13半导体芯片
130焊线
2,2’,3,4,5,5’电子封装件
20,20’基体
20a第一侧
20b第二侧
200芯板
200a开口
200’封装胶体
201介电层
21导磁件
21a第一表面
21b第二表面
21c侧面
22,22’,32,52,52’导体结构
220,220’金属层
221导电柱
322导电迹线
44封装材。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用于配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用于限定本发明可实施的限定条件,所以不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语,也仅为便于叙述的明了,而非用于限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A及图2A’为本发明的电子封装件2的第一实施例的示意图。
如图2A及图2A’所示,该电子封装件2包括:一基体20、嵌埋于该基体20中的一导磁件21、设于该导磁件21周围的导体结构22、设于该基体20上的电子组件(图略)、以及结合该基体20的线路层(图略)。
所述的基体20具有相对的第一侧20a与第二侧20b,且该基体20包含一具有开口200a的芯板200及一覆盖该芯板200的介电层201,使该导磁件21位于该开口200a中,并以该介电层201包覆该导磁件21,其中,该介电层201的表面作为该第一侧20a的表面与该第二侧20b的表面。具体地,该芯板200为陶瓷基板、金属板、铜箔基板、线路板等。
所述的导磁件21为高磁导率(permeability)的导磁件,如铁素体(ferrite),其具有与该第一侧20a同向的第一表面21a、相对该第一表面21a的第二表面21b(其与该第二侧20b同向)、及邻接该第一与第二表面21a,21b的侧面21c,其中,该介电层201流入该开口200a中以包覆该导磁件21的第一表面21a、第二表面21b及侧面21c。
所述的导体结构22与该导磁件21产生磁通量,并使该导体结构22与该导磁件21构成电感。
所述的电子组件为主动组件、被动组件或其组合者,且该主动组件为例如半导体芯片,而该被动组件为例如电阻、电容及电感。于此,该电子组件为主动组件。
所述的线路层设于该芯板200与该介电层201上,且该线路层具有多个贯穿该芯板200与该介电层201的导电盲孔(图略)。
于本实施例中,该导体结构22为一横向回状线圈,使该导磁件21位于该回状线圈中,且该回状线圈的路径为依序经过该导磁件21的第一表面21a、侧面21c、第二表面21b及侧面21c。
具体地,该导体结构22具有分别设于该第一侧20a与第二侧20b上的金属层220、及连通该第一侧20a与第二侧20b并连接该金属层220的多个导电柱221,且该金属层220为直线状迹线层(如图2A’所示),使该金属层220的布设对应该导磁件21的第一表面21a及第二表面21b,而该些导电柱221的布设对应该导磁件21的侧面21c。
又,于制作时,先将该导磁件21放入该开口200a中,再形成该介电层201以包覆该导磁件21,之后制作该导体结构22。
另外,该金属层220与该导电柱221为铜材,且以布线(routing)制程制作。
图2B及图2B’为本发明的电子封装件2’的第二实施例的示意图。本实施例与第一实施例的差异在于回状线圈的实施例与基体的实施例,所以仅说明相异处,而其它相同处不再赘述。
如图2B及图2B’所示,该导体结构22’为一纵向回状线圈,且该回状线圈的路径为环绕该导磁件21的侧面21c。
于本实施例中,该金属层220’为绕圈状迹线层,且该金属层220’的布设对应该导磁件21的侧面21c,并使该些导电柱221迭架各该金属层220’。
此外,该金属层220’为铜层,且以布线(routing)制程制作。
又,该基体20’以模压(molding)制程制作的封装胶体200’取代芯板200,使该导磁件21嵌埋于该封装胶体200’中,且可选择性形成该介电层201。具体地,若该封装胶体200’外露该导磁件21的第一表面21a及/或第二表面21b,该介电层201将压合于该导磁件21的第一表面21a及/或第二表面21b上,如图2B所示,该介电层201覆盖该导磁件21的第一表面21a及第二表面21b;若该封装胶体200’包覆该导磁件21的第一表面21a、第二表面21b及侧面21c时,则可省略该介电层201的制作。
另外,也可将封装胶体200’应用于第一实施例的电子封装件。
图3、图3’及图3”为本发明的电子封装件3的第三实施例的示意图。本实施例与第一实施例的差异在于回状线圈的设计,所以仅说明相异处,而其它相同处不再赘述。
如图3、图3’及图3”所示,该导体结构32接触该导磁件21。
于本实施例中,该导体结构32包含附着于该导磁件21上的多个导电迹线322,且该导电迹线322自该第一表面21a经该侧面21c而延伸至该第二表面21b,使该导电柱221接触该第一表面21a与该第二表面21b上的导电迹线322,以令该导体结构32构成另一横向回状线圈,且该导磁件21位于该回状线圈中。
此外,该导电迹线322可用溅镀(Sputtering)、涂布(coating)或电镀(plating)制程制作。
另外,也可将导电迹线322应用于第二实施例的电子封装件,且该金属层220’或导电柱221接触该导电迹线322。
图4为本发明的电子封装件4的第四实施例的剖视示意图。本实施例与第一实施例的差异在于导磁件的设计,所以仅说明相异处,而其它相同处不再赘述。
如图4所示,该导磁件21外包覆有封装材44,使该封装材44嵌埋于该基体20中。
于本实施例中,先将封装材44包覆该导磁件21,再一并埋设于该开口200a中,并以该介电层201包覆该封装材44。具体地,该封装材44覆盖该导磁件21的第一表面21a、第二表面21b及侧面21c。
此外,该金属层220为线路重布层(Redistributionlayer,简称RDL),所以该金属层220可与该线路层一同制作于该芯板200或该介电层201上。
另外,也可将该导磁件21外包覆有封装材44的实施例应用于第二及第三实施例的电子封装件。
图5A、图5A’及图5B为本发明的电子封装件5,5’的第五实施例的示意图。本实施例与第一实施例的差异在于该导体结构的实施例,所以仅说明相异处,而其它相同处不再赘述。
如图5A及图5A’所示,该导体结构52为绕圈状迹线层且无导电柱,该导体结构52设于该导磁件21的第一表面21a上方及/或第二表面21b上方,而未设于该导磁件21的侧面21c。
于本实施例中,该导体结构52设于对应该导磁件21的第一表面21a上的该基体20的第一侧20a上,如图5A’所示,该导体结构52盘据于该第一表面21a上方。
或者,如图5B所示,该导体结构52’设于对应该导磁件21的第一表面21a上的该基体20的第一侧20a上、及对应该导磁件21的第二表面21b上的该基体20的第二侧20b上。
另外,也可将封装胶体200’、导电迹线322与导电柱221、封装材44等结构应用于第五实施例的电子封装件。
本发明的电子封装件2,2’,3,4,5,5’藉由该导体结构22,22’,32,52,52’环绕该导磁件21,使磁场将趋向于集中在低磁阻的铁磁路径(ferromagneticpath),即该导磁件21,因而得以增加磁通量,进而增加电感量,使本发明的电感值可提高至75nH(Henry)(远大于现有技术的17nH)。
此外,本发明藉由该导磁件21的设计,可增加单一线圈的电感值,所以相较于现有无磁铁的线圈型电感,本发明可用较少的线圈数量达到相同的电感值。例如,现有线圈型电感需三圈线圈才能达到17nH,而本发明的回状线圈仅需一圈即可达到17nH。
又,本发明的电感由该导体结构22,22’,32,52,52’与该导磁件21所构成,所以能依需求微小化电感的体积。例如,欲达到相同的电感值,本发明的回状线圈的圈数少于现有线圈型电感的圈数圈,因而减少电感的体积,且该导磁件21内部可无需设计线路(即纯导磁材质),因而其体积可依需求减少,所以本发明的电感符合微小化的需求。
因此,相较于现有技术,本发明的电子封装件2,2’,3,4,5,5’能以更小的布设范围制作电感并产生更大的电感值。
上述实施例仅用于例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (12)
1.一种电子封装件,其特征为,该封装件包括:
基体,其具有相对的第一侧与第二侧;
导磁件,其嵌埋于该基体中,且该导磁件具有与该第一侧同向的第一表面、相对该第一表面的第二表面、及邻接该第一与第二表面的侧面;以及
导体结构,其设于该导磁件周围。
2.根据权利要求1所述的电子封装件,其特征为,该基体包含具有开口的芯板,且该导磁件位于该开口中。
3.根据权利要求1所述的电子封装件,其特征为,该基体包含封装胶体,使该导磁件嵌埋于该封装胶体中。
4.根据权利要求1所述的电子封装件,其特征为,该导磁件为铁素体。
5.根据权利要求1所述的电子封装件,其特征为,该导体结构为回状线圈,使该导磁件位于该回状线圈中。
6.根据权利要求5所述的电子封装件,其特征为,该回状线圈的路径依序经过该导磁件的第一表面、侧面、第二表面及侧面。
7.根据权利要求5所述的电子封装件,其特征为,该回状线圈的路径为环绕该导磁件的侧面。
8.根据权利要求1所述的电子封装件,其特征为,该导体结构具有分别设于该第一侧与第二侧上的金属层、及连通该第一侧与第二侧并连接该金属层的多个导电柱。
9.根据权利要求1所述的电子封装件,其特征为,该导体结构接触该导磁件。
10.根据权利要求9所述的电子封装件,其特征为,该导体结构包含形成于该导磁件上的多个导电迹线。
11.根据权利要求1所述的电子封装件,其特征为,该导磁件外包覆有封装材,且该封装材嵌埋于该基体中。
12.根据权利要求1所述的电子封装件,其特征为,该导体结构为迹线层,且设于该导磁件的第一表面上方及/或第二表面上方。
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