CN104867894A - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

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Publication number
CN104867894A
CN104867894A CN201410081790.0A CN201410081790A CN104867894A CN 104867894 A CN104867894 A CN 104867894A CN 201410081790 A CN201410081790 A CN 201410081790A CN 104867894 A CN104867894 A CN 104867894A
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China
Prior art keywords
semiconductor chip
passive component
semiconductor
semiconductor package
package part
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CN201410081790.0A
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English (en)
Inventor
石啟良
钟兴隆
朱德芳
杨胜明
陈宏成
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN104867894A publication Critical patent/CN104867894A/zh
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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing & Machinery (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

一种半导体封装件及其制法，该制法先提供一封装基板，其具有相对的第一表面与第二表面，该第一表面具有多个焊垫，再于该第一表面上设置多个被动组件，且于该等被动组件上设置一半导体芯片，于该半导体芯片上设置有粘着膜，以供该半导体芯片藉由该粘着膜设置于该等被动组件上，接着藉由多个焊线电性连接该半导体芯片与焊垫，最后，于该封装基板的第一表面上形成封装胶体，以包覆该半导体芯片、被动组件与焊线。本发明能解决现有的将被动组件安置于基板角端位置或半导体芯片接置区域以外的布局面积的缺点，以及避免现有的焊线容易触及被动组件而造成短路的缺点。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件及其制法，尤指一种具有被动组件的半导体封装件及其制法。
背景技术
电子产品能否达到轻、薄、短、小、快的理想境界，主要取决于集成电路（IC）组件在高记忆容量、宽频及低电压化需求的发展，然而，集成电路组件能否持续提高记忆容量与操作频率并降低电压需求，端视集成电路组件上的电子电路与电子组件积体化的程度以及作为提供电子电路讯号与电源传递媒介所用的输入／输出连接件(I/Oconnector)的密度而定。
目前，为了符合业界的需求，让球栅数组(BGA)封装型式的半导体装置能容纳较多例如电容器、电阻器、电感器或振荡器等的被动组件(passive device)已蔚为球栅数组封装型式的半导体装置的主流。
某些例如通讯或高频半导体装置的半导体应用装置常需要将许多电阻器、电感器、电容器及振荡器等被动组件电性连接至所封装的半导体芯片，俾使该半导体芯片具有特定的电流特性或发出特定的电讯号。
图1所示者，为现有的球栅数组封装型式的半导体装置的立体图。如图所示，多个被动组件11虽安置于基板10表面，但是为了避免该等被动组件11阻碍半导体芯片12与多个焊指垫(bonding fingers)（未图标）间的电性连接以及半导体芯片12与多个焊指垫的配置，传统上多将该等被动组件11安置于基板10的角端位置或半导体芯片12接置区域以外的基板10的额外布局面积上。
然而，限制被动组件11的设置位置将会减少基板10的线路布局(routability)的灵活性，且限制焊指垫的位置亦导致该等被动组件11的布设数量受到局限，而不利半导体装置的高度集积化的发展趋势；甚者，被动组件11的布设数量随着半导体封装件的高性能的要求而相对地遽增，倘若采取前述现有方法，该基板10的表面必须同时容纳许多半导体芯片12及许多被动组件11，造成基板10的面积加大，进而迫使封装件的体积增大，也不符合半导体封装件轻薄短小的发展潮流。
基于上述问题，遂有人构想将多个被动组件整合至半导体芯片与焊指垫区域间的基板区域上，如图2所示的另一种现有的球栅数组封装型式的半导体装置的剖视图；然而，随着半导体装置内的单位面积的输出／输入连接件的数量增加，焊线21的数量也随之提升；此外，一般被动组件22的高度（例如0.8毫米）高于半导体芯片23的高度（例如0.55毫米），所以如欲避免焊线21触及被动组件22而造成短路，则需要拉高焊线21并使之横越该被动组件22的正上方，导致焊接的困难度提升并增加制程复杂性，也使得焊线21的线弧(wire loop)长度增加，且由于焊线21本身多是由金或铝等材质制成，故增长焊线21的线弧长度将明显提升焊线21的成本；况且，焊线21本身具有重量，拉高的焊线21若缺乏支撑，容易因本身重力崩塌(sag)而触及被动组件22并产生短路。
因此，如何避免上述现有技术中的种种问题，实为目前业界所急需解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明的主要目的为提供一种半导体封装件及其制法，能解决现有的将被动组件安置于基板角端位置或半导体芯片接置区域以外的布局面积的缺点。
本发明的半导体封装件包括：封装基板，其具有相对的第一表面与第二表面，该第一表面具有多个焊垫；多个被动组件，其设于该第一表面上；粘着膜，其粘设于该多个被动组件上；半导体芯片，其粘设于该粘着膜上而使该粘着膜位于该半导体芯片与被动组件之间；多个焊线，其电性连接该半导体芯片与焊垫；以及封装胶体，其形成于该封装基板的第一表面上，以包覆该半导体芯片、被动组件与焊线。
于前述的半导体封装件中，该第一表面具有一半导体芯片设置区，供该多个被动组件设于该半导体芯片设置区中，且令该多个焊垫围设于该半导体芯片设置区外。
于前述的半导体封装件中，还包括多个设于该封装基板的第二表面上的导电组件。
于本发明的半导体封装件中，该导电组件为焊球，且该被动组件为电容器、电阻器、电感器或振荡器。
本发明还提供一种半导体封装件的制法，包括：提供一封装基板，其具有相对的第一表面与第二表面，且该第一表面具有多个焊垫；于该第一表面上设置多个被动组件；于该等被动组件上设置一粘着膜与一半导体芯片，以使该粘着膜位于该半导体芯片与被动组件之间；藉由多个焊线电性连接该半导体芯片与焊垫；以及于该封装基板的第一表面上形成封装胶体，以包覆该半导体芯片、被动组件与焊线。
于前述的半导体封装件的制法中，该粘着膜先设于该半导体芯片上，且其制备的步骤包括：于一具有多个该半导体芯片的半导体晶圆的一表面上接置该粘着膜；以及进行切单步骤。
依上所述的半导体封装件的制法，该第一表面具有一半导体芯片设置区，供该多个被动组件设于该半导体芯片设置区中，且令该多个焊垫围设于该半导体芯片设置区外，于形成该封装胶体之后，还包括于该封装基板的第二表面上设置多个导电组件，该导电组件为焊球，且该被动组件为电容器、电阻器、电感器或振荡器。
由上可知，本发明的被动组件不会额外占用封装基板的面积，而能维持线路布局的灵活性；再者，该被动组件并不会有焊线接触被动组件而短路的问题存在，进而能提高产品良率与提升产品信赖度。
附图说明
图1所示者为现有的球栅数组封装型式的半导体装置的立体图。
图2所示者为另一种现有的球栅数组封装型式的半导体装置的剖视图。
图3A至图3F所示者为本发明的半导体封装件的制法的剖视图，其中，图3F’为图3F的另一实施例。
符号说明
10           基板
11、22、31   被动组件
12、23、401  半导体芯片
21、32       焊线
30           封装基板
30a          第一表面
30b          第二表面
301          焊垫
33           封装胶体
34           导电组件
40           半导体晶圆
41           粘着膜
A            半导体芯片设置区。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的用语亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图3A至图3F所示者，为本发明的半导体封装件的制法的剖视图，其中，图3F’为图3F的另一实施例。
首先，如图3A所示，提供一封装基板30，其具有相对的第一表面30a与第二表面30b，且该第一表面30a具有一半导体芯片设置区A与围设于该半导体芯片设置区A外的多个焊垫301。
如图3B所示，于该第一表面30a的半导体芯片设置区A上设置多个被动组件31，该被动组件31为电容器、电阻器、电感器或振荡器。
如图3C所示，于一具有多个半导体芯片401的半导体晶圆40的一表面上接置粘着膜41，并进行切单步骤。
如图3D所示，藉由该粘着膜41将该半导体芯片401设置于该等被动组件31上。
如图3E所示，藉由多个焊线32电性连接该半导体芯片401与焊垫301。
如图3F所示，于该封装基板30的第一表面30a上形成封装胶体33，以包覆该半导体芯片401、被动组件31与焊线32，并于该封装基板30的第二表面30b上设置多个导电组件34，该导电组件34例如为焊球。
要补充说明的是，本发明的被动组件31并不限于完全在该半导体芯片401对该封装基板30的投影范围内，而也可部分超出该半导体芯片401对该封装基板30的投影范围，如图3F’所示。
本发明还提供一种半导体封装件，包括：一封装基板30，其具有相对的第一表面30a与第二表面30b，该第一表面30a具有一半导体芯片设置区A与围绕该半导体芯片设置区A的多个焊垫301；多个被动组件31，其设于该第一表面30a的半导体芯片设置区A上；粘着膜41，其粘设于该多个被动组件31上；一半导体芯片401，其粘设于该粘着膜41上而使该粘着膜41位于该半导体芯片401与被动组件31之间；多个焊线32，其电性连接该半导体芯片401与焊垫301；以及封装胶体33，其形成于该封装基板30的第一表面30a上，以包覆该半导体芯片401、被动组件31与焊线32。
前述的半导体封装件中，该第一表面30a具有一半导体芯片设置区A，供该多个被动组件31设于该半导体芯片设置区A中，且令该多个焊垫301围设于该半导体芯片设置区A外，且还包括多个设于该封装基板30的第二表面30b上的导电组件34。
依前所述的半导体封装件，该导电组件34为焊球，且该被动组件31为电容器、电阻器、电感器或振荡器。
综上所述，相较于现有技术，由于本发明的被动组件设置于半导体芯片设置区中，所以不会额外占用封装基板的面积，并能维持线路布局的灵活性；此外，该被动组件并不干涉焊线的设置且并非位于焊线的线弧下方，因而不会有焊线接触被动组件而短路的问题存在，进而能提高产品良率与提升产品信赖度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (11)

1.一种半导体封装件，其包括：
封装基板，其具有相对的第一表面与第二表面，该第一表面具有多个焊垫；
多个被动组件，其设于该第一表面上；
粘着膜，其粘设于该多个被动组件上；
半导体芯片，其粘设于该粘着膜上而使该粘着膜位于该半导体芯片与被动组件之间；
多个焊线，其电性连接该半导体芯片与焊垫；以及
封装胶体，其形成于该封装基板的第一表面上，以包覆该半导体芯片、被动组件与焊线。
2.如权利要求1所述的半导体封装件，其特征在于，该第一表面具有一半导体芯片设置区，供该多个被动组件设于该半导体芯片设置区中，且令该多个焊垫围设于该半导体芯片设置区外。
3.如权利要求1所述的半导体封装件，其特征在于，该半导体封装件还包括多个设于该封装基板的第二表面上的导电组件。
4.如权利要求3所述的半导体封装件，其特征在于，该导电组件为焊球。
5.如权利要求1所述的半导体封装件，其特征在于，该被动组件为电容器、电阻器、电感器或振荡器。
6.一种半导体封装件的制法，包括：
提供一封装基板，其具有相对的第一表面与第二表面，且该第一表面具有多个焊垫；
于该第一表面上设置多个被动组件；
于该等被动组件上设置一粘着膜与一半导体芯片，以使该粘着膜位于该半导体芯片与被动组件之间；
藉由多个焊线电性连接该半导体芯片与焊垫；以及
于该封装基板的第一表面上形成封装胶体，以包覆该半导体芯片、被动组件与焊线。
7.如权利要求6所述的半导体封装件的制法，其特征在于，该第一表面具有一半导体芯片设置区，供该多个被动组件设于该半导体芯片设置区中，且令该多个焊垫围设于该半导体芯片设置区外。
8.如权利要求6所述的半导体封装件的制法，其特征在于，该粘着膜先设于该半导体芯片上，且其制备的步骤包括：
于一具有多个该半导体芯片的半导体晶圆的一表面上接置该粘着膜；以及
进行切单步骤。
9.如权利要求6所述的半导体封装件的制法，其特征在于，于形成该封装胶体之后，还包括于该封装基板的第二表面上设置多个导电组件。
10.如权利要求9所述的半导体封装件的制法，其特征在于，该导电组件为焊球。
11.如权利要求6所述的半导体封装件的制法，其特征在于，该被动组件为电容器、电阻器、电感器或振荡器。
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Application publication date: 20150826