CN104205327B - 半导体组件及其制造方法 - Google Patents

半导体组件及其制造方法 Download PDF

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CN104205327B
CN104205327B CN201280072193.0A CN201280072193A CN104205327B CN 104205327 B CN104205327 B CN 104205327B CN 201280072193 A CN201280072193 A CN 201280072193A CN 104205327 B CN104205327 B CN 104205327B
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wiring
semiconductor
pattern layer
conductive component
seal member
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CN104205327A (zh
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苏赛贤
萧元甄
王传伟
苏孝文
陈浩洋
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NEPES
Nepes Co Ltd
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Abstract

本发明提供一种包括精密且工序缺陷低的穿过布线的制造半导体组件的方法，本发明的一个实施例的制造半导体组件的方法包括如下步骤：准备导电部件的步骤；去除导电部件的一部分而形成平面部和从平面部突出的突出部的步骤；形成密封导电部件的密封部件的步骤；去除密封部件的一部分而使导电部件的突出部从密封部件露出来形成穿过布线的步骤；在穿过布线上形成与穿过布线电连接的再布线图案层的步骤；在再布线图案层上安装半导体芯片的步骤；以及形成与穿过布线电连接的外部连接部件的步骤。

Description

半导体组件及其制造方法
技术领域
本发明的技术思想涉及一种半导体组件，更详细而言，涉及一种包括穿过布线的半导体组件及其制造方法。
背景技术
近年来，半导体元件随着工序技术的微细化和功能的多样化，芯片尺寸减小，且伴随输出、输入端子数量的增加，电极焊盘间距逐渐微细化，随着各种功能的融合化的加速化，将各种元件集成于一个封装内的系统级封装技术逐渐兴起。并且，系统级封装技术中，为了将动作间噪音最小化并提高信号速度，逐渐变更为能够维持较短的信号距离的三维层叠技术方式。另一方面，为了应对这种技术的改善要求的同时，为了控制产品价格上升且为了提高生产率、降低制造成本，导入了包括多个半导体芯片的半导体组件。
当在现有的封装中层叠多个半导体芯片的情况下，为了相互连接上侧半导体芯片和下侧半导体芯片，通常在形成下侧半导体芯片的扇出式封装之后，在封装模型上通过激光钻头等形成通孔，在所述通孔中填充导电性物质来形成穿过布线。但存在难以精密地形成在封装模型上形成的通孔且难以在所述通孔中致密地填充导电性物质的局限性。
发明内容
(一)要解决的技术问题
本发明的技术思想所要完成的技术课题在于提供一种包括精密且工序缺陷低的穿过布线的制造半导体组件的方法。
(二)技术方案
用于实现上述技术课题的本发明的技术思想的制造半导体组件的方法，其包括如下步骤：准备导电部件的步骤；去除所述导电部件的一部分而形成平面部和从所述平面部突出的突出部的步骤；形成密封所述导电部件的密封部件的步骤；去除所述密封部件的一部分使所述导电部件的所述突出部从所述密封部件露出来形成穿过布线的步骤；在所述穿过布线上形成与所述穿过布线电连接的再布线图案层的步骤；在所述再布线图案层上安装半导体芯片的步骤；以及形成与所述穿过布线电连接的外部连接部件的步骤。
用于解决上述技术课题的本发明的技术思想的半导体组件，其利用上述的制造方法进行制造，所述半导体组件包括：穿过布线，利用去除导电部件的一部分而形成的突出部来形成；再布线图案层，位于所述穿过布线上，并且与所述穿过布线电连接；半导体芯片，位于所述再布线图案层上，并且与所述再布线图案层电连接；以及外部连接部件，与所述穿过布线电连接。
(三)有益效果
本发明的技术思想的半导体组件，与现有的填充通孔来形成穿过布线的情况相比，由于预先从导电部件形成突出部，利用所述突出部形成穿过布线，因此能够提供精密且工序缺陷低的穿过布线。
并且，不要求用于形成所述穿过布线的在密封部件上进行通孔形成工序和用导电物填充所述通孔的填充工序，因此制造工序变得简单，能够提供产率增加、工序费用减少的效果。
附图说明
图1是表示本发明的一个实施例的半导体组件的俯视图。
图2是沿着A-A线切割本发明的一个实施例的图1的半导体组件的剖视图。
图3至图22是按照工序步骤表示制造本发明的一个实施例的图1的制造半导体组件的方法的剖视图。
图23是表示本发明的一个实施例的半导体组件的剖视图。
图24是表示本发明的一个实施例的半导体组件的剖视图。
具体实施方式
以下，参照附图对本发明的优选实施例进行详细说明。本发明的实施例是为了向该技术领域的技术人员更完整地说明本发明的技术思想而提供的，以下实施例可以变更为多种其他方式，本发明的技术思想的范围并不限定于以下实施例，而是这些实施例使本发明公开内容更充实、完整，是为了向本领域技术人员完整地传达本发明的技术思想而提供的。如本说明书中所使用的术语“和/或”包括相应列举的项目中任意一个和一个以上的所有组合。相同符号始终意味着相同的要件。并且，附图中的各种要件和区域是概略描绘。因此，本发明的技术思想并不受附图中绘出的相对的大小或间隔的限制。
图1是表示本发明的一个实施例的半导体组件100的俯视图。图2是沿着A-A线切割本发明的一个实施例的图1的半导体组件100的剖视图。
参照图1和图2，半导体组件100包括穿过布线110、半导体芯片120、密封部件130、再布线图案层140、底部填充层160及外部连接部件170。
穿过布线110可以位于穿过密封部件130的位置。穿过布线110能够通过再布线图案层140与半导体芯片120电连接。即，穿过布线110能够通过再布线图案144和半导体芯片连接部件124与半导体芯片120的半导体芯片焊盘122电连接。如参照以下的图3至图22所说明，穿过布线110能够利用从导电部件111(参照图4)形成的突出部113(参照图4)来形成。
从密封部件130露出的穿过布线110可以具有与密封部件130的表面135相比凹陷的表面115。作为代替方案，密封部件的130的表面和穿过布线110的露出的表面可以位于同一平面上。
密封部件130可以包括绝缘物，例如可以包括环氧模塑化合物(epoxy moldcompound，EMC)。
再布线图案层140可以位于密封部件130和穿过布线110上，能够与穿过布线110电连接。与再布线图案层140连接的穿过布线110的表面116可以位于与密封部件130的表面136同一平面上。再布线图案层140可以包括第一绝缘层142、再布线图案144及第二绝缘层146。再布线图案144可以被第一绝缘层142和第二绝缘层146包围。再布线图案144可以包括导电物，例如可以包括金属，可以包括铜、铜合金、铝或铝合金。再布线图案144能够对穿过布线110进行再布线，和/或能够对半导体芯片120进行再布线。因此，再布线图案144能够将半导体芯片120的输出、输入端子微细化，并且能够增加所述输出、输入端子的数量。并且，通过再布线图案144，半导体组件100能够具有扇出式结构。
并且，再布线图案层140可以由预先制造的结构体构成，这种结构体通过压接、粘结、回流等方式粘结在密封部件130上的情况也属于本发明的技术思想。
半导体芯片120可以位于再布线图案层140上，与再布线图案层140电连接。例如，半导体芯片120的半导体芯片焊盘122能够通过半导体芯片连接部件124与再布线图案层140的再布线图案144电连接。半导体芯片120可以为存储器芯片或逻辑芯片。这种存储器芯片例如可以包括动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、闪存(flash)、相变化存储器(PRAM)、可变电阻式存储器(ReRAM)、铁电存储器(FeRAM)或非挥发性的磁性随机存储器(MRAM)。这种逻辑芯片可以为控制存储器芯片的控制器。
半导体芯片120能够通过半导体芯片连接部件124的高度与再布线图案层140分开。作为代替方案，半导体芯片120与再布线图案层140接触的情况也属于本发明的技术思想。此时，半导体组件100可以不包括底部填充层160。
底部填充层160可以位于半导体芯片120与再布线图案层140之间，以便填充半导体芯片120与再布线图案层140之间的空间。底部填充层160能够填充半导体芯片连接部件124之间的空间。底部填充层160可以包括绝缘物，例如可以为环氧模塑化合物、二氧化硅、树脂、玻璃质物质或聚合物等。底部填充层160能够实施以半导体芯片120与再布线图案层140接触的状态进行固定的功能，为此，可以具有能够防止由外部冲击引起的龟裂的适当的韧性(toughness)。
外部连接部件170能够在再布线图案层140的相反位置与穿过布线110电连接，由此能够通过再布线图案层140与半导体芯片120电连接。并且，外部连接部件170能够将半导体芯片120与外部装置电连接。为了外部连接部件170与穿过布线110的电连接，穿过布线110可以具有凹陷的表面115，外部连接部件170能够通过密封部件130并排和/或固定。外部连接部件170可以与穿过布线110垂直地位于相同的位置。外部连接部件170可以包括导电物，例如可以包括金属。外部连接部件170可以为锡球。
如图1所示，半导体芯片120可以位于半导体组件100的中央部分。但是，这仅仅是例示，本发明的技术思想并不限定于此，半导体芯片120位于半导体组件100的任意部分的情况也属于本发明的技术思想。
外部连接部件170可以位于半导体芯片120的外围。并且，外部连接部件170可以位于与半导体芯片120重叠的位置。图1所示的外部连接部件170的排列仅仅是例示，本发明的技术思想并不限定于此，外部连接部件170的多种排列属于本发明的技术思想。
图3至图22是按照工序步骤表示制造本发明的一个实施例的图1的半导体组件100的制造方法的剖视图。
参照图3，准备导电部件111。导电部件111可以具有平板形状。导电部件111可以包括导电性物质，例如可以包括金属。导电部件111例如可以包括铜、铜合金、铝或铝合金。
参照图4，去除导电部件111的一部分而形成平面部112和从平面部112突出的突出部113。可以将所述工序称为半蚀刻(half etching)工序，但并不限定于突出部113的高度与平面部112的高度相同的情况。突出部113的高度可以具有与在后续的工序中形成的穿过布线110(参照图11)相同的高度或比其略高的高度。平面部112的高度可以多种变更，为了后续的去除工序，越薄越优选，但为了防止导电部件111的挠曲现象等，可以具有一定的厚度。这种形成突出部113的工序可以利用光刻和蚀刻工序去除导电部件111的一部分来实施。作为代替方案，可以利用冲压装置，通过将导电部件111压接在模型来形成突出部113。在形成突出部113之后，为了去除不需要的残留物，还可以实施清洗工序。
参照图5，将导电部件111粘合在第一载体基板119上。例如，导电部件111能够利用第一粘结部件118粘合在第一载体基板119上。平面部112可以面向第一载体基板119，且能够与第一粘结部件118接触。第一载体基板119可以包括硅(silicon)、玻璃(glass)、陶瓷(ceramic)、塑料(plastic)或聚合物(polymer)。第一粘结部件118可以为液态粘结剂或粘结胶带。
参照图6，形成密封导电部件111的密封部件130。并且，密封部件130能够填充导电部件111的突出部113之间。并且，密封部件130可以覆盖导电部件111。密封部件130可以包括绝缘物，例如可以包括环氧模塑化合物。
参照图7，去除密封部件130的一部分而使导电部件111的突出部113从密封部件130露出。所述去除工序可以利用抛光、回蚀或机械化学抛光(mechanical chemicalpolishing，CMP)来实施。
参照图8，在密封部件130上粘合第二粘结部件138。由此能够在露出的导电部件111上粘合第二粘结部件138。第二粘结部件138可以为液态粘结剂或粘结胶带。第一粘结部件118和第二粘结部件138可以包括相同的物质，或者包括互不相同的物质。
参照图9，在第二粘结部件138上粘合第二载体基板139。即，第二载体基板139粘合在导电部件111的露出的突出部113上。由此，第二载体基板139以导电部件111为基准沿相对于第一载体基板119的相反方向粘合。第二载体基板139可以包括硅、玻璃、陶瓷、塑料或聚合物。第一载体基板119和第二载体基板139可以包括相同的物质，或者包括互不相同的物质。
参照图10，去除第一载体基板119和第一粘结部件118。并且，进行翻转以使导电部件111的平面部112朝上侧。
参照图11，去除密封部件130的一部分和导电部件111的平面部112而使导电部件111的突出部113从密封部件130露出。所述露出的导电部件111的突出部113形成穿过布线110。穿过布线110可以为硅通孔(through silicon via，TSV)或基板通孔(throughsubstrate via，TSV)。穿过布线110可以包括铜、铜合金、铝或铝合金。所述去除工序可以利用抛光、回蚀或机械化学抛光(mechanical chemical polishing，CMP)来实施。在形成穿过布线110之后，为了去除不需要的残留物，还可以实施清洗工序。
参照图12至图14，在穿过布线110上形成再布线图案层140。
参照图12，在密封部件130和露出的穿过布线110上形成第一绝缘层142。接着，去除第一绝缘层142的一部分，形成使穿过布线110露出的第一开口部141。第一绝缘层142可以包括绝缘物，例如可以包括氧化物、氮化物或环氧模塑化合物等。
参照图13，在第一绝缘层142上形成与穿过布线110电连接的再布线图案144。再布线图案144能够填充第一开口部141。再布线图案144可以包括导电物，例如可以包括金属，可以包括铜、铜合金、铝或铝合金。再布线图案144可以利用蒸镀、镀金等各种方法来形成。再布线图案144能够对穿过布线110进行再布线。
参照图14，在再布线图案144上形成第二绝缘层146。接着，去除第二绝缘层146的一部分而形成使重新布再布线图案144的一部分露出的第二开口部143。第二绝缘层146可以包括绝缘物，例如可以包括氧化物、氮化物或环氧模塑化合物等。第一绝缘层142和第二绝缘层146可以包括相同的物质，或者包括不同的物质。第一绝缘层142、再布线图案144及第二绝缘层146能够构成再布线图案层140。
并且，再布线图案层140可以由预先制造的结构体构成，这种结构体通过压接、粘结、回流等方式粘结在密封部件130的情况也属于本发明的技术思想。
参照图15，去除第二载体基板139和第二粘结部件138。由此能够使穿过布线110露出。具体而言，能够使位于再布线图案层140的相反侧的穿过布线110的表面露出。
参照图16，在再布线图案层140上粘合第三载体基板149。例如，第三载体基板149能够利用第三粘结部件148粘合在再布线图案层140上。第三载体基板149可以包括硅、玻璃、陶瓷、塑料或聚合物。第三粘结部件148可以为液态粘结剂或粘结胶带。第三载体基板149可以包括与第一载体基板119和/或第二载体基板139相同的物质，或者包括互不相同的物质。第三粘结部件148可以包括与第一粘结部件118和/或第二粘结部件138相同的物质，或者包括互不相同的物质。
图15和图16中示出的工序可以以相反的顺序实施。例如，可以在再布线图案层140上粘合第三载体基板149之后，去除第二载体基板139和第二粘结部件138。
参照图17，去除露出的穿过布线110的一部分而形成具有与密封部件130的表面135相比凹陷的表面115的穿过布线110。去除所述穿过布线110的一部分的步骤可以利用湿法蚀刻来实施。通过所述湿法蚀刻，能够对穿过布线110的表面进行清洗。
参照图18，去除第三载体基板149和第三粘结部件148。由此能够使再布线图案层140的再布线图案144露出。并且通过第二开口部143使再布线图案144露出。结果，能够构成包括穿过布线110和再布线图案层140的独立的结构体150。再布线图案层140的再布线图案144在结构体150的一侧露出，并且该一侧可以具有安装与再布线图案层140电连接的半导体芯片120(参照图19)的区域。穿过布线110在与所述一侧相反的另一侧从密封部件130露出，并且该另一侧可以具有粘合与穿过布线110电连接的外部连接部件170(参照图22)的区域。这种结构体150能够作为插入体发挥作用。
参照图19，在结构体150上安装半导体芯片120。例如，在再布线图案层140上安装半导体芯片120。半导体芯片120可以为存储器芯片或逻辑芯片。半导体芯片120可以包括一个半导体芯片，或者包括多个半导体芯片。半导体芯片120包括半导体芯片焊盘122。半导体芯片焊盘122上可以粘合如焊锡凸块的半导体芯片连接部件124。半导体芯片连接部件124能够与通过第二开口部143露出的再布线图案144接触而相互电连接。这种情况下，还可以实施回流工序将半导体芯片连接部件124粘合在再布线图案144。作为代替方案，在通过第二开口部143露出的再布线图案144形成半导体芯片连接部件124之后，可以以半导体芯片120的半导体芯片焊盘122和半导体芯片连接部件124电连接的方式，将半导体芯片120安装在结构体150上。
半导体芯片120可以通过再布线图案层140的再布线图案144进行再布线。由此，再布线图案144能够将半导体芯片120的输出、输入端子微细化，并且，能够增加所述输出、输入端子的数量。并且，通过再布线图案144，半导体组件100能够具有扇出式结构。
参照图20，示出通过图19的工序在结构体150上安装有半导体芯片120的最终结构体。通过半导体芯片连接部件124的高度，半导体芯片120与再布线图案层140分开。作为代替方案，第二开口部143的深度和半导体芯片连接部件124的高度相同而使半导体芯片120与再布线图案层140接触的情况也属于本发明的技术思想。
参照图21，在半导体芯片120的下侧形成底部填充(underfill)层160。底部填充层160填充半导体芯片120与再布线图案层140之间的空间。底部填充层160可以具有适当的粘度，以便填充半导体芯片连接部件124之间。底部填充层160可以包括绝缘物，例如可以为环氧模塑化合物、二氧化硅、树脂、玻璃质物质或聚合物等。可以利用液态底部填充物质填充半导体芯片120与再布线图案层140之间的空间之后，进行加热或干燥而使所述液态底部填充物质固态化，从而形成底部填充层160。
参照图22，形成与穿过布线110电连接的外部连接部件170。外部连接部件170可以包括导电物，例如可以包括金属。外部连接部件170可以为锡球。可以通过回流工序，在穿过布线110上粘合外部连接部件170。由此，完成半导体组件100。
图23是表示本发明的一个实施例的半导体组件200的剖视图。本实施例的半导体组件200是变更上述实施例的半导体组件中的一部分结构的半导体组件，因此，省略重复说明。
参照图23，半导体组件200包括穿过密封部件130的穿过布线110，位于穿过布线110上且与其电连接的再布线图案层140，位于再布线图案层140上且与其电连接的第一半导体芯片220a和第二半导体芯片220b，填充第一半导体芯片220a与再布线图案层140之间的空间和第二半导体芯片220b与再布线图案层140之间的空间以便将第一半导体芯片220a和第二半导体芯片220b固定在再布线图案层140的底部填充层160，以及在再布线图案层140的相反位置上与穿过布线110电连接的外部连接部件170。
第一半导体芯片220a和第二半导体芯片220b能够与图1的半导体芯片120类似地与再布线图案层140电连接。第一半导体芯片220a和第二半导体芯片220b可以具有相同的大小，或者具有互不相同的大小。第一半导体芯片220a和第二半导体芯片220b可以为存储器芯片或逻辑芯片。并且，第一半导体芯片220a和第二半导体芯片220b可以为具有相同的功能的同种产品，或者是具有互不相同的功能的异种产品。例如，第一半导体芯片220a可以为逻辑芯片，第二半导体芯片220b为存储器芯片，或者也可以与此相反。半导体组件200能够构成系统芯片(system on chip，SOC)或系统级封装(system in package，SIP)。并且，第一半导体芯片220a和/或第二半导体芯片220b分别是层叠有多个半导体芯片的结构体的情况也属于本发明的技术思想。
图23中示出第一半导体芯片220a和第二半导体芯片220b平面排列的情况，但垂直层叠的情况也属于本发明的技术思想。
图24是表示本发明的一个实施例的半导体组件300的剖视图。本实施例的半导体组件300是变更上述实施例的半导体组件中的一部分结构的半导体组件，因此，省略重复说明。
参照图24，半导体组件300包括穿过密封部件130的穿过布线110，位于穿过布线110上且与其电连接的再布线图案层140，位于再布线图案层140上且与其电连接的半导体芯片120，填充半导体芯片120与再布线图案层140之间的空间以便将半导体芯片120固定于再布线图案层140的底部填充层160，以及在与再布线图案层140相反的位置上与穿过布线110电连接的外部连接部件170。并且，还包括位于再布线图案层140上，密封半导体芯片120的外部密封部件380。外部密封部件380可以包括绝缘物，例如可以包括环氧模塑化合物。外部密封部件380能够实施从外部保护半导体芯片120的功能和/或向外部排出由半导体芯片120产生的热量的功能。外部密封部件380可以包括与密封部件130相同的物质，或者包括互不相同的物质。并且，外部密封部件380可以包括与底部填充层160相同的物质，或者包括互不相同的物质。
并且，在图24的半导体组件300上融合图23的半导体组件200的技术特征的情况也属于本发明的技术思想。
以上说明的本发明的技术思想并不限定于前述的实施例和附图，对于本发明所属技术领域的技术人员能够明确，在不脱离本发明的技术思想的范围内可以实施各种替换、变形及变更。
工业实用性
利用本发明，能够在半导体组件中制造出一种精密且工序缺陷低的穿过布线。

Claims (18)

1.一种制造半导体组件的方法，其包括如下步骤：
准备导电部件的步骤；
去除所述导电部件的一部分形成平面部和从所述平面部突出的突出部的步骤；
形成密封所述导电部件的密封部件的步骤；
去除所述密封部件的一部分使所述导电部件的所述突出部从所述密封部件露出来形成穿过布线的步骤；
在所述穿过布线上形成与所述穿过布线电连接的再布线图案层的步骤；
去除所述穿过布线的一部分形成具有与所述密封部件的表面相比凹陷的表面的穿过布线的步骤；
在所述再布线图案层上安装半导体芯片的步骤；以及
形成与所述穿过布线电连接的外部连接部件的步骤，
所述外部连接部件粘合在所述穿过布线的所述凹陷的表面。
2.根据权利要求1所述的制造半导体组件的方法，其特征在于，在实施安装所述半导体芯片的步骤之后，还包括形成填充所述半导体芯片与再布线图案层之间的空间的底部填充层的步骤。
3.根据权利要求1所述的制造半导体组件的方法，其特征在于，形成具有所述凹陷的表面的穿过布线的步骤利用湿法蚀刻来实施。
4.根据权利要求1所述的制造半导体组件的方法，其特征在于，在实施形成所述突出部的步骤之后，还包括为了在所述导电部件上去除不需要的残留物，对形成有所述突出部的所述导电部件进行清洗的步骤。
5.根据权利要求1所述的制造半导体组件的方法，其特征在于，形成所述穿过布线的步骤包括利用回蚀或机械化学抛光来去除所述密封部件的一部分和所述导电部件的所述平面部的步骤。
6.根据权利要求5所述的制造半导体组件的方法，其特征在于，
形成所述穿过布线的步骤在实施利用回蚀或机械化学抛光来去除所述密封部件的一部分和所述导电部件的所述平面部的步骤之后，
还包括为了去除不需要的残留物，对所述穿过布线进行清洗的步骤。
7.根据权利要求1所述的制造半导体组件的方法，其特征在于，
在实施形成所述密封部件的步骤之前，还包括将所述导电部件粘合在第一载体基板上的步骤。
8.根据权利要求7所述的制造半导体组件的方法，其特征在于，
使所述突出部露出形成所述穿过布线的步骤还包括如下步骤：
在所述露出的突出部上粘合第二载体基板的步骤；以及
去除所述第一载体基板的步骤。
9.根据权利要求8所述的制造半导体组件的方法，其特征在于，
在实施形成所述再布线图案层的步骤之后，还包括如下步骤：
去除所述第二载体基板的步骤；以及
在所述再布线图案层上粘合第三载体基板的步骤。
10.根据权利要求1所述的制造半导体组件的方法，其特征在于，
形成所述再布线图案层的步骤包括如下步骤：
在所述穿过布线上形成使所述穿过布线露出的第一绝缘层的步骤；
在所述第一绝缘层上形成与所述穿过布线电连接的再布线图案的步骤；以及
在所述再布线图案上形成使所述再布线图案的一部分露出的第二绝缘层的步骤。
11.根据权利要求1所述的制造半导体组件的方法，其特征在于，
形成所述突出部的步骤包括利用光刻和蚀刻工序去除所述导电部件的一部分形成所述突出部的步骤。
12.根据权利要求1所述的制造半导体组件的方法，其特征在于，
形成所述突出部的步骤包括冲压加工所述导电部件来形成所述突出部的步骤。
13.一种半导体组件，其包括：
穿过布线，用密封部件对去除导电部件的一部分形成的突出部进行密封而形成；
再布线图案层，位于所述穿过布线上，并且与所述穿过布线电连接；
半导体芯片，位于所述再布线图案层上，并且与所述再布线图案层电连接；以及
外部连接部件，与所述穿过布线电连接，
所述穿过布线具有与所述密封部件的表面相比凹陷的表面，
所述外部连接部件粘合在所述穿过布线的所述凹陷的表面上。
14.根据权利要求13所述的半导体组件，其特征在于，
所述半导体组件还包括填充所述半导体芯片与再布线图案层之间的空间的底部填充层。
15.根据权利要求13所述的半导体组件，其特征在于，
所述半导体芯片包括多个半导体芯片。
16.根据权利要求13所述的半导体组件，其特征在于，
所述半导体组件还包括外部密封部件，所述外部密封部件位于所述再布线图案层上，并且密封所述半导体芯片。
17.根据权利要求13所述的半导体组件，其特征在于，
所述穿过布线包括铜、铜合金、铝或铝合金。
18.根据权利要求13所述的半导体组件，其特征在于，
所述密封部件包括环氧模塑化合物。
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