CN101286502A - 半导体封装结构 - Google Patents
半导体封装结构 Download PDFInfo
- Publication number
- CN101286502A CN101286502A CNA2007102004577A CN200710200457A CN101286502A CN 101286502 A CN101286502 A CN 101286502A CN A2007102004577 A CNA2007102004577 A CN A2007102004577A CN 200710200457 A CN200710200457 A CN 200710200457A CN 101286502 A CN101286502 A CN 101286502A
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- semiconductor package
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供一种半导体封装结构,其包括一基板、至少一被动元件、一绝缘填充材料及一芯片。所述基板包括一封装面,所述封装面开设有一凹槽,所述至少一被动元件设置于所述凹槽内并与所述基板电性连接,所述绝缘填充材料填充于所述凹槽内并覆盖所述至少一被动元件,所述芯片设置于所述绝缘填充材料上并与所述基板电性连接。所述半导体封装结构在所述基板的封装面开设所述凹槽收容所述至少一被动元件,如此,可提高所述半导体封装结构的空间利用率,缩小所述半导体封装结构的尺寸。
Description
技术领域
本发明涉及半导体封装技术,特别涉及一种小尺寸的半导体封装结构。
背景技术
半导体封装结构主要包括芯片及封装外壳,封装外壳封装芯片,以保护芯片,避免其受到机械损害及电气侵扰。另外,半导体封装结构通常还包括电阻、电容、电感等被动元件,以配合芯片构成完整的电子系统。
请参阅图1,典型的半导体封装结构100a包括芯片11a、被动元件12a及基板13a。芯片11a及被动元件12a设置于基板13a上并与基板13a电连接,其中,芯片11a设置于基板13a中心处,被动元件12a绕设于芯片11a周围。然而,被动元件12a如此设置不利于半导体封装结构100a的小型化,且对芯片11a布线的空间造成限制。
发明内容
有鉴于此,有必要提供一种可缩小尺寸的半导体封装结构。
一种半导体封装结构,其包括一基板、至少一被动元件、一绝缘填充材料及一芯片。所述基板包括一封装面,所述封装面开设有一凹槽,所述至少一被动元件设置于所述凹槽内并与所述基板电性连接,所述绝缘填充材料填充于所述凹槽内并覆盖所述至少一被动元件,所述芯片设置于所述绝缘填充材料上并与所述基板电性连接。
所述半导体封装结构在所述基板的封装面开设所述凹槽收容所述至少一被动元件,如此,可提高所述半导体封装结构的空间利用率,缩小所述半导体封装结构的尺寸。
附图说明
图1为典型的半导体封装结构的俯视示意图;
图2为本发明第一实施例的半导体封装结构的剖面示意图;
图3为本发明第二实施例的半导体封装结构的剖面示意图。
具体实施方式
第一实施例
请参阅图2,本实施例的半导体封装结构100包括一基板10、至少一被动元件20、一绝缘填充材料30及一芯片40。所述基板10包括一封装面11,所述封装面11开设有一凹槽12。所述至少一被动元件20设置于所述凹槽12内且与所述基板10电性连接。所述绝缘填充材料30填充于所述凹槽12内并覆盖所述至少一被动元件20。所述芯片40设置于所述绝缘填充材料30上且与所述基板10电性连接。
所述基板10形成有电路(图未示),并在凹槽底面121及封装面11分别形成有多个与所述电路电性连接的第一焊盘13及第二焊盘14。具体地,所述基板10的下表面15还形成有多个第三焊盘16,用于与外部电路(图未示)电连接。所述第三焊盘可以是球栅阵列(Ball GridArray,BGA)、无引线芯片载体(Leadless Chip Carrier,LCC)或引线框(Leadframe)。
所述基板10可采用塑料、陶瓷或玻璃材料制成,本实施例的基板10采用塑料制成。具体地,塑料材料可采用掺有玻璃纤维的环氧树脂、掺有有机硅的环氧树脂或掺有芳香聚酰胺的环氧树脂制成,本实施例的基板10由掺有有机硅的环氧树脂制成。
所述凹槽12开设于所述封装面11的中央,其尺寸大于所述芯片40的尺寸,其深度大于所述绝缘填充材料30的厚度。即是说,所述绝缘填充材料30填充于所述凹槽12后形成的上表面31低于所述封装面11。如此,所述芯片40可收容于或部分收容于所述凹槽12内,降低所述半导体封装结构100的高度。
本实施例的芯片40部分收容于所述凹槽12内,以露出其上表面41,方便所述芯片40的布线作业。
所述至少一被动元件20为表面贴装元件(Surface Mounted Device,SMD),其通过表面贴装技术(Surface Mounted Technology,SMT)焊接于所述多个第一焊盘13上。
本实施例的绝缘填充材料30采用可固化接着剂,如此,所述芯片40可直接接着于所述绝缘填充材料30,进而固定所述芯片40。所述可固化接着剂可采用热固化接着剂或紫外光固化接着剂,并采用相应的热熟化或紫外熟化工艺固化所述可固化接着剂。
所述芯片40通过多条引线42电性连接至所述多个第二焊盘14,从而实现与所述基板电连接。所述引线42可采用金线、银线、铜线等良导体线材,本实施例的引线42采用金线。
具体地,本实施例的半导体封装结构100还包括一封装层50,其包覆于所述芯片40及引线42上,以保护所述芯片40及引线42,避免其受到机械损害及电气侵扰。本实施例的封装层50采用环氧树脂材料,其可通过转送成型法(Transfer Molding)或射出成型法(InjectionMolding)等成型方法成型,本实施例采用转送成型法形成所述封装层50。
所述半导体封装结构100在所述基板10的封装面11开设所述凹槽12收容所述至少一被动元件20,如此,可提高所述半导体封装结构100的空间利用率,缩小所述半导体封装结构100的尺寸,方便所述芯片40的布线作业。
另外,所述凹槽尺寸大于所述芯片40的尺寸,深度大于所述绝缘填充材料30的厚度,使得所述芯片40部分收容于所述凹槽12内,更进一步缩小所述半导体封装结构100的尺寸。
第二实施例
本实施例的芯片40为影像感测芯片,本实施例的半导体封装结构200与第一实施例的半导体封装结构100不同之处包括:
本实施例的绝缘填充材料60采用环氧树脂,其通过射出成型法等成型方法填充于所述凹槽12内,并形成一平整表面61。所述芯片40通过一接着层70设置于所述平整表面61上。所述接着层70可采用可固化接着剂或双面胶垫,本实施例采用可固化接着剂。
所述半导体封装结构200包括一可固化接着剂80及一透明板90,所述可固化接着剂80包覆于所述引线42与所述第二焊盘14,所述透明板90覆盖于所述影像感测芯片并接着于所述可固化接着剂80上。
应该指出,上述实施例仅为本发明的较佳实施方式,本领域技术人员还可在本发明精神内做其它变化。这些依据本发明精神所做的变化,都应包含在本发明所要求保护的范围之内
Claims (10)
1. 一种半导体封装结构,其包括一基板、至少一被动元件、一绝缘填充材料及一芯片;其特征在于,所述基板包括一封装面,所述封装面开设有一凹槽,所述至少一被动元件设置于所述凹槽内并与所述基板电性连接,所述绝缘填充材料填充于所述凹槽内并覆盖所述至少一被动元件,所述芯片设置于所述绝缘填充材料上并与所述基板电性连接。
2. 如权利要求1所述的半导体封装结构,其特征在于,所述凹槽的尺寸大于所述芯片的尺寸,所述凹槽的深度大于所述绝缘填充材料的厚度。
3. 如权利要求2所述的半导体封装结构,其特征在于,所述芯片全部或部分收容于所述凹槽内。
4. 如权利要求1所述的半导体封装结构,其特征在于,所述绝缘填充材料为可固化接着剂,所述芯片接着于所述绝缘填充材料。
5. 如权利要求1所述的半导体封装结构,其特征在于,所述绝缘填充材料为环氧树脂,所述芯片通过一接着层设置于所述填充材料上。
6. 如权利要求1所述的半导体封装结构,其特征在于,所述凹槽底面形成有多个第一焊盘,所述至少一被动元件为焊接于所述多个第一焊盘的表面贴装元件。
7. 如权利要求1所述的半导体封装结构,其特征在于,所述封装面形成有多个第二焊盘,所述半导体封装结构还包括多条电性连接所述芯片与所述多个第二焊盘的引线。
8. 如权利要求7所述的半导体封装结构,其特征在于,所述半导体封装结构还包括一封装层,所述封装层包覆于所述芯片及引线上。
9. 如权利要求8所述的半导体封装结构,其特征在于,所述封装层采用环氧树脂。
10. 如权利要求7所述的半导体封装结构,其特征在于,所述芯片为影像感测芯片,所述半导体封装结构还包括一可固化接着剂及一透明板,所述可固化接着剂涂布于所述影像感测芯片周围并包覆于所述引线与所述第二焊盘,所述透明板接着于所述可固化接着剂以密封所述影像感测芯片。
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WO2015109596A1 (zh) * | 2014-01-26 | 2015-07-30 | 清华大学 | 一种封装结构、封装方法及在封装方法中使用的模板 |
CN104867894A (zh) * | 2014-02-25 | 2015-08-26 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
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US20060051912A1 (en) * | 2004-09-09 | 2006-03-09 | Ati Technologies Inc. | Method and apparatus for a stacked die configuration |
US7342308B2 (en) | 2005-12-20 | 2008-03-11 | Atmel Corporation | Component stacking for integrated circuit electronic package |
US20080054490A1 (en) | 2006-08-31 | 2008-03-06 | Ati Technologies Inc. | Flip-Chip Ball Grid Array Strip and Package |
SG148054A1 (en) * | 2007-05-17 | 2008-12-31 | Micron Technology Inc | Semiconductor packages and method for fabricating semiconductor packages with discrete components |
US20120090883A1 (en) * | 2010-10-13 | 2012-04-19 | Qualcomm Incorporated | Method and Apparatus for Improving Substrate Warpage |
CN105977214A (zh) * | 2016-06-23 | 2016-09-28 | 华天科技(西安)有限公司 | 一种基于露芯塑封工艺的tsv芯片封装件及其制造方法 |
US11139268B2 (en) * | 2019-08-06 | 2021-10-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method of manufacturing the same |
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US6014586A (en) * | 1995-11-20 | 2000-01-11 | Pacesetter, Inc. | Vertically integrated semiconductor package for an implantable medical device |
US5963429A (en) * | 1997-08-20 | 1999-10-05 | Sulzer Intermedics Inc. | Printed circuit substrate with cavities for encapsulating integrated circuits |
US6228682B1 (en) * | 1999-12-21 | 2001-05-08 | International Business Machines Corporation | Multi-cavity substrate structure for discrete devices |
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WO2015109596A1 (zh) * | 2014-01-26 | 2015-07-30 | 清华大学 | 一种封装结构、封装方法及在封装方法中使用的模板 |
US9960093B2 (en) | 2014-01-26 | 2018-05-01 | Tsinghua University | Packaging structure, packaging method and template used in packaging method |
CN104867894A (zh) * | 2014-02-25 | 2015-08-26 | 矽品精密工业股份有限公司 | 半导体封装件及其制法 |
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