CN215220710U - 半导体设备 - Google Patents

半导体设备 Download PDF

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Publication number
CN215220710U
CN215220710U CN202023051748.4U CN202023051748U CN215220710U CN 215220710 U CN215220710 U CN 215220710U CN 202023051748 U CN202023051748 U CN 202023051748U CN 215220710 U CN215220710 U CN 215220710U
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laser direct
conductive
lds
substrate
electrical contact
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M·德赖
D·维特洛
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STMicroelectronics SRL
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STMicroelectronics SRL
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    • H—ELECTRICITY
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    • H01L2224/73227—Wire and HDI connectors
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82103—Forming a build-up interconnect by additive methods, e.g. direct writing using laser direct writing
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

本公开涉及半导体设备。一种系统级封装(SiP)半导体设备，包括激光直接结构化(LDS)材料的衬底。第一和第二半导体裸片被布置在LDS材料的衬底的相对表面处的第一和第二引线框架结构处。封装LDS材料被模制到LDS材料的衬底的第二表面上。第一半导体裸片和封装LDS材料位于LDS材料的衬底的相对侧上。一组电接触构造在封装模制材料的与LDS材料的衬底相对的表面处。引线框架结构包括经激光束处理的LDS材料。LDS材料的衬底和封装LDS材料包括形成至少一个导电过孔的经激光束处理的LDS材料，至少一个导电过孔提供导电线路的至少一部分，导电线路在第一半导体裸片与在封装模制材料的与衬底相对的表面处的电接触构造之间。根据本公开的半导体设备可以实现高设计灵活性。

Description

半导体设备
技术领域
本描述涉及半导体设备。
例如，一个或多个实施例可以实现为诸如集成电路(IC)的半导体设备。
背景技术
名称系统级封装(SiP)通常被应用于将多个集成电路和/或无源组件封闭在单个封装中的技术。
系统级封装布局受各种因素的影响，诸如裸片尺寸、裸片的相对位置(并排或堆叠)和键合焊盘(bonding pad)的位置。
无论封装多宽和设备灵活性如何，设备键合焊盘的定位都可以对SiP配置造成某些限制，导致设计约束。
结果，由于设计不兼容，相同设备可能不适合在两种不同的SiP布局中使用，这可能涉及新的设备设计。
实用新型内容
已知的解决方案中系统级封装布局受各种因素的影响，并且存在对封装配置的设计约束。因此，需要一种可以实现高设计灵活性的半导体设备。
根据本公开的第一方面，提供了一种半导体设备。该半导体设备包括：激光直接结构化衬底，衬底具有第一表面和第二表面，第二表面与第一表面相对；至少一个第一半导体裸片和至少一个第二半导体裸片，至少一个第一半导体裸片被布置在激光直接结构化衬底的第一表面处的第一引线框架结构处，至少一个第二半导体裸片被布置在激光直接结构化衬底的第二表面处的第二引线框架结构处；封装激光直接结构件，被模制到激光直接结构化衬底的第二表面上，第二表面具有被布置在第二引线框架结构处的至少一个第二半导体裸片，其中至少一个第一半导体裸片和封装激光直接结构件被放置在激光直接结构化衬底的相对侧处；以及一组电接触构造，在封装激光直接结构件的与激光直接结构化衬底相对的表面处，其中：在激光直接结构化衬底的第一表面处的第一引线框架结构和在激光直接结构化衬底的第二表面处的第二引线框架结构包括经激光束处理的激光直接结构件，并且激光直接结构化衬底和封装激光直接结构件包括形成至少一个导电过孔的经激光束处理的激光直接结构件，至少一个导电过孔提供导电构造的至少一部分，导电构造在至少一个第一半导体裸片与一组电接触构造中的电接触构造之间，一组电接触构造在封装激光直接结构件的与激光直接结构化衬底相对的表面处。
在一个实施例中，在封装激光直接结构件的与激光直接结构化衬底相对的表面处的一组电接触构造包括经激光束处理的激光直接结构件。
在一个实施例中，第一引线框架结构和第二引线框架结构中的每个引线框架结构包括经激光束处理的激光直接结构件，经激光束处理的激光直接结构件提供裸片焊盘和导电引线的阵列，裸片焊盘被配置用于在其上布置至少一个半导体裸片。
在一个实施例中，半导体设备包括：包括经激光束处理的激光直接结构件的至少一个导电过孔，至少一个导电过孔延伸穿过激光直接结构化衬底，并且将第一引线框架结构中的导电引线的阵列中的导电引线与第二引线框架结构中的导电引线的阵列中的导电引线电耦合。
在一个实施例中，半导体设备包括：包括经激光束处理的激光直接结构件的至少一个导电过孔，至少一个导电过孔延伸穿过封装激光直接结构件，并且将第二引线框架结构中的导电引线的阵列中的导电引线与一组电接触构造中的电接触构造电耦合，一组电接触构造在封装激光直接结构件的与激光直接结构化衬底相对的表面处；以及包括经激光束处理的激光直接结构件的至少一个导电过孔，至少一个导电过孔延伸穿过激光直接结构化衬底和封装激光直接结构件，将第一引线框架结构中的导电引线的阵列中的导电引线与一组电接触构造中的电接触构造电耦合，一组电接触构造在封装激光直接结构件的与激光直接结构化衬底相对的表面处。
在一个实施例中，半导体设备包括：包括经激光束处理的激光直接结构件的至少一个导电过孔，至少一个导电过孔延伸穿过封装激光直接结构件，并且将在激光直接结构化衬底的第二表面处的第二引线框架结构处的至少一个第二半导体裸片与一组电接触构造中的电接触构造电耦合，一组电接触构造在封装激光直接结构件的与激光直接结构化衬底相对的表面处。
在一个实施例中，半导体设备包括另外的封装激光直接结构件，另外的封装激光直接结构件被模制到激光直接结构化衬底的第一表面上，第一表面具有被布置在第一引线框架结构处的至少一个第一半导体裸片，其中包括经激光束处理的激光直接结构件的至少一个导电构造被提供在另外的封装激光直接结构件、激光直接结构化衬底、和封装激光直接结构件中，至少一个导电构造将被布置在第一引线框架结构处的至少一个第一半导体裸片与以下一项电耦合：在封装激光直接结构件的与激光直接结构化衬底相对的表面处的一组电接触构造中的电接触构造，或被嵌入在封装激光直接结构件中的无源组件，无源组件优选地与被布置在第二引线框架结构处的至少一个第二半导体裸片电耦合。
在一个实施例中，半导体设备包括导电键合图案，导电键合图案在以下两项之间：被布置在第一引线框架结构和第二引线框架结构中的一个引线框架结构的裸片焊盘处的至少一个半导体裸片，与在第一引线框架结构和第二引线框架结构中的一个引线框架结构中的引线框架结构的导电引线的阵列中的导电引线。
在一个实施例中，半导体设备包括在经激光束处理的激光直接结构件处的金属件。
根据本公开的半导体设备具有较高的设计灵活性。
附图说明
现在将参考附图，仅通过示例的方式描述一个或多个实施例，其中：
图1和图2是可以向其应用实施例的半导体产品的截面图，并且
图3A至图3K是根据一个或多个实施例的在制造半导体设备中的可能动作的示例。
将理解，为了简单和易于解释，各种附图可能未按相同比例绘制，这可以适用于相同附图的不同部分。
具体实施方式
本公开的一个或多个实施例有助于克服前述的缺点。根据一个或多个实施例，有助于克服之前讨论的缺点的技术特征可以通过具有以下描述中阐述的特征的方法来实现。
一个或多个实施例可以涉及一种对应的半导体设备。
权利要求是本文提供的实施例的公开内容的组成部分。
一个或多个实施例可以有助于使用激光直接结构化(LDS)技术将两个或更多个裸片(或芯片)封装在诸如QFN型封装的封装中。QFN是四方扁平无引脚的首字母缩写。
一个或多个实施例可以有助于将LDS技术应用于制造半导体设备。
一个或多个实施例可以有助于避免使用常规的引线框架或复杂的球栅阵列(BGA)衬底。
一个或多个实施例可以依赖于背对背配置，该背对背配置减少了LDS模制/写入/金属化步骤的数目。
一个或多个实施例可以有助于在重新使用现有设计来组装新的SiP产品时实现增加的灵活性。
一个或多个实施例可以有助于实现更高的设计灵活性。
在一个或多个实施例中，例如，经由模制彼此堆叠的化合物层，可以相对于标准SiP减小板上空间约束。
一个或多个实施例可以依赖于通过LDS过程直接创建的引线框架。
例如，由于省去了引线框架交付的等待时间，一个或多个实施例可以导致生产成本和时间的减少。
一个或多个实施例可以有助于实现高设计灵活性。
一个或多个实施例可以提供标准SiP的备选。
在随后的描述中，说明了各种具体细节，以便提供对根据描述的实施例的各种示例的深入理解。可以在没有一个或多个特定细节的情况下，或者在其他方法、组件、材料等的情况下获得实施例。在其他情况下，没有详细示出或描述已知的结构、材料或操作，以使实施例的各个方面将不被遮盖。
在本描述的框架中对“实施例”或“一个实施例”的引用旨在指示关于该实施例描述的特定配置、结构或特性被包括在至少一个实施例中。因此，可以在本描述的各个方面中出现的诸如“在实施例中”、“在一个实施例中”的短语不一定精确地指代相同实施例。此外，在一个或多个实施例中，可以以任何适当的方式组合特定的构造、结构或特性。本文中使用的附图标记仅出于方便起见而被提供，并且因此不定义保护的程度或实施例的范围。
图1是诸如集成电路(IC)的半导体设备10的截面图。
如本文例示的，设备10可以包括(至少一个)半导体芯片或裸片12’、12”的对，其经由裸片附接材料14’、14”而被布置在例如相应的裸片焊盘16a’、16a”上，裸片焊盘16a’、16a”由引线框架中的导电引线16b’、16b”的阵列围绕。
当前，使用名称“引线框架(leadframe)”(或“引线框架(lead frame)”)(例如，参见美国专利商标局USPC术语的合并词汇表)来指示为集成电路芯片或裸片以及电引线提供支持的金属框架，电引线将裸片或芯片中的集成电路互连到其他电子组件或接触。
本质上，引线框架包括导电构造(引线)的阵列，导电构造(引线)从轮廓位置在半导体芯片或裸片的方向上向内延伸，从而从裸片焊盘形成导电构造的阵列，裸片焊盘被配置成具有附接在其上的至少一个半导体芯片或裸片。这可以经由诸如裸片附接粘合剂(例如，裸片附接膜或DAF)的常规手段进行。
如图1中例示的，两个半导体芯片或裸片12’、12”以一种背对背布置的方式被附接在相应的裸片焊盘16a’、16a”上，裸片焊盘16a’、16a”形成在双面引线框架的相对表面处，使用LDS技术，在LDS材料的层16中制造该双面引线框架。
为了简化和易于理解，在整个说明书中将以两个半导体芯片或裸片12’、12”为例。另外，将认识到，本文例示的概念可以被扩展到SiP布置中的实际上任何数目的芯片或裸片。
激光直接结构化(LDS)是一种基于激光的加工技术，目前被广泛用于工业和消费电子市场的各个领域，例如用于高性能天线集成，其中天线设计可以被直接形成在模制塑料部件上。在示例性过程中，可以利用可商购的树脂来制造模制部件，该树脂包括适于LDS过程的添加剂；对于该目的，广泛范围的树脂目前可用，诸如，如PC、PC/ABS、ABS、LCP的聚合物树脂。
在LDS中，可以使用激光束将所需的导电图案转移到塑料模制件上，然后对塑料模制件进行金属化(例如，经由利用铜或其他金属进行无电镀)来最终完成所需的导电图案。
如图1中例示的，被应用于LDS材料的层16的相对表面的激光束处理(在如今的LDS技术中可能跟随有金属化)有利于在这些相对表面上形成裸片焊盘16a’、16a”(可选地，在中心位置)和引线16b’、16b”(可选地，在层16的外围位置)。
如图1中例示的，可以经由诸如(例如，Au/Cu/Al)接线键合图案(bondingpattern)的导电构造18’、18”，来提供半导体裸片12’、12”到引线16b’、16b”的电耦合，导电构造18’、18”根据所需的信号路由图案，将在半导体裸片12’、12”的前表面处的裸片焊盘与引线框架中的引线16b’、16b”耦合。夹子或带同样可以用于导电构造18’、18”。
诸如US2019/115287A1或意大利专利申请102019000014829和102019000014832的文件(后两个文件在本申请提交之日尚未向公众开放)是LDS技术的可能应用的示例，该技术涉及激光钻孔和结构化模制化合物以在其中提供导电构造。实际上，LDS技术使得可以利用通过对LDS材料的激光束处理(可能跟随有金属化(例如，通过镀覆工艺来生长金属厚铜))而产生的线路/过孔来代替导线、夹子或带，而无需使用全金属引线框架。
注意，这种方法可以应用于系统级封装(SiP)过程，以便有助于在引线框架和互连的布局设计中实现灵活性。
一个或多个实施例可以通过放宽对引线框架和互连设计的约束来有助于创建(更多)灵活的SiP布局。
在本文例示的一个或多个实施例中，应用于系统级封装(SiP)工艺的LDS技术可以利用以下可能性：(电)耦合两个或更多个裸片(诸如12’和12”)，而不管它们的尺寸和/或它们在不同平面上的可能布置，这有助于减小整体封装尺寸，如果需要的话，无源组件可以被嵌入在封装中。
该方法的第一示例在图1中由一个或多个过孔20提供，过孔20可以被形成(经由本领域技术人员已知的LDS处理，包括可能跟随有金属化的激光束处理)延伸穿过LDS材料层16。
例如，这些过孔20可以被配置成：
(电)耦合引线框架的相对表面上的引线16b’和16b”，这些引线继而分别耦合到裸片12’和12”：例如，参见图1的左侧，使在引线框架的一个表面(这里，上表面)上形成的诸如16b’的引线变得在相对侧(这里，下表面)可访问：例如，参见图1的右侧。
在一个或多个实施例中，将LDS技术应用于封装半导体设备可因此促进创建从一个或多个裸片通过过孔和线路到引线框架引线或衬底端子的互连。
如图1中例示的(并且另外如本领域中常规的)，一块封装模制化合物22(例如，环氧模制化合物或EMC)可以被模制到半导体裸片12’和接线键合图案18’上，以提供(电绝缘)保护性封装。
如图1中例示的，另一块封装模制化合物24可以被模制到半导体裸片12”和接线键合图案18”上，以提供类似的保护性封装。
在一个或多个实施例中，封装模制化合物24可以包括LDS材料，可以向该LDS材料应用本领域技术人员已知的LDS处理(包括可能跟随有金属化的激光束处理)，以在LDS化合物中形成延伸穿过LDS化合物24的一个或多个过孔。
例如，这些过孔26可以配置成：
经由焊盘或连接盘26a，使形成在裸片12”的前表面(这里，面向下)上的裸片焊盘变得在设备10的封装的表面(这里，化合物24的下表面)处可访问：例如，参见图1，下部中心。
经由焊盘或连接盘26a，使形成在引线框架层16的任一表面上的诸如16b’和/或16b”的引线变得在设备10的封装的表面(这里，在化合物24的下表面)处可访问：例如，参见图1的右手侧。
在后一种情况下，如本文所例示的：
可以通过延伸穿过化合物24的过孔26，来提供在设备10的封装的表面处的引线框架(LDS材料层16)的下表面处形成的诸如16b”的引线的可访问性。
可以通过延伸穿过LDS材料层16的过孔20和延伸穿过LDS化合物24的过孔26，来提供在设备10的封装的表面处的引线框架(LDS材料层16)的上表面处形成的诸如16b’的引线的可访问性。
图1还例示了(左侧，下部)向LDS化合物24应用LDS处理(激光束处理，可能跟随有金属化)以形成引线框架引线或连接盘(为简化起见，仍被指示为26a)，以用于将设备10安装到衬底(例如，印刷电路板或PCB)上的可能性。
图2是在如本文例示的SiP上下文中进一步扩展LDS技术的用途的可能性的示例。
在图2中，与已经结合图1描述的部件或元件相似的部件或元件由相同的附图标记表示。为了简洁，这里将不再重复对这些部件或元件的对应详细描述。
另外，将理解，结合图2中例示的半导体设备10而在本文例示的一个或多个特征可以单独地或组合地被包括在图1中例示的半导体设备10中；同样，结合图1中例示的半导体设备10而在本文例示的一个或多个特征可以单独地或组合地被包括在图2中例示的半导体设备10中。
简而言之，在图1中例示的实施例中，LDS材料用于引线框架层16并且用于设备封装的下部24：常规的封装模制化合物(例如EMC)用于设备封装的上部22。
相反地，在图2中例示的实施例中，LDS材料用于整个设备封装，封装包括：
LDS封装模制材料的第一块220，用于被模制到裸片或芯片12’上的设备封装的上部，裸片或芯片12’在16a’处被布置到引线框架的上表面上，
LDS封装模制材料的第二块(可能包括两个部分241、242)，用于被模制到裸片或芯片12”上的设备封装的下部，裸片或芯片12”在16a”处被模制到引线框架的下表面上。
在一个或多个实施例中(如图1和图2两者中所例示的)，用于(引线框架)层16和在24、220、241、242处用于封装模制的LDS材料可以包括广泛范围的LDS材料中的任何一种，例如，诸如聚合物树脂(如目前市场上可用的PC、PC/BS、BS、LCP)的树脂。可选地，在用于16、24、20、241、242时，可以根据所预期的应用，可以考虑相同类型的LDS材料或不同类型的LDS材料。
在图2中例示的实施例中，对(引线框架)层16的LDS材料的LDS处理可以提供一种引线框架结构，该结构包括(仅)裸片焊盘16a’和16a”，裸片12’和12”可以被布置(例如，在14’、14”处附接)在裸片焊盘16a’和16a”上。
在其上模制之后(在200、241处并且可能在242处，以单个步骤或多个步骤)，可以提供LDS化合物材料导电构造(以甚至非常复杂的导电构造的布线的形式)，诸如线路(迹线)和/或过孔(统称为260)。
在一个或多个实施例中，诸如260的构造可以至少部分地代替诸如18’(和18”)的键合构造。
再次，对LDS材料的激光处理可以涉及经由激光束进行的LDS化合物激活，以及可能的金属化(诸如镀覆)以增加电导率，如本领域中常规的那样。
例如，线路/过孔260可以被配置成使形成在裸片12’的前表面(这里，面向上)上的裸片焊盘变得在设备10的封装的表面(这里，在化合物241、242的下表面)处可访问。
如图2中例示的，线路/过孔260可以包括：
第一过孔，从形成在裸片12’的前表面(这里，面向上)上的裸片焊盘延伸到LDS化合物220的上表面，
“水平”线路，在LDS化合物220的上表面朝向其外围延伸，第二过孔，沿着设备的封装的侧面，延伸穿过LDS化合物220和LDS引线框架层16。
图2例示了构造260延伸的可能性：
延伸穿过LDS化合物241、242到在化合物241、242的下表面(即在设备10的封装的表面)处的引线或连接盘26a：参见图2的右侧；和/或
延伸穿过LDS化合物241的部分241到组件28(例如，诸如电阻器的无源组件)，组件28经由线路/过孔耦合到裸片12”，这种组件28被LDS化合物241的部分242封装并且因此被保护。
与图1相似，图2还例示了以下可能性：
提供(通过在241和242处对LDS化合物的LDS处理)过孔，该过孔被配置成：致使形成在裸片12”的前表面(这里，面向下)上的裸片焊盘经由焊盘或连接盘26a，在设备10的封装的表面(这里，在化合物241、242的下表面)处可访问：例如参见图2，下部中心；
在241、242处向LDS化合物应用LDS处理，以形成引线框架引线或连接盘(为简单起见，仍被指示为26a)，以用于将设备10安装在衬底(例如，印刷电路板或PCB)上。
图3A至图3K是在制造如图1中例示的半导体设备10中的可能动作的示例。
另外，本领域技术人员将理解，这些动作中的大多数动作可以应用于制造如图2中例示的半导体设备10；换句话说，尽管结合制造如图1中例示的半导体设备10来例示，但是图3A至图3K中例示的动作可以被应用于制造如图2中例示的半导体设备10。
同样地，结合如图2中例示的半导体设备10例示的一个或多个特征可以单独地或组合地被包括在如图1中例示的半导体设备10中。
仅以简单的非限制性示例的方式，在一个或多个实施例中，(例如，在18’被嵌入在诸如EMC的常规封装材料中的情况下)如图1中以18’和18”例示的接线键合图案中的一个或两个，可以由形成在LDS封装材料中的导电构造来代替，该导电构造通过向LDS材料进行激光束处理(可能跟随有金属化(例如镀铜))来形成。
同样，本领域技术人员将理解，尽管为了简化在这里例示了制造单个设备10，但是一个或多个实施例可以涉及同时制造多个设备10，多个设备10旨在经由“切单颗(singulation)”动作被最终分离，如本领域中常规的那样。
图3A至图3K通过示例的方式涉及以下动作(所例示的顺序不是强制性的，因为至少某些动作可以以不同的顺序被执行)：
图3A：提供LDS材料的引线框架层16；
图3B：对LDS材料的引线框架层16的LDS处理(例如，激光结构化和诸如水电镀的金属化)，以在层16的相对表面处形成裸片焊盘16a’、16a”和引线16b’、16b”，以及穿过层16的过孔(诸如20)；
图3C：将裸片12’附接到裸片焊盘16a’(为简单起见，裸片附接材料14’不可见)；
图3D：提供接线键合18’；
图3E：模制(标准)封装材料22(例如，环氧模制化合物)；
图3F：将裸片12”附接到裸片焊盘16a”(为简单起见，裸片附接材料14”不可见)；
图3G：提供接线键合18”；
图3H：模制LDS封装材料24；
图3I：对LDS材料24的LDS处理(例如，激光结构化和诸如水电镀的金属化)，以形成过孔26和焊盘(连接盘)26a；
图3J：焊盘26a的镀覆(例如，锡镀覆)，如在26b所例示的；
图3K：将设备10安装在衬底B(例如，印刷电路板或PCB)上。
本文例示的方法可以包括：
提供激光直接结构化材料(简称LDS材料)的衬底(例如16)，该衬底具有第一表面和第二表面，第二表面与第一表面相对，
在LDS材料的衬底的第一表面处的第一引线框架结构(例如，在如16a’的裸片焊盘)处布置(例如，如在14’、14”处例示的那样附接)至少一个第一半导体裸片(例如，12)，并且在LDS材料的衬底(16)的第二表面处的第二引线框架结构(例如，在如16”的裸片焊盘)处布置至少一个第二半导体裸片(例如12”)，
将封装LDS材料(例如，24或241、242)模制到LDS材料的衬底的第二表面上，第二表面具有被布置在所述第二引线框架结构处的至少一个第二半导体裸片，其中至少一个第一半导体裸片和封装LDS材料位于LDS材料的衬底的相对侧上(例如，参见图1和图2，其中第一半导体裸片12’在引线框架层16上方，而LDS模制化合物24或241、242在引线框架层16之下)，
在封装LDS材料中，在封装模制材料的与LDS材料的衬底相对的表面处提供一组电接触构造(例如26a)(例如，参见图1和图2，其中引线或连接盘26a在LDS模制化合物24或241、242的下表面处，与面向LDS模制化合物的上表面的引线框架层16相对)，
向LDS材料的衬底应用激光束处理，以在LDS材料的衬底的第一表面处形成第一引线框结构(例如，图1中的16a’、16b’或图2中的16a’)，并且在LDS材料的衬底的第二表面处形成第二引线框结构(例如，图1中的16a”、16b”或图2中的16a”)，向LDS材料的衬底和封装LDS材料(24；241，242)应用激光束处理，以在其中形成至少一个导电过孔(例如，参见图1中的过孔20或在图2中的延伸穿过引线框架层16的构造260的中间部分)，该导电过孔提供导电构造的至少一部分，该导电构造在所述至少一个第一半导体裸片(例如，12’)与所述一组电接触构造中的电接触构造(26a)之间，所述一组电接触构造(例如，26a)在封装模制材料的与LDS材料的衬底相对的表面处。
本文例示的方法可以包括：向封装LDS材料(例如，24；241，242)应用激光束处理，以在封装模制材料的与LDS材料的衬底相对的表面处在其中形成所述一组电接触构造(例如26a)。
如本文例示的方法可以包括：向LDS材料的衬底应用激光束处理，以在其中形成第一引线框架结构和第二引线框架结构(例如，参见图1中的16a’、16b’和16a”、16b”)，第一引线框架结构和第二引线框架结构包括裸片焊盘(例如，图1中的16a’、16a”)和导电引线的阵列(例如，参见图1中的16b’，16b”)，裸片焊盘被配置用于在其上布置至少一个半导体裸片(12’，12”)。
本文例示的方法可以包括：向LDS材料的衬底应用激光束处理，以在其中形成穿过LDS材料的衬底的至少一个导电过孔(例如，参见图1中最左边的过孔20)，其中穿过LDS材料的衬底的至少一个导电过孔将所述第一引线框架结构中的导电引线的阵列中的导电引线(例如，16b’)与所述第二引线框架结构中的导电引线的阵列中的导电引线(例如，16b”)电耦合。
本文例示的方法可以包括：向封装LDS材料(例如24)应用激光束处理，以在其中形成穿过封装LDS材料的至少一个导电过孔(例如，参见图1中右侧的第二过孔26)，其中穿过封装LDS材料的至少一个导电过孔将所述第二引线框架结构中的导电引线的阵列中的导电引线与一组电接触构造中的电接触构造电耦合，该组电接触构造在封装模制材料的与LDS材料的衬底相对的表面处，和/或
向LDS材料的衬底和封装LDS材料应用激光束处理，以在其中形成穿过LDS材料的衬底和封装LDS材料的至少一个导电过孔(例如，参见图1中最右侧的过孔26)，其中穿过LDS材料的衬底和封装LDS材料的至少一个导电过孔将所述第一引线框架结构中的导电引线的阵列中的导电引线与一组电接触构造中的电接触构造电耦合，该组电接触构造在封装模制材料的与LDS材料的衬底相对的表面处。
本文例示的方法可以包括：提供导电键合图案(例如，图1中的18’、18”)，导电键合图案在被布置在所述第一引线框架结构和所述第二引线框架结构中的一个的裸片焊盘处的至少一个半导体裸片，与在第一引线框架结构和第二引线框架结构中的所述一个中的引线框架结构的导电引线的阵列中的导电引线(例如16b’，16b”)之间。
本文例示的方法可以包括：向封装LDS材料应用激光束处理，以在其中形成穿过封装LDS材料的至少一个导电过孔(例如，参见图1和图2两者的下部中心处的过孔26)，其中穿过封装LDS材料的至少一个导电过孔将在LDS材料的衬底的第二表面处的第二引线框架结构处的所述至少一个第二半导体裸片，与在封装模制材料的与LDS材料的衬底相对的表面处的一组电接触构造中的电接触构造电耦合。
本文例示的方法可以包括：
将另外的封装LDS材料(例如，图2中的220)模制到LDS材料的衬底的第一表面上，第一表面具有被布置在所述第一引线框架结构处的至少一个第一半导体裸片；
向所述另外的封装LDS材料、LDS材料的衬底和封装LDS材料应用激光束处理，以在其中形成至少一个导电构造(例如，图2中的线路/过孔260)，至少一个导电构造将被布置在所述第一引线框架结构处的所述至少一个第一半导体裸片与以下一项电耦合：
在封装模制材料的与LDS材料的衬底16相对的表面处的一组电接触构造中的电接触构造(例如，参见在图2的右侧上的构造260)，
被嵌入在封装LDS材料中的无源组件(例如28)，无源组件可选地与被布置在所述第二引线框架结构处的至少一个第二半导体裸片电耦合(例如，参见图2的左侧上的构造260)。
本文例示的方法可以包括：向LDS材料的激光束处理和金属化向其应用激光束处理的LDS材料。
本文讨论的设备(例如10)可以包括图1和图2中例示的特征，前提是图1中例示的设备10的一个或多个特征可以单独或组合地被转移到如图2中例示的设备10，而图2中例示的设备10的一个或多个特征可以单独或组合地被转移到图1中例示的设备10。
这些特征可以包括：
激光直接结构化(简称为LDS)材料的衬底，衬底具有第一表面和第二表面，第二表面与第一表面相对，
至少一个第一半导体裸片，被布置在LDS材料的衬底的第一表面处的第一引线框架结构处，以及至少一个第二半导体裸片，被布置在LDS材料的衬底的第二表面处的第二引线框架结构处，
封装LDS材料，被模制到LDS材料的衬底的第二表面上，第二表面具有被布置在所述第二引线框架结构处的至少一个第二半导体裸片，其中至少一个第一半导体裸片和封装LDS材料位于LDS材料的衬底的相对侧处，
一组电接触构造，在封装模制材料的与LDS材料的衬底相对的表面处，
其中：
在LDS材料的衬底的第一表面处的第一引线框架结构和在LDS材料的衬底的第二表面处的第二引线框架结构包括经激光束处理的LDS材料，
LDS材料的衬底和封装LDS材料包括形成至少一个导电过孔的经激光束处理的LDS材料，至少一个导电过孔提供导电构造的至少一部分，导电构造在所述至少一个第一半导体裸片与所述一组电接触构造中的电接触构造之间，该组电接触构造在封装模制材料的与LDS材料的衬底相对的表面处。
本文例示的设备可以包括以下特征中的一个或多个特征：
在封装模制材料的与LDS材料的衬底相对的表面处的所述一组电接触构造包括经激光束处理的LDS材料，和/或
所述第一引线框架结构和第二引线框架结构包括经激光束处理的LDS材料，其提供裸片焊盘和导电引线的阵列，裸片焊盘被配置用于在其上布置至少一个半导体裸片，和/或
包括经激光束处理的LDS材料的至少一个导电过孔被提供穿过LDS材料的衬底，将所述第一引线框架结构中的导电引线的阵列中的导电引线与所述第二引线框架结构中的导电引线的阵列中的导电引线电耦合，和/或
包括经激光束处理的LDS材料的至少一个导电过孔被提供穿过封装LDS材料，将所述第二引线框架结构中的导电引线的阵列中的导电引线与一组电接触构造中的电接触构造电耦合，该组电接触构造在封装模制材料(24)的与LDS材料的衬底(16)相对的表面处；和/或
包括经激光束处理的LDS材料的至少一个导电过孔被提供穿过LDS材料的衬底和封装LDS材料，将在所述第一引线框架结构中的导电引线的阵列中的导电引线与一组电接触构造中的电接触构造电耦合，该组电接触构造在封装模制材料的与LDS材料的衬底相对的表面处，和/或
包括经激光束处理的LDS材料的至少一个导电过孔被提供穿过封装LDS材料，将在LDS材料的衬底的第二表面处的第二引线框架结构处的所述至少一个第二半导体裸片与一组电接触构造中的电接触构造电耦合，该组电接触构造在封装模制材料的与LDS材料的衬底相对的表面处，和/或
提供另外的封装LDS材料，其被模制到LDS材料的衬底的第一表面上，第一表面具有被布置在所述第一引线框架结构处的至少一个第一半导体裸片，其中包括经激光束处理的LDS材料的至少一个导电构造被提供在另外的封装LDS材料、LDS材料的衬底和封装LDS材料(24)中，将被布置在所述第一引线框架结构处的所述至少一个第一半导体裸片与以下一项电耦合：
在封装模制材料的与LDS材料的衬底(16)相对的表面处的一组电接触构造中的电接触构造，
被嵌入在封装LDS材料中的无源组件，无源组件可选地与被布置在所述第二引线框架结构处的至少一个第二半导体裸片电耦合。
在本文例示的设备中，可以提供导电键合图案(例如，18’、18”)，导电键合图案在被布置在所述第一引线框架结构和所述第二引线框架结构中的一个引线框架结构的裸片焊盘处的至少一个半导体裸片，与在所述第一引线框架结构和所述第二引线框架结构中的所述一个引线框架结构中的引线框架结构的导电引线的阵列中的导电引线之间。
本文例示的设备可以包括在所述经激光束处理的LDS材料处的金属化材料(例如，铜)。
在不损害基本原理的情况下，细节和实施例可以相对于仅通过示例描述的内容变化，甚至显著变化，而不背离实施例的范围。
上述各种实施例可以被组合以提供另外的实施例。可以根据以上具体实施方式对实施例进行这些和其他改变。通常，在以下权利要求中，所使用的术语不应当被解释为将权利要求限制为说明书和权利要求中公开的特定实施例，而是应当被解释为包括所有可能的实施例以及赋予这些权利要求的等同物的全部范围。因此，权利要求不受公开内容的限制。

Claims (9)

1.一种半导体设备，其特征在于，包括：
激光直接结构化衬底，所述衬底具有第一表面和第二表面，所述第二表面与所述第一表面相对；
至少一个第一半导体裸片和至少一个第二半导体裸片，所述至少一个第一半导体裸片被布置在所述激光直接结构化衬底的所述第一表面处的第一引线框架结构处，所述至少一个第二半导体裸片被布置在所述激光直接结构化衬底的所述第二表面处的第二引线框架结构处；
封装激光直接结构件，被模制到所述激光直接结构化衬底的所述第二表面上，所述第二表面具有被布置在所述第二引线框架结构处的所述至少一个第二半导体裸片，其中所述至少一个第一半导体裸片和所述封装激光直接结构件被放置在所述激光直接结构化衬底的相对侧处；以及
一组电接触构造，在所述封装激光直接结构件的与所述激光直接结构化衬底相对的表面处，
其中：
在所述激光直接结构化衬底的所述第一表面处的所述第一引线框架结构和在所述激光直接结构化衬底的所述第二表面处的所述第二引线框架结构包括经激光束处理的激光直接结构件，并且
所述激光直接结构化衬底和所述封装激光直接结构件包括形成至少一个导电过孔的经激光束处理的激光直接结构件，所述至少一个导电过孔提供导电构造的至少一部分，所述导电构造在所述至少一个第一半导体裸片与所述一组电接触构造中的电接触构造之间，所述一组电接触构造在所述封装激光直接结构件的与所述激光直接结构化衬底相对的所述表面处。
2.根据权利要求1所述的设备，其特征在于，在所述封装激光直接结构件的与所述激光直接结构化衬底相对的所述表面处的所述一组电接触构造包括经激光束处理的激光直接结构件。
3.根据权利要求1所述的设备，其特征在于，所述第一引线框架结构和所述第二引线框架结构中的每个引线框架结构包括经激光束处理的激光直接结构件，所述经激光束处理的激光直接结构件提供裸片焊盘和导电引线的阵列，所述裸片焊盘被配置用于在其上布置至少一个半导体裸片。
4.根据权利要求3所述的设备，其特征在于，包括：包括经激光束处理的激光直接结构件的至少一个导电过孔，所述至少一个导电过孔延伸穿过所述激光直接结构化衬底，并且将所述第一引线框架结构中的所述导电引线的阵列中的导电引线与所述第二引线框架结构中的所述导电引线的阵列中的导电引线电耦合。
5.根据权利要求3所述的设备，其特征在于，包括：包括经激光束处理的激光直接结构件的至少一个导电过孔，所述至少一个导电过孔延伸穿过所述封装激光直接结构件，并且将所述第二引线框架结构中的所述导电引线的阵列中的导电引线与所述一组电接触构造中的电接触构造电耦合，所述一组电接触构造在所述封装激光直接结构件的与所述激光直接结构化衬底相对的表面处；以及
包括经激光束处理的激光直接结构件的至少一个导电过孔，所述至少一个导电过孔延伸穿过所述激光直接结构化衬底和所述封装激光直接结构件，将所述第一引线框架结构中的所述导电引线的阵列中的导电引线与所述一组电接触构造中的电接触构造电耦合，所述一组电接触构造在所述封装激光直接结构件的与所述激光直接结构化衬底相对的表面处。
6.根据权利要求3所述的设备，其特征在于，包括：包括经激光束处理的激光直接结构件的至少一个导电过孔，所述至少一个导电过孔延伸穿过所述封装激光直接结构件，并且将在所述激光直接结构化衬底的所述第二表面处的所述第二引线框架结构处的所述至少一个第二半导体裸片与所述一组电接触构造中的电接触构造电耦合，所述一组电接触构造在所述封装激光直接结构件的与所述激光直接结构化衬底相对的所述表面处。
7.根据权利要求3所述的设备，其特征在于，包括另外的封装激光直接结构件，所述另外的封装激光直接结构件被模制到所述激光直接结构化衬底的所述第一表面上，所述第一表面具有被布置在所述第一引线框架结构处的所述至少一个第一半导体裸片，其中包括经激光束处理的激光直接结构件的至少一个导电构造被提供在所述另外的封装激光直接结构件、所述激光直接结构化衬底、和所述封装激光直接结构件中，所述至少一个导电构造将被布置在所述第一引线框架结构处的所述至少一个第一半导体裸片与以下一项电耦合：
在所述封装激光直接结构件的与所述激光直接结构化衬底相对的表面处的所述一组电接触构造中的电接触构造，或
被嵌入在所述封装激光直接结构件中的无源组件，所述无源组件与被布置在所述第二引线框架结构处的所述至少一个第二半导体裸片电耦合。
8.根据权利要求1所述的设备，其特征在于，包括导电键合图案，所述导电键合图案在以下两项之间：被布置在所述第一引线框架结构和所述第二引线框架结构中的一个引线框架结构的裸片焊盘处的至少一个半导体裸片，与在所述第一引线框架结构和所述第二引线框架结构中的所述一个引线框架结构中的所述引线框架结构的导电引线的阵列中的导电引线。
9.根据权利要求1所述的设备，其特征在于，包括在所述经激光束处理的激光直接结构件处的金属件。
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US11721614B2 (en) 2023-08-08

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