IT202200011561A1 - Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente - Google Patents

Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente Download PDF

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Publication number
IT202200011561A1
IT202200011561A1 IT102022000011561A IT202200011561A IT202200011561A1 IT 202200011561 A1 IT202200011561 A1 IT 202200011561A1 IT 102022000011561 A IT102022000011561 A IT 102022000011561A IT 202200011561 A IT202200011561 A IT 202200011561A IT 202200011561 A1 IT202200011561 A1 IT 202200011561A1
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IT
Italy
Prior art keywords
semiconductor device
semiconductor devices
manufacturing
manufacturing semiconductor
devices
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Application number
IT102022000011561A
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English (en)
Inventor
Michele Derai
Guendalina Catalano
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St Microelectronics Srl
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Priority to IT102022000011561A priority Critical patent/IT202200011561A1/it
Priority to US18/324,897 priority patent/US20230386980A1/en
Publication of IT202200011561A1 publication Critical patent/IT202200011561A1/it

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/82009—Pre-treatment of the connector or the bonding area
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
IT102022000011561A 2022-05-31 2022-05-31 Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente IT202200011561A1 (it)

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Application Number Priority Date Filing Date Title
IT102022000011561A IT202200011561A1 (it) 2022-05-31 2022-05-31 Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente
US18/324,897 US20230386980A1 (en) 2022-05-31 2023-05-26 Method of manufacturing semiconductor devices and corresponding semiconductor device

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IT102022000011561A IT202200011561A1 (it) 2022-05-31 2022-05-31 Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente

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Citations (10)

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Publication number Priority date Publication date Assignee Title
US20180342453A1 (en) 2017-05-23 2018-11-29 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding product
US20190115287A1 (en) 2017-10-12 2019-04-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, corresponding device and circuit
US20200203264A1 (en) 2018-12-24 2020-06-25 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20200321274A1 (en) 2019-04-05 2020-10-08 Stmicroelectronics S.R.L. Method of manufacturing leadframes for semiconductor devices, corresponding leadframe and semicondctor device
US20210050226A1 (en) 2019-08-16 2021-02-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20210050299A1 (en) 2019-08-16 2021-02-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20210091030A1 (en) * 2019-09-25 2021-03-25 Intel Corporation Electroless-catalyst doped-mold materials for integrated-circuit die packaging architectures
US20210183748A1 (en) 2019-12-17 2021-06-17 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20210305203A1 (en) 2019-01-22 2021-09-30 Stmicroelectronics S.R.L. Semiconductor device and corresponding method of manufacture
US20220068741A1 (en) * 2020-08-27 2022-03-03 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180342453A1 (en) 2017-05-23 2018-11-29 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding product
US20190115287A1 (en) 2017-10-12 2019-04-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, corresponding device and circuit
US20200203264A1 (en) 2018-12-24 2020-06-25 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20210305203A1 (en) 2019-01-22 2021-09-30 Stmicroelectronics S.R.L. Semiconductor device and corresponding method of manufacture
US20200321274A1 (en) 2019-04-05 2020-10-08 Stmicroelectronics S.R.L. Method of manufacturing leadframes for semiconductor devices, corresponding leadframe and semicondctor device
US20210050226A1 (en) 2019-08-16 2021-02-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20210050299A1 (en) 2019-08-16 2021-02-18 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20210091030A1 (en) * 2019-09-25 2021-03-25 Intel Corporation Electroless-catalyst doped-mold materials for integrated-circuit die packaging architectures
US20210183748A1 (en) 2019-12-17 2021-06-17 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
US20220068741A1 (en) * 2020-08-27 2022-03-03 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding device

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