IT201700087201A1 - Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore - Google Patents

Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore

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Publication number
IT201700087201A1
IT201700087201A1 IT102017000087201A IT201700087201A IT201700087201A1 IT 201700087201 A1 IT201700087201 A1 IT 201700087201A1 IT 102017000087201 A IT102017000087201 A IT 102017000087201A IT 201700087201 A IT201700087201 A IT 201700087201A IT 201700087201 A1 IT201700087201 A1 IT 201700087201A1
Authority
IT
Italy
Prior art keywords
semiconductor
device manufacturing
corresponding device
semiconductor devices
devices
Prior art date
Application number
IT102017000087201A
Other languages
English (en)
Inventor
Samuele Sciarrillo
Ivan Venegoni
Paolo Colpani
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102017000087201A priority Critical patent/IT201700087201A1/it
Priority to US16/048,108 priority patent/US10566283B2/en
Publication of IT201700087201A1 publication Critical patent/IT201700087201A1/it

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    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521970B1 (en) * 2000-09-01 2003-02-18 National Semiconductor Corporation Chip scale package with compliant leads
US20070290343A1 (en) * 2006-06-15 2007-12-20 Sony Corporation Electronic component, semiconductor device employing same, and method for manufacturing electronic component
US20120193793A1 (en) * 2011-02-01 2012-08-02 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
CN206293434U (zh) * 2016-02-01 2017-06-30 意法半导体股份有限公司 半导体器件

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223454A (en) 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US5550068A (en) * 1990-11-05 1996-08-27 Nippon Telegraph And Telephone Corporation Process of fabricating a circuit element for transmitting microwave signals
WO1998052224A1 (en) 1997-05-15 1998-11-19 Formfactor, Inc. Lithographically defined microelectronic contact structures
US6228759B1 (en) 2000-05-02 2001-05-08 Advanced Micro Devices, Inc. Method of forming an alloy precipitate to surround interconnect to minimize electromigration
US6528412B1 (en) 2001-04-30 2003-03-04 Advanced Micro Devices, Inc. Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening
JP3794403B2 (ja) 2003-10-09 2006-07-05 セイコーエプソン株式会社 半導体装置
US7427557B2 (en) 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
US8148822B2 (en) 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same
US8264072B2 (en) 2007-10-22 2012-09-11 Infineon Technologies Ag Electronic device
US8283209B2 (en) 2008-06-10 2012-10-09 Stats Chippac, Ltd. Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps
TW201019440A (en) 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
JP5335931B2 (ja) 2008-12-26 2013-11-06 メギカ・コーポレイション 電力管理集積回路を有するチップ・パッケージおよび関連技術
US8946896B2 (en) 2008-12-31 2015-02-03 Stmicroelectronics, Inc. Extended liner for localized thick copper interconnect
US8389397B2 (en) 2010-09-14 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing UBM undercut in metal bump structures
US8227333B2 (en) 2010-11-17 2012-07-24 International Business Machines Corporation Ni plating of a BLM edge for Pb-free C4 undercut control
JP2012114148A (ja) 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd 半導体装置の製造方法
US8298930B2 (en) 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
JP5948924B2 (ja) 2012-02-09 2016-07-06 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、回路装置、回路装置の製造方法、電子機器
US9147628B2 (en) 2012-06-27 2015-09-29 Infineon Technoloiges Austria AG Package-in-packages and methods of formation thereof
JP2014241320A (ja) 2013-06-11 2014-12-25 ソニー株式会社 半導体装置、半導体装置の製造方法
US9786633B2 (en) 2014-04-23 2017-10-10 Massachusetts Institute Of Technology Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
US10804153B2 (en) 2014-06-16 2020-10-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method to minimize stress on stack via
US9224686B1 (en) 2014-09-10 2015-12-29 International Business Machines Corporation Single damascene interconnect structure
JP6484490B2 (ja) 2015-04-10 2019-03-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102379165B1 (ko) 2015-08-17 2022-03-25 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US10541204B2 (en) * 2015-10-20 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and method of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521970B1 (en) * 2000-09-01 2003-02-18 National Semiconductor Corporation Chip scale package with compliant leads
US20070290343A1 (en) * 2006-06-15 2007-12-20 Sony Corporation Electronic component, semiconductor device employing same, and method for manufacturing electronic component
US20120193793A1 (en) * 2011-02-01 2012-08-02 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
CN206293434U (zh) * 2016-02-01 2017-06-30 意法半导体股份有限公司 半导体器件

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