WO1998052224A1 - Lithographically defined microelectronic contact structures - Google Patents

Lithographically defined microelectronic contact structures Download PDF

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Publication number
WO1998052224A1
WO1998052224A1 PCT/US1998/009999 US9809999W WO9852224A1 WO 1998052224 A1 WO1998052224 A1 WO 1998052224A1 US 9809999 W US9809999 W US 9809999W WO 9852224 A1 WO9852224 A1 WO 9852224A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic component
contact structure
layer
region
masking
Prior art date
Application number
PCT/US1998/009999
Other languages
French (fr)
Inventor
David V. Pedersen
Igor Y. Khandros
Original Assignee
Formfactor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US1997/008634 external-priority patent/WO1997043654A1/en
Application filed by Formfactor, Inc. filed Critical Formfactor, Inc.
Priority to EP98922344A priority Critical patent/EP0985231A1/en
Priority to KR1020047003178A priority patent/KR100577131B1/en
Priority to KR1019997010532A priority patent/KR100577132B1/en
Priority to JP54959498A priority patent/JP3378259B2/en
Priority to AU74915/98A priority patent/AU7491598A/en
Publication of WO1998052224A1 publication Critical patent/WO1998052224A1/en

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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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Definitions

  • the present invention relates to resilient (spring) contact (interconnection) elements (structures) suitable for effecting pressure and/or compliant connections between electronic 5 components and, more particularly, to microminiature contact structures.
  • Exemplary materials for the core element include gold.
  • Exemplary materials for the coating include nickel and its alloys.
  • the resulting spring contact element may be used to effect pressure, or demountable, connections between two or more electronic components, particularly microelectronic components, including semiconductor devices.
  • the aforementioned PARENT CASE discloses fabricating spring contact elements by depositing at least one layer of metallic material into openings defined in multiple masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device.
  • Each spring contact element has a base end, a contact end, and a central body portion. In an embodiment disclosed therein, the contact end may be offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end.
  • a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate.
  • the spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween.
  • the spring contact elements are disposed on a semiconductor devices resident on a semiconductor wafer so that temporary connections can be made with the semiconductor devices to burn-in and/or test the semiconductor devices prior to their being singulated from the semiconductor wafer.
  • the present invention addresses and is particularly well- suited to making interconnections to modern microelectronic devices having their terminals (bond pads) disposed at a fine-pitch.
  • fine-pitch refers to microelectronic devices that have their terminals disposed at a spacing of less than 5 mils, such as 2.5 mils or 65 ⁇ m. As will be evident from the description that follows, this is preferably achieved by taking advantage of the close tolerances that readily can be realized by using lithographic rather than mechanical techniques to fabricate the contact elements.
  • a plurality of substantially identical spring contact elements can be mounted to the electronic component so that their free ends are disposed in a pattern and at positions which are spatially-translated from the pattern of the terminals on the component.
  • the spring contact elements include, but are not limited to, composite interconnection elements and plated-up structures.
  • the electronic component includes, but is not limited to, a semiconductor device, a memory chip, a portion of a semiconductor wafer, a space transformer, a probe card, a chip carrier, and a socket.
  • An object of the present invention is to provide an improved technique for fabricating spring contact elements. Another object of the invention is to provide a technique for fabricating spring contact elements using processes that are inherently well suited to the fine-pitch, close-tolerance world of microelectronics.
  • Another object of the invention is to provide a technique for fabricating microminiature spring contact elements directly on active electronic components, such as semiconductor devices, without damaging the semiconductor devices. This includes fabricating microminiature spring contact elements on semiconductor devices resident on a semiconductor wafer, prior to the semiconductor devices being singulated from the semiconductor wafer.
  • Another object of the invention is to provide a technique for fabricating spring contact 0 elements that are suitable for socketing (one form of releasably connecting to) electronic components such as semiconductor devices, such as for performing burn-in on said devices.
  • microelectronic contact structures are fabricated by applying a masking layer on a surface of an electronic component, creating openings in the masking layer, depositing conductive traces onto the masking layer and into the openings, and building 5 up masses of conductive material on the conductive traces.
  • the masses of conductive material each represent a contact structure having its base end extending up through the opening, having a main body portion extending across the masking layer (on the conductive trace), and having a tip end.
  • the sidewalls of the openings in the masking o layer may preferably be tapered (sloped). Techniques for forming tapered (sloped) openings are disclosed herein.
  • the conductive traces may be deposited onto the masking layer using a stencil (shadow mask).
  • the openings in the masking layer defining the 5 base ends of selected ones of the contact structures can be located over contact pads of the electronic component.
  • the openings in the masking layer defining base ends of selected ones of the contact structures can be located remote from the contact pads and connected to the contact pads by a patterned conductive layer underlying the masking layer.
  • protruding features may be disposed on the o masking layer so that tip ends of the contact structures are offset from main body portions of the contact structures.
  • the electronic component may include, but is not limited to, an active semiconductor device, a memory chip, a portion of a semiconductor wafer, a space transformer, a probe card, a chip carrier, and a socket.
  • the electronic component may be a passive device that supports one or more electronic connections. It is particularly preferred to add the microelectronic contact structures of this invention to an active electronic device, particularly a silicon semiconductor device.
  • the contact structures of this invention are suitable for making either temporary or permanent electrical connections to terminals of another electronic component such as a printed circuit board (PCB) interconnection substrate.
  • PCB printed circuit board
  • the component upon which the contact structures are fabricated is brought together with the other electronic component so that the tip ends of the contact structures make pressure connections with the terminals of the other electronic 0 component.
  • the contact structures react resiliently (in elastic deformation mode) to maintain contact pressure and electrical connections between the two components.
  • the component upon which the contact structures are fabricated is brought together with the other electronic component, and the tip ends of the contact structures are joined, such as by soldering or brazing or with a conductive adhesive, to 5 the terminals of the other electronic component.
  • the contact structures are compliant, and accommodate differential thermal expansion between the two electronic components.
  • the contact structures of the present invention can be fabricated directly on the surface of a semiconductor device, or on the surfaces of a plurality of semiconductor devices resident on a semiconductor wafer. In this manner, a plurality of semiconductor devices resident on a o semiconductor wafer can be "readied" for burn-in and/or test prior to being singulated from the semiconductor wafer.
  • the tapered (sloped) openings in the masking layer manifest themselves as tapered (sloped) regions in the seed layer, as well as in tapered (sloped) regions of the resulting contact structures formed on the seed layer. 5
  • the present invention is directed to the fabrication of one or more microelectronic contact structures.
  • a structure may be fabricated by applying a masking layer on a surface of an electronic component, creating an opening in the masking layer, o depositing a seed layer (preferably as a conductive trace) onto the masking layer and into the opening, and building up a mass of conductive material on the conductive trace.
  • the sidewalls of an opening can be tapered. Techniques for tapering the sidewalls of the opening are disclosed.
  • the conductive traces can be deposited through a stencil (shadow mask), thereby obviating a need for an additional masking layer.
  • a protruding feature such as in the form of a dot of insulating material, may be disposed on the masking layer so that the tip end of the resulting contact structure has a topology.
  • the mass of conductive material has a generally hemispherical lateral cross section as built up on the seed layer.
  • the opening in the masking layer, defining a base end of the contact structure, can be over a contact pad of the electronic component, or remotely located therefrom and connected to the contact pad by a conductive trace.
  • the contact structure is built up in a multilevel trough in multilevel masking layers.
  • the creation of such a multilevel trough is relatively complicated as compared with the relatively straightforward technique of the present invention that involves forming of openings (222) in a masking layer (220), preferably a single masking layer which can be patterned in a single step.
  • the technique of the present invention facilitates the formation of tapered sidewalls (e.g., of the openings 222) which provide a smooth transition from one level of the contact structure (e.g., its base portion) to another level of the contact structure (e.g., its main body portion).
  • the "third level” - namely the tip end of the contact structure is defined by the relatively straightforward instrumentality of a protruding feature (230) as opposed to another trough in another masking layer.
  • the overall shape (geometry) of the contact structure is determined by and built up upon a conductive trace (250) rather than in a trough.
  • Figure 1A is a side cross-sectional view of a technique for making a spring contact element, as disclosed in the PARENT CASE.
  • Figure IB is a side cross-sectional view of the spring contact element of Figure 1A, as o disclosed in the PARENT CASE.
  • Figure IC is a perspective view of the spring contact element of Figure IB, as disclosed in the PARENT CASE.
  • Figure 2A is a side cross-sectional view of a step in a first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2B is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2C is a top plan view of an interim product formed in the step shown in Figure 2B, according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2D is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2E is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2F is a top plan view of interim products formed in the step shown in Figure 2E, 5 according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2G is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2H is an end cross-sectional view of the product formed by the step shown in o Figure 2G, according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figures 21 and 2J are perspective views of two of many possible configurations for the contact structure of the present invention, highlighting its funnel-like base end.
  • Figure 21 illustrates a structure resulting from partially coating the sidewalls of an opening, as shown in Figures 2E and 2G generally.
  • Figure 2J shows a structure resulting from fully coating the sidewalls of an opening, as shown in Figures 4E and 4G.
  • Figure 2K is a top plan view of an interim product formed in the step shown in Figure 2G, according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figures 2L and 2M are side cross-sectional and perspective views, respectively of a completed contact structure formed on an electronic component, according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 2N is a side cross-sectional view of a contact structure of Figures 2L and 2M 0 with its tip end making contact with a contact pad of an electronic component, according to the invention.
  • Figure 2O is a side cross-sectional view of a contact structure of Figures 2L and 2M with its tip end soldered to a contact pad of an electronic component, according to the invention.
  • Figure 3 A is a side cross-sectional view of a step, comparable to the step shown in 5 Figure 2D, in a second exemplary embodiment of a portion of a process for making a contact structure, according to the invention.
  • Figure 3B is a side cross-sectional view of another step, comparable to the step shown in Figure 2E, in the second exemplary embodiment of a portion of a process for making a contact structure, according to the invention.
  • Figure 3C is a side cross-sectional view of another step, comparable to the step shown in Figure 2K, in the second exemplary embodiment of a portion of a process for making a contact structure, according to the invention.
  • Figure 3D is a side cross-sectional view of an optional enhanced structure, adding a tip and post structure to the structure of Figure 3C.
  • Figure 4A is a side cross-sectional view of a step, comparable to the step shown in
  • FIG. 2A in a third exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 4B is a side cross-sectional view of another step, comparable to the step shown in Figure 2B, in the third exemplary embodiment of a process for making a contact structure, o according to the invention.
  • Figure 4C is a top plan view of an interim product formed in the step shown in Figure 4B, according to the third exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 4D is a side cross-sectional view of another step, comparable to the step shown in Figure 2D, in the third exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 4E is a side cross-sectional view of another step, comparable to the step shown in Figure 2E, in the third exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figures 4F is a top plan view of an interim product formed in the step shown in Figure 4E, according to the third exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 4G is a side cross-sectional view of another step, comparable to the step shown in Figure 2G, in the third exemplary embodiment of a process for making a contact structure, according to the invention.
  • Figure 5A is a side cross-sectional view of a technique for creating an opening in a masking layer on a substrate, according to the prior art.
  • Figure 5B is a side cross-sectional view of an opening created in a masking layer on a substrate, according to the prior art.
  • Figure 5C is a side cross-sectional view of another technique for creating an opening in a masking layer on a substrate, according to the prior art.
  • Figure 5D is a side cross-sectional view of a technique for creating a tapered opening in a masking layer on a substrate, according to the invention.
  • Figure 5E is a side cross-sectional view of another technique for creating a tapered opening in a masking layer on a substrate, according to the invention.
  • Figure 5F is a side cross-sectional view of another technique for creating a tapered opening in a masking layer on a substrate, according to the invention.
  • Figure 6A is a top plan view of an embodiment of a tip end of a contact structure, according to the invention.
  • Figure 6B is a top plan view of another embodiment of a tip end of a contact structure, according to the invention.
  • Figure 7 illustrates a top plan view of a preferred embodiment of a spring shape, according to the invention.
  • Figure 8 illustrates a stencil for forming and transferring a protruding feature according to this invention.
  • Figures 1A-1C illustrate a technique of fabricating microelectronic contact structures which are spring contact elements, by depositing at least one layer of metallic material into o openings defined in multiple masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device, as disclosed in the aforementioned PARENT CASE.
  • a number of insulating layers having openings formed therein are aligned and "seeded” with a layer of conductive material.
  • a mass of conductive material can then be formed (or deposited) in the seeded opening(s), such as by 5 electroplating (or CVD, sputtering, electroless plating, etc.).
  • the masses can function as freestanding resilient contact structures which extend not only vertically above the surface of the component, but also laterally from the location whereat they are mounted.
  • the contact structures are readily engineered to be compliant in both the Z-axis as well as in the x-y plane (parallel to the surface of the component). Note 0 that in reference to Figures 1A, IB and IC "above” is to be read in the sense of the drawing only as the three dimension relationships can be transformed, translated and rotated generally and remain within the teachings of the invention.
  • Figure 1A is illustrative of an exemplary technique for fabricating one of a plurality of freestanding resilient (spring) contact elements 120 on a substrate 102.
  • the substrate 102 for 5 example, may be an active electronic component, including semiconductor devices, including semiconductor devices resident on a semiconductor wafer.
  • the substrate 102 has a plurality (one of many shown) or areas 112 on its surface whereat the spring contact elements will be fabricated.
  • these areas 112 preferably would be o terminals (such as bond pads) of the electronic component.
  • the technique involves applying a number (three shown) of patterned masking layers 104, 106 and 108 having openings onto the surface of the substrate.
  • the layers are patterned to have openings (as shown) aligned with the areas 112, and the openings are sized and shaped so that an opening in a one layer (e.g., 108, 106) extends further from the area 112 than an opening in an underlying layer (e.g., 106, 104, respectively).
  • the first layer 104 has an opening, which may be over the area 112.
  • a portion of the opening in the second layer 106 is aligned over at least a portion of the opening in the first layer 104 and, conversely, a portion of the first layer 104 extends under a portion of the opening in the second layer 106.
  • a portion of the opening in the third layer 108 is aligned over at least a portion of the opening in the second layer 106 and, conversely, a portion of the second layer 106 extends under a portion of the opening in the third layer 108.
  • the bottom portion of a given overall opening is over the selected area 112 and its top portion is elevated from its bottom portion.
  • a conductive metallic material is deposited into the openings, and the masking layers are removed, resulting in a free-standing contact structure having been fabricated directly upon the substrate with its base end secured to the substrate 102 at the area 112 and its free end extending both above the surface of the substrate and laterally-displaced from the area 112.
  • a thin (e.g., 4500 A) "seed" layer of conductive material 114 such as titanium-tungsten (Ti-W) may be deposited into the openings.
  • a mass of conductive metallic material (e.g., nickel) 120 can be deposited by electroplating into the openings.
  • Figures IB and IC illustrate a resulting spring contact element 120 having its base end 122 adjacent the area 112, and its free-end (tip) 124 elevated in the z-axis above the surface of the substrate 102 as well as laterally offset in the x-axis and y-axis from the base end 122.
  • the contact element 120 will react to pressure applied in the z-axis at its tip end 124, as indicated by the arrow 132, such as would result from making a temporary pressure electrical connection with a terminal (not shown) of another electronic component (not shown). Compliance in the z-axis ensures that contact force (pressure) will be maintained, and also accommodates non-planarities (if any) between terminals (not shown) on the other electronic component (not shown). Such temporary electrical connections are useful for making temporary connections to the electronic component 102, such as for performing burn-in and or testing of the component 102.
  • the tip end 124 may also be free to move compliantly in the x- and y- directions, as indicated by the arrows 136 and 134, respectively. This would be important in the context of joining (by soldering, or brazing, or with a conductive adhesive) the tip end 124 to a terminal (not shown) of another electronic component (not shown) which has a different coefficient of thermal expansion than the substrate (component) 102.
  • Such permanent electrical connections are useful for assemblies of electronic components, such as a plurality of memory chips (each of which is represented by the substrate 102) to another electronic component such as an interconnection substrate such as a printed circuit board ("PCB"; not shown).
  • these fabricated masses 120 can function as freestanding resilient contact structures that have been fabricated with very precise dimensions and very precise spacings from one another. For example, tens of thousands of such spring contact elements (120) are readily precisely fabricated on a corresponding number of terminals on semiconductor devices that are resident on a semiconductor wafer (not shown).
  • the resulting spring contact elements 120 are principally, preferably entirely, metallic, and may be formed (fabricated) as multilayer structures. Suitable materials for the one or more 0 layers of the contact structures are set forth in the PARENT CASE. A representative one of those materials is nickel (and its alloys).
  • the PARENT CASE describes a method of fabricating spring contact elements (120) directly on a substrate (102) such as an electronic component, such as a semiconductor device which may be resident on a semiconductor wafer, by applying at least one layer of s masking material (104, 106, 108) on a surface of the substrate (102) and patterning the masking layer to have openings extending from areas (112) on the substrate to positions which are spaced above the surface of the substrate and which also are laterally and/or transversely offset from the areas 112); by optionally seeding (114) the openings; by depositing at least one layer of a conductive metallic material into the openings; and by removing the masking material so that o the remaining conductive metallic material forms free-standing contact elements extending from the surface of the substrate, each contact element having a base end which is secured to a one of the areas of the substrate and having a tip end for making an electrical connection to a terminal of an electronic component.
  • the techniques of the present invention in at least one layer of s masking material (
  • contact structure can be fabricated with fewer layers of masking material (e.g. photoresist).
  • Figures 2A-2L illustrate an embodiment of the technique of the present invention.
  • FIG. 2A shows an exemplary electronic component 200 upon which a plurality of contact structures can be fabricated.
  • the fabrication of a single contact structure (260) will be described as exemplary of fabricating a plurality of such contact structures, preferably all at the same time on the same component.
  • each of the contact structures fabricated on a single component will be substantially identical to one another (i.e., dimensions, shape, etc.), but it is within the scope of this invention that the dimensions and 5 shape of each contact structure can individually be controlled and determined by the designer for given application requirements.
  • the electronic component 200 is a semiconductor device comprising a silicon substrate 202, a passivation layer (e.g., polyimide, 4 ⁇ m thick) 204 disposed on the surface of the silicon substrate 202, and a plurality (one of many shown) of openings 206 0 extending through the passivation layer 204 to a metallic contact pad 208.
  • a passivation layer e.g., polyimide, 4 ⁇ m thick
  • openings 206 0 extending through the passivation layer 204 to a metallic contact pad 208.
  • metallic contact pad 208 there are a plurality of such contact pads on an electronic component.
  • each contact pad is commonly (i.e., according to the prior art) connected (e.g., with a bond wire) to a corresponding contact pad on another electronic component (not shown), such as a thin small- outline package (TSOP).
  • TSOP thin small- outline package
  • a conductive layer 210 is deposited.
  • the conductive layer 210 is, for example, titanium-tungsten (Ti-W) which may be deposited by sputtering to a thickness of about 3000-6000 A (Angstroms), such as to a thickness of about 4500A.
  • the conductive layer 210 substantially conformally and contiguously covers the surface of the passivation layer 204, the sidewalls of the opening 206 and the exposed o (within the opening) surface of the metallic contact pad 208.
  • the conductive layer 210 is preferably electrically conductive and, if deposited as a continuous "blanket” layer, will electrically short together all of the contact pads (208) of the electronic component.
  • this shorting feature of the conductive layer 210 can advantageously be employed to establish an appropriate potential for an electrolytic 5 process (e.g., electroplating) for fabricating contact structures on the electronic component. It is within the scope of this invention that the conductive layer 210 can also be patterned, rather than continuous, and can be deposited as multiple, non-contiguous regions. In a preferred embodiment, the conductive layer 210 covers the exposed surface of terminal 208. In an alternative embodiment, the conductive layer 210 covers only a portion of terminal 208. In o another alternative embodiment, conductive layer 210 does not cover terminal 208 at all but is in the general area of terminal 208 such that when seed layer 250 is applied, it makes contact with conductive layer 210.
  • an electrolytic 5 process e.g., electroplating
  • a second conductive layer (412, described hereinbelow), of another material can be deposited and patterned onto the conductive layer 210 (see the analogous conductive layer 410, described hereinbelow in the description of Figure 4A).
  • This can be used, for example, to effect local interconnections and rerouting of signals from the contact pad 208 to the contact structure (260).
  • a dual layer may be preferred for many applications. Selection of suitable materials is within the skill in the art.
  • the contact pad (208) is on or in (yet exposed) the surface of the substrate (202) itself, without there being a passivation layer (204), although a passivation layer is commonly present on semiconductor devices.
  • the passivation layer 204 Prior to depositing the conductive layer 210, the passivation layer 204 (if there is one present) may optionally first be "roughed up" to enhance adhesion of the conductive layer 210 to the passivation layer 204.
  • suitable parameters that may be determined readily by one skilled in the art
  • suitable parameters that may be determined readily by one skilled in the art
  • a layer of masking material (e.g., photoresist) 220 is deposited onto the surface of the component 202 (i.e., onto the conductive layer 210) and is patterned (e.g., using conventional photolithographic techniques) to include an opening 222 extending completely through the masking layer 220.
  • the opening 222 may be o located either at a position which is over (as shown) the opening 206 in the passivation layer
  • the 204 or may be located at a position (as described hereinbelow) which is remote from the opening 206 and, consequently, remote from the contact pad 208.
  • a plurality of contact structures can be fabricated on the 5 electronic component with a layout that differs from that of the contact pads of the electronic component.
  • One particularly preferred configuration is to position openings 222 so that contact structures built thereon will have tips in an area array comparable to a ball grid array.
  • the openings can be connected to contact pads on the electronic component arranged, for example, as peripheral pads. It may be advantageous to make the contact structures substantially identical o without displacement from the contact pads. In this instance, it is useful to locate openings 222 in an area array corresponding to the array of the tips of the ultimate contact structures.
  • Each opening 222 preferably has a larger area than the area of opening 206 over the contact pad 208.
  • a square contact pad 208 measuring 4 mils x 4 mils i.e., 100 ⁇ m x 100 ⁇ m
  • a square opening 222 measuring 200 ⁇ m x 200 ⁇ m would have an area of 40.000 (four times the exposed area of the contact pad 208).
  • a circular opening 222 having a diameter of 200 ⁇ m would have an area of 31.400 ⁇ m 2 (approximately three times the exposed area of the contact pad 208).
  • the opening exposes an area of the terminal and/or substrate of between about 10,000 and about 40,000 ⁇ m 2 , most preferably in excess of about 30,000 ⁇ m 2 .
  • the footprint (base end area) of the contact structure should provide sufficient area for the mechanical securement (adhesion) of the contact structure to the electronic component.
  • the openings 222 it is preferred that they be tapered (as discussed in greater detail hereinbelow, with respect to Figures 5D-5F), and that the dimensions at the bottom of a tapered opening be on the order of 200 ⁇ m x 200 ⁇ m for a square opening, or 200 ⁇ m diameter for a circular opening. In applications that are space-constrained, and these dimensions are not possible, the available space can be used. For example, when dealing with an electronic component having 100 ⁇ m x 100 ⁇ m pads on 125 ⁇ m centers, the openings 222 can have dimensions on the order of 105 ⁇ m x 105 ⁇ m. 110 ⁇ m x 110 ⁇ m. or the like.
  • the bases of the contact structures can be remotely located (as described hereinbelow) from the pads to which they are electrically connected and have larger (e.g., 200 ⁇ m) preferred dimensions.
  • the tapered (sloped) region of the opening 222 is designated by the reference numeral 223 in Figure 2B.
  • the masking layer 220 is preferably deposited to a thickness of at least about 50 ⁇ m. including at least about 100 ⁇ m. at least about 150 ⁇ m. and at least about 200 ⁇ m.
  • the masking layer 220 can be deposited as multiple layers. It is the overall thickness of the masking layer 220 that will determine primarily the distance that the main body portion of the contact structure is spaced away from the surface of the electronic component. Note the offset distance "d2" of the main body portion 266 from the base portion 262 of the spring contact element 260 shown in Figure 2L. Compare Figure 3A of the aforementioned PARENT CASE.
  • the sidewalls (edgewalls) of the openings 222 are tapered so that the opening may be larger at the surface of the masking layer 220 than at the conductive layer 210. This is referred to as a "positive" taper. No taper would result in steep sidewalls having an angle of 90° (ninety degrees).
  • the sidewalls of the openings have an average taper angle of about
  • the tapered opening can be formed in any suitable manner and may, in fact, be stepped like an inverted, stepped, truncated pyramid. Controlling the shape of the opening (222) in the masking layer (220) is discussed in greater detail hereinbelow.
  • Figure 2C is a top plan view of the electronic component 200 of Figure 2B, showing two openings 222a and 222b in the masking layer 220, each opening associated with a one of two contact pads 208a and 208b (shown in dashed lines), respectively.
  • the tapered regions of the openings 222a and 222b are designated by the reference numerals 223 a and 223b, respectively, in this figure.
  • a protruding feature 230 may be deposited onto the surface of the masking layer 220 with its center at a distance "L" from the a center of the opening 222.
  • this feature 230 will define the contact (tip) end (264) of a resulting contact structure (260) being fabricated on the electronic component, and the distance "L” represents the straight-line distance between the base (262) and tip (264) ends of the contact structure (260) being fabricated on the electronic component.
  • the protruding feature 230 can be a "dot" or “dollop” of material, for example exhibiting a squashed hemispherical shape, and may be a small quantity of epoxy, photoresist, or the like which may suitably be applied through a stencil or by using conventional screen printing techniques.
  • the protruding feature 230 may also be of a conductive material. Suitable dimensions for a protruding feature 230 in the form of a squashed hemispherical dot are about 5-15 mils (125-375 ⁇ m in diameter and about 2 mils
  • the protruding feature can be skinnier (e.g., less than about 5 mils wide), or that it can be wider (e.g., greater than about 15 mils wide).
  • the photoresist can be soft-baked to release the protruding feature from the stencil then, after removing the stencil, hard-baked.
  • the distance "L”, between the base end (262) and tip end (264) of the resulting microelectronic spring contact structure may be, for example, in the range of about from IQ 5 1000 mils, preferably in the range of from 10-50 mils.
  • a stencil (shadow mask) 240 may be disposed over the surface of the masking layer 220.
  • the stencil 240 has a plurality (one of many shown) of openings 242. As illustrated, an opening 242 extends from opening 222 to a corresponding protruding feature 230.
  • the stencil 240 may suitably be a thin (e.g., about 2 mil 0 thick) foil of stainless steel which may be punched or etched to have openings 242.
  • Stencil 240 can be of any suitable material having any suitable thickness which will permit a seed layer 250 to be deposited onto the masking material 220 in a pattern of conductive traces corresponding to the shapes of the openings 242.
  • a "seed" layer 250 5 is deposited, such as by sputtering, onto the exposed surfaces of the masking layer 220 and protruding features 230.
  • the seed layer 250 is deposited within the exposed portions of opening 222 and onto the surface of the conductive layer 210 within opening 222.
  • the seed layer 250 has a sloped region 253 where it is deposited on the sloped region 223 of the opening 222 in the masking material 220.
  • the seed layer 250 may be deposited as a pattern of a plurality of "traces", each of which is a physical realization of the pattern of openings 242 in the overlying stencil 240.
  • the seed layer 250 serves as a precursor for a contact structure to be fabricated on the electronic component.
  • the conductive traces of the seed layer 250 will each serve as an electroform whereupon the substance (mass) of the contact 5 structure (260) can be fabricated.
  • the selection of masking material 220 and process for deposition of seed layer 250 need to be considered together.
  • the masking material needs to be stable in the environment of the deposition method.
  • a typical positive photoresist material contains some solvent and may outgas under high vacuum conditions. It is preferable in this instance to modify the o material, for example by baking or exposure to light in order to cross-link or otherwise rigidify the masking material.
  • Polyimide is a useful masking material and will tolerate a sputtering environment without significant degradation.
  • Deposition also can be by means of chemical vapor deposition (CVD) or e-beam processes. These require less vacuum than does sputtering. For these, traditional Novolac photoresist resins can be used, perhaps with some moderate cross- linking.
  • any modification to the masking material to make it stable under vacuum may make it more difficult to remove later in the process.
  • a suitable material and process can be selected by one skilled in the art.
  • One particularly preferred process is to use Novolac photoresist, patterned as described above, then partially cross-linked by heating. Deposition of seed layer 250 is performed using CVD.
  • Figure 2F illustrates the result of the steps described in Figure 2E in top view, and shows two openings 242a and 242b in a stencil 240, each opening 242a and 242b extending from over an associated one of two contact pads 208a and 208b (shown in dashed lines) to a selected one of two protruding features 230a and 230b (shown in dashed lines), respectively.
  • Figure 2F also illustrates two patterned traces 250a and 250b of the seed layer having been deposited through the openings 242a and 242b, respectively, in the stencil 240.
  • the traces 250a and 250b are illustrated with cross-hatching, for illustrative clarity, but it should clearly be understood that this cross-hatching does not indicate a cross-section in this figure.
  • Each of the traces 250a and 250b illustrated in Figure 2F has a base end 252a and 252b, 5 a tip end 254a and 254b, and a central body portion 256a and 256b, respectively, corresponding to the base ends (262), tip ends (264) and main body portions (266), respectively, of contact structures (260) that will be built up onto the conductive traces 250a and 250b.
  • the sloped regions 253a and 253b of the traces 250a and 250b, respectively, are illustrated in this figure.
  • FIG. 2G illustrates a next step of the process, wherein the shadow mask 240 has been o removed and a plurality (one of many shown) of contact structures 260 are built up, such as by plating (e.g., electroplating), as a mass of conductive material upon the plurality (one of many shown) of traces 230.
  • Each contact structure 260 has a base end portion 262 (compare 302 of the PARENT CASE), a tip end portion 264 (compare 304 of the PARENT CASE), and a main body portion 266 (compare 306 of the PARENT CASE) extending between the base end portion 5 262 and the tip end portion 264.
  • the contact structure 260 has a sloped region 263 between its base end 262 and its main body portion 266, the sloped region 263 being built on the sloped region 253 of the seed layer 250 which, in turn, is built on the sloped region 223 of the opening 222 in the masking material 220.
  • Figure 2H is a cross-sectional view of the electronic component 200 of Figure 2H, o taken on a line 2H-2H, illustrating the profile (transverse cross-section) of a contact structure
  • the profile is roughly semicircular or mushroom-shaped.
  • This section, taken through the main body portion 266 is representative of the profile of the contact structure throughout its entire length.
  • This structure is a result of electroplating on an exposed seed layer that is approximately planar.
  • the overall height "H" of the resulting contact structure 260 in other words the height of its tip end 264 away from the surface of the substrate 202, is preferably at least about 4.0 mils, and may be about 8.0 mils or greater.
  • the thickness "t" of the contact structure 260 itself- in other words, of the mass of conductive material on the trace 250 - is preferably at least about 0.5 mils and may be about 1.5 mils or greater.
  • the width "w" of the contact structure 260 itself - in other words, of the mass of conductive material on the trace 250 - is preferably at least about 0.5 mils 0 and may be about 4.0 mils or greater.
  • the width may be constant along the main body portion 266, or the main body portion may be tapered in width, for example, from wider near the base end 264 to narrower near the tip end 266 of the main body portion 266.
  • the length "L”, between the base end (262) and tip end (264) of the resulting microelectronic contact structure (260) is suitably at least about 10 mils and may 5 be as long as about 50 mils or greater.
  • Figures 21 and 2J are perspective views of two of many possible configurations for the contact structure 260 of Figure 2G, disassociated from the component 200, for illustrative clarity. These figures illustrate two important variations that can be selected using this invention.
  • the contact structure has a square base end 262.
  • the 5 contact structure has a round (circular) base end 262.
  • the funnel shape of the base end in the sloped region 263 is readily appreciated, said shape having been imparted to the base end by the sloping sidewalls (223) of the opening 222 in the masking layer 220.
  • the sloped region 263 of the base end 262 is completely covered (360°), and a small "lip" extends around the entire base end.
  • top plan views 2F and 2K show complete funnel embodiments, alternative to the partial funnel embodiments of detailed cross sections of Figures 2E, 2G and 2L.
  • Figures 2F and 2K can be modified 0 slightly to correspond to the specific embodiments of Figures 2E, 2G and 2L.
  • a resulting structure would resemble a partial funnel, as shown in Figure 21, with a circular base, as shown in Figure 2J.
  • Figure 2K is a top plan view of the electronic component 200 of Figure 2G illustrating two of a plurality of contact structures 260a and 260b, each contact structure 260a and 260b 5 associated with a one of two contact pads 208a and 208b (shown in dashed lines).
  • the contact structures 260a and 260b each have a base end 262a and 262b, a tip end 264a and 264b and a central body portion 266a and 266b, respectively.
  • the sloped regions 263 a and 263b of the contact structures 260a and 260b, respectively, are illustrated in this figure.
  • the resulting contact structures are suitably tapered o (widthwise) from wider at their base ends 262a and 262b to narrower at their tip ends 264a and
  • the contact structures 260a and 260b are illustrated with double cross-hatching, for illustrative clarity, but it should clearly be understood that this double cross-hatching does not indicate a cross-section in this figure. 5
  • the base end portion 262 hence the entire contact structure 260, is electrically connected to an associated one of the contact pads 208 of the electronic component via the seed layer 250 and the conductive layer 210.
  • a group of the contact pads 208 of the electronic component may be shorted to one another by the conductive layer 210 to facilitate o building up the contact structures 260 by an electroplating process.
  • the masking layer 220 can be removed, such as by washing it away with a suitable solvent.
  • a masking layer 220 of photoresist can selectively be washed away with acetone, without adversely affecting any of the other elements described hereinabove.
  • all portions of the conductive layer 210 that are not covered by another material (i.e., by the seed layer 250) can selectively be etched away using appropriate chemistry.
  • Figures 2L and 2M illustrate, in cross-section and perspective views, respectively, the final product of a free-standing contact structure 260 attached at its base end 262 to an electronic component, its main body portion 266 positioned away the surface of the electronic component 202, and its tip end portion 264 having a topography extending even farther from the level of the main body portion 266.
  • the sloped region 263 of the base end 262 of the resulting contact structure 260 is clearly visible in these figures, as well as in Figures 2N and 2O, described hereinbelow.
  • an elongate mass of conductive material is deposited onto the masking material so as to have a base end 262, a tip end 264 opposite the base end 262, and a main body portion 266 between the base end 262 and the tip end 264, wherein the main body portion 266 is in a plane which is preferably approximately parallel to the surface of the substrate 202 and which is offset (in the z-axis) from the base end 262.
  • the tip end 264 as a result of the protruding feature 230, is further offset from the main body portion 266.
  • the resulting contact structure 260 is freestanding, secured by its base end 262 to the substrate 202, with its tip end 264 free to make contact with a terminal (e.g., 270 or 280) of another electronic component (e.g., 272 or 282, respectively, described hereinbelow).
  • a terminal e.g., 270 or 280
  • another electronic component e.g., 272 or 282, respectively, described hereinbelow.
  • the contact structures of the present invention are principally, preferably entirely, metallic, and may be formed (fabricated) as multilayer structures.
  • Suitable materials for the one or more layers of the mass of conductive material for the contact structures include but are not limited to: nickel, and its alloys; copper, cobalt, iron, and their alloys; gold (especially hard gold) and silver, both of which exhibit excellent current-carrying capabilities and good contact resistivity characteristics; elements of the platinum group; noble metals; semi-noble metals and their alloys, particularly elements of the palladium group and their alloys; and tungsten, molybdenum and other refractory metals and their alloys.
  • Use of nickel and nickel alloys is particularly preferred. In cases where a solder-like finish is desired, tin, lead, bismuth, indium and their alloys can also be used.
  • Suitable processes for depositing the material for the conductive layer 210, the seed layer 250, and contact structure 260 include, but are not limited to: various processes involving deposition of materials out of aqueous solutions; electrolytic plating; electroless plating; chemical vapor deposition (CVD); physical vapor deposition (PVD); processes causing the deposition of materials through induced disintegration of liquid or solid precursors; and the like, all of these techniques for depositing materials being generally well known.
  • Suitable materials for the conductive layer 210 include titanium-tungsten (Ti-W) which may be deposited by sputtering to a thickness of 3000-6000 A. such as to a thickness of 4500A.
  • An optional but preferred addition to the conductive layer 210 is a layer of gold, which may be deposited to a thickness of 2500-4500 A thick, for example 3500 A thick.
  • the purpose of the conductive layer 210 is principally to provide an electrical connection to the conductive trace(s) 250 for the purpose of utilizing an electroplating process to build up a mass of conductive material which will become the resulting contact structure (260) on the seed layer. However, it is within the scope of this invention that the conductive layer 210 is omitted. Another process such as electroless plating may be employed for building up the mass of conductive material that will become the resulting contact structure.
  • the seed layer 250 can be, for example, gold (Au) which may be deposited by sputtering to a thickness of about 2500-4000A.
  • the seed layer is copper (Cu) which may be deposited by sputtering to a thickness of about 1000-3000A.
  • the seed layer 250 may another suitable material upon which the mass of the resulting contact structure (260) can be built up.
  • Suitable materials for the masking material (220, 320, 420) include a variety of lithographic photoresists, Novolac resin, and polyimide. COMPLIANCE AND RESILIENCE
  • Figure 2N illustrates a case wherein it is desired to make a pressure contact connection between a tip end 264 of a contact structure 260 and a contact pad 270 of another electronic component 272 such as a printed circuit board (PCB).
  • the contact structure 260 should react resiliently (i.e., elastically, rather than plastically) in the "z-axis" which is normal (at ninety degrees) to the surface of the substrate 202.
  • Such would be the case, for example, wherein it is desired to make socketable, readily removable, connections between the substrate 202 and the electronic component 272.
  • Figure 2O illustrates a case wherein it is desired to more permanently join, such as with solder 284, the tip end 264 of contact structure 260 to a contact pad 280 (compare 270) of another electronic component 282 (compare 272) such as a printed circuit board (PCB).
  • the contact structures 260 should react compliantly in the "x-axis" and/or "y-axis", both of which are parallel to the surface of the substrate 202. Such would be the case wherein it is desired to accommodate differences in thermal expansion coefficients between two electronic components.
  • the contact structure (260) reacts to applied forces by resiliently and/or compliantly deflecting in any or all of the x-, y- and z-axes.
  • Such a resilient contact structure can be enhanced by adding additional components.
  • a useful feature of the contact structure (260) of the present invention is that the tip end 264 is offset from the main body portion 266. This offset is a result of the presence of the protruding feature 230. Note the offset distance "dl" of the tip end portion 264 from the main body portion 266 of the spring contact element 260 shown in Figure 2L. Compare Figure 3A of the aforementioned PARENT CASE.
  • a contact structure may have a main body portion that extends to a tip end of the contact structure without the tip end being offset from the main body portion.
  • the tip end can be generally coplanar with the main body portion.
  • Figure 3A illustrates a masking layer 320 (compare 220) having an opening 322 (compare 222) applied over a conductive layer 310 (compare 210) on a substrate (compare 202) having a contact pad 308 (compare 208) exposed through an opening 306 (compare 206) in a passivation layer 304 (compare 204).
  • a protruding feature 230 is not provided.
  • the tapered region of the opening 322 is designated by the reference numeral 323 in this figure.
  • Figure 3B (compare Figure 2E also illustrates a stencil (shadow mask) 340 (compare 240) disposed over the masking layer 320, the stencil 340 having an opening 342 (compare 242) through which a seed layer 350 (compare 250) is deposited onto the masking layer 320, including into the openings 310 and 306 and onto the contact pad 308. Since a protruding feature (230) is not provided in this embodiment, it can be observed that the seed layer 350 does not "bump up" towards what will be the tip end portion of the resulting contact structure, but rather is essentially in line (coplanar) with what will be the main body portion of the resulting contact structure.
  • the seed layer 350 has a sloped region 353 where it is deposited on the sloped region 323 of the opening 322 in the masking material 320.
  • FIG. 3C illustrates the contact structure 360 (compare 260) resulting from such a process, after the aforementioned plating, washing off masking layer 320 and selectively etching away portions of the conductive layer 310 have occurred.
  • the resulting contact structure 360 has a base end 362 (compare 262) a tip end 364 (compare 264) and a main body portion 366 (compare 266).
  • the contact structure 360 has a sloped region 363 between its base end 362 and its main body portion 366. The sloped region 363 is on the sloped region 353 of the seed layer 350 which, in turn, is on the sloped region 323 of the opening 322 in the masking material 320.
  • Another useful enhancement to this structure is to include a spacer element so that the added tip element protrudes further away from main body portion 366.
  • Copending, commonly assigned United States Patent Application 08/ ⁇ not yet assigned>, filed January 29, 1998, entitled “MICROELECTRONIC CONTACT STRUCTURES, AND METHODS OF MAKING SAME” describes making a post structure, making a tip structure, joining the two together and to a supporting structure. This would work well with the resilient contact structure of Figure 3C, providing a resilient contact structure with a precisely defined tip structure.
  • a tip-post combination prepared as described in the copending application is brazed to the tip portion of main body portion 366 and the tip-post combination is released as described in the copending application.
  • tip portion 364 is secured by brazing material 381 to post 382, which is secured by brazing material 383 to tip body 384.
  • Tip body 384 is illustrated with a preferred tip point 385, but this feature is optional.
  • the base ends (262) having their base ends (262) generally directly on the locations of contact pads (208) of an electronic component such as a semiconductor device.
  • an electronic component such as a semiconductor device.
  • the tip end (264) of the contact structure (260) can have a different layout (pattern, pitch, etc.) than the contact pads to which they are connected.
  • the aforementioned U.S. Patent Application No. 08/955,001 discloses fabricating a spring contact element at an area on an electronic component which is remote from a terminal (contact pad) with which it is associated (to which it is electrically connected).
  • the spring contact element may be mounted to a conductive line that extends from a terminal (contact pad) of the electronic component to a position remote from the terminals.
  • a plurality of substantially identical spring contact elements can be mounted to the electronic component so that their free (distal) ends are disposed in a pattern and at positions which are not dependent on the pattern of the terminals on the electronic component.
  • the free ends of the spring contact terminals may be spatially translated from the terminals to which they are electrically connected.
  • the concept of locating spring contact elements remotely from the terminals of the electronic component can be incorporated into the technique(s) of the present invention so that the microelectronic contact structures of the present invention can be fabricated at positions remote from the terminals with which they are associated (electrically connected).
  • Figure 4A is comparable to Figure 2A, and illustrates an exemplary electronic component 400 (compare 200) upon which a plurality of contact structures can be fabricated.
  • the fabrication of a single contact structure (460, compare 260) will be described as exemplary of fabricating a plurality of such contact structures, preferably all at the same time on the same component.
  • each of the contact structures fabricated on a single component will be substantially identical to one another (i.e., dimensions, shape, etc.), but it is within the scope of this invention that the dimensions and shape of each contact structure can individually be controlled and determined by the designer for given application requirements.
  • the electronic component 400 is a semiconductor device comprising a silicon substrate 402 (compare 202), a passivation layer 404 (compare 204) disposed on the surface of the silicon substrate 402, and an opening 406 (compare 206) extending through the passivation layer 404 to a metallic contact pad 408 (compare 208).
  • a silicon substrate 402 compact 202
  • a passivation layer 404 compact 204
  • an opening 406 extending through the passivation layer 404 to a metallic contact pad 408 (compare 208).
  • a conductive layer 410 (compare 210) is deposited, such as a conformal, contiguous layer of titanium-tungsten (Ti-W) deposited by sputtering to a thickness of about 4500 A and covering the surface of the passivation layer 404, the sidewalls of the opening 406 and the exposed (within the opening) surface of the metallic contact pad 408.
  • a second conductive layer 412 can be deposited onto the conductive layer 410 and patterned to cover an area extending from a position on the contact pad 408 to a position 422 which is remote from the contact pad 408. Depositing and patterning the second conductive layer 412 is done with conventional semiconductor processing techniques including, but not limited to: (a) the second conductive layer 412 is deposited as a blanket layer, and subsequently patterned (e.g. using conventional photolithographic techniques);
  • the second conductive layer 412 is deposited as a patterned layer, using, for example, a stencil such as stencil 240 described above; or
  • the second conductive layer 412 is deposited as a blanket layer, covering all, or perhaps a region of, the conductive layer 410.
  • This second conductive layer 412 can be patterned in a subsequent step, for example using techniques described in the aforementioned U.S. Patent Application No. 08/955,001.
  • the second conductive layer 412 preferably is a 2500-4500 A thick, for example 3500 A thick, layer of gold (Au).
  • the design of and specific dimensions for second conductive layer 412 may correspond generally to a conventional trace and suitable dimensions can be selected readily by one skilled in the art.
  • a layer of masking material (e.g., photoresist) 420 is deposited onto the surface of the silicon substrate 402 (i.e., onto the conductive layer 410 and onto the second conductive layer 412) and is patterned (e.g., using conventional photolithographic techniques) to include an opening 422 (compare 222) extending completely through the masking layer 420.
  • a layer of masking material e.g., photoresist
  • the opening 422 is located at a position which is remote from the opening 406 and, consequently, remote from the contact pad 408, rather than being over (as described with respect to the previous example) the opening 406 in the passivation layer 404.
  • a plurality of substantially identical contact structures (460) can be fabricated on the electronic component with a layout that differs from that of the contact pads of the electronic component.
  • each opening 422 preferably has a larger area than the area of opening 406 over the contact pad 408.
  • the opening 422 may have an area of 40.000 ⁇ m 2 (four times the exposed area of the contact pad 408).
  • the footprint (base end area) of the contact structure should be sufficiently large (given spacing constraints) for mechanical securement (adhesion) of the contact structure to the electronic component.
  • the masking layer 420 is preferably deposited to a thickness of at least about 50 ⁇ m. including at least about 100 ⁇ m. at least about 150 ⁇ m. and at least about 200 ⁇ m.
  • the sidewalls (edgewalls) of the openings 422 are preferably positively tapered. In a manner similar to that described hereinabove with respect to Figure 2B, the tapered region of the opening 422 is designated by the reference numeral 423 in this figure.
  • Figure 4C (comparable to Figure 2C) is a top plan view of the electronic component 400 of Figure 4B, showing the opening 422 in the masking layer 420, and an associated contact pad 408 (shown in dashed lines).
  • the patterned portion of the second conductive layer 412 is also shown in dashed lines, extending from the contact pad 408 to within the opening 422.
  • the tapered region of the opening 422 is designated by the reference numeral 423 in this figure.
  • a protruding feature 430 may be deposited onto the surface of the masking layer 420 at a distance " L' " (comparable to the distance " L ") from the opening 422.
  • the feature 430 defines the basic geometry of a contact (tip) end (464) of a resulting contact structure (460) being fabricated on the electronic component 400.
  • the protruding feature 430 is a "dot” or “dollop” of material such as epoxy, photoresist, or the like.
  • a stencil (shadow mask) 440 (compare 240) is disposed over the surface of the masking layer 420 and has an opening 442 (compare 242).
  • a "seed" layer 450 e.g., of gold
  • sputtering a "seed” layer 450 is deposited (e.g., by sputtering) onto the exposed (through the openings 442) surfaces of the masking layer 420 and protruding feature 430, including extending down into the opening 422 in the masking layer 420 and onto the exposed surface of the second conductive layer 412.
  • the patterned portion seed layer 450 can be considered a "trace" which serves as a base for defining a contact structure 460 to be fabricated on the electronic component 400.
  • the seed layer 450 has a sloped region 453 where it is deposited on the sloped region 423 of the opening 422 in the masking material 420.
  • Figure 4F (comparable to Figure 2F) is a top plan view of the electronic component 400 of Figure 4E, showing the opening 442 in the stencil 440, the opening 442 extending from a position (the opening 422) which is remote from the contact pads 408 (shown in dashed lines) to the protruding feature 430 (shown in dashed lines).
  • Figure 4F also illustrates a patterned trace of the seed layer 450 having been deposited through the opening 442 in the stencil 440.
  • the trace is illustrated with cross-hatching, for illustrative clarity, but it should clearly be understood that this cross-hatching does not indicate a cross-section in this figure.
  • the trace has a base end 452, a tip end 454, and a central body portion 456.
  • Figure 4G illustrates the result after a next step of the process, wherein a contact structure 460 (compare 260) is built up upon the conductive trace of seed layer 450.
  • the contact structure 460 has a base end portion 462 (compare 262), a tip end portion 464 (compare 264) and a main body portion 466 (compare 266) extending between the base end portion 462 and the tip end portion 464.
  • the contact structure 460 has a sloped region 463 between its base end 462 and its main body portion 466, the sloped region 463 built on the sloped region 453 of the seed layer 450 which, in turn, is on the sloped region 423 of the opening 422 in the masking material 420.
  • a cross-sectional view of the contact structure 460, taken through the main body portion 466, would look comparable to the cross- sectional view of the contact structure 260 shown in Figure 21.
  • the contact structure 460 can be identical to the contact structure 260, with the notable exception that its base end 462 is remotely located from the contact pad 408 with which it is associated. In other words, the contact structure 460 can have the same range and variety of geometries, dimensions and materials as the contact structure 260.
  • the masking layer 420 can be removed, such as by washing it away with a suitable solvent, without adversely affecting any of the other elements described hereinabove.
  • all portions of the conductive layer 210 which are not covered by another material can selectively be etched away using appropriate chemistry, resulting in a final product of a free-standing contact structure 460 attached at its base end 462 to an electronic component 400 at a location which is 0 remote from the contact pad 408 to which it is electrically connected, its main body portion 466 being positioned away from the surface of the electronic component 400, and its tip end portion 464 having a topography positioned farther away from the level of the main body portion 466.
  • the contact structure of this example can be fabricated without first disposing the dot 430 on the masking layer, resulting in a contact 5 structure (compare 360) in which the tip end is in line with the main body portion. Again, however, the base end of such a contact structure would be remotely located from the contact pad to which it is electrically connected by the second conductive layer 412.
  • any combination of the various contact structures (e.g., 260, 360, 460) described hereinabove can be mounted to a single electronic o component.
  • a plurality of contact structures can be mounted to an electronic component and electrically connected to a corresponding plurality of terminals on the electronic component in a manner that the layout and/or pitch of the contact structures is different than that of the component terminals.
  • the component terminals may be disposed at a first pitch in a peripheral pattern and the tip ends of the contact structures may be disposed in an area array at a second pitch, or vice-versa.
  • each of the contact structures are fabricated to be substantially similar (such as identical) to one another.
  • One advantage of using similar structures is that the mechanical and resilient properties of the structures can be similar. Space translation can be effected by process steps that have minimal impact on the fabrication of the contact structures.
  • the conductive traces of second conductive layer 412 which effect the space translation can extend in a straight line (linearly) along the surface of the electronic component to the base end of the contact structures to effect "simple" space translation such as fan-out (or fan-in). Or, the conductive traces which effect the space translation can be routed along the surface of the electronic component including, if desired, crossing over one another to effect more complex space-translation schemes.
  • a benefit of the present invention is that the contact layout of an existing electronic component can be modified, after the electronic component has already been completely manufactured.
  • a completed (finished) semiconductor device has a number of bond pad terminals accessible on a surface thereof through openings in a passivation layer. If a plurality of identical contact structures were mounted to or fabricated upon those terminals, the tip ends of the contact structures "mirror" the layout of the bond pads.
  • the present invention essentially "relocates" the terminals (at least a portion thereof) so that the tip ends of the contact structures can have a completely different layout than the bond pads of the semiconductor device.
  • the hole (222, 322, 422) in the masking layer (220, 320, 420) be tapered. Openings that are tapered can be implemented in a number of ways.
  • Figures 5A and 5B illustrate a prior art technique for creating an opening 502 through a layer of masking material 504 on a substrate 506.
  • the masking layer 504 may be a photosensitive material, such as photoresist.
  • a photolithography mask 508 is disposed over the masking layer 504.
  • the mask 508 is transparent to (transmissive of) light from a preferably actinic light source 510.
  • the mask 508 has a pattern of opaque material 512 (e.g., iron oxide or chrome) on a surface thereof.
  • the mask 508 is placed as close as possible to the masking material 504 in what may be analogized to "contact printing" in the photographic industry.
  • an area 514 where there is no opaque material 512 on the surface of the mask 508 light from the source 510 can pass through the mask 508 onto the masking material 504.
  • the areas where there is opaque material 512 on the surface of the mask 508 light from the source 510 cannot pass through the mask 508 onto the masking material 504.
  • either the areas 522 or the area 524 can selectively be washed away (removed) with a suitable solvent, such as acetone. As best viewed in Figure 5B, the developed area 524 of the masking material 504 is washed away at the completion of exposure to light.
  • Figure 5C illustrates an alternate prior art technique for creating an opening (502) through a layer of masking material 504' (compare 504) on a substrate 506.
  • a photolithography mask 508 is disposed over the masking layer 504, and has a pattern of opaque material 514' (compare 512) on a surface thereof.
  • the opaque material 514' is over area 524' of the masking material 504' whereat it is desired to create the opening (502).
  • Remaining areas 512' (compare 514) of the mask 508 are not covered by opaque material so that light from the source 510 can pass through these areas onto underlying areas 522' of the masking material 504'.
  • the areas 522' are exposed to light and become "developed", and the area 524' is not exposed to light.
  • the area 524' can thus be washed away at the completion of exposure to light, resulting in the desired opening (502) in the layer of masking material 504'.
  • This exemplifies a "negative" photoresist, since the remaining masking material is the antithesis of the pattern of opaque material on the mask.
  • the sidewalls (edgewalls) of the openings (222, 322, 422) in the masking layer(s) of the present invention are tapered, and have a "positive” taper such as in the range of 60-75°.
  • tapered sidewalls in an opening in a masking material can be achieved, for example, by:
  • a stepped masking layer may optionally be reflowed to smooth out the step(s); or
  • the masking material 534 can be heated in a controlled manner and/or immersed in a dilute solvent. This can "soften” the angle of the steep sidewalls of the opening, resulting in an opening 538 (compare 222, 322, 422) which curves (tapers) gently (e.g. sinusoidal, as shown) from its base (at the surface of the substrate 536) to the top (as viewed) surface of the masking material 534. It is evident, however, that the area of the base of the opening will have diminished.
  • the initial opening in the masking material should be oversized accordingly, so that the final "re-flowed" dimension of the base of the opening has the desired dimensions (e.g., 200 ⁇ m diameter).
  • the opening 538 in the masking material 534 has a tapered region 539 (compare 223, 323, 423). (b) tapering by controlling exposure
  • Figure 5E illustrates a technique for creating an opening with a tapered sidewall through a layer of masking material 544 (compare 534) on a substrate 546 (compare 536) by using the exemplary technique described with respect to Figure 5A, and controlling the dose (exposure and duration) of light passing through the transparent area 514 of the mask 508.
  • portions of the masking material 544 closest to its surface (top, as viewed) will develop more quickly than portions of the masking material 544 which are "deeper” in the layer.
  • the fastest developing portion of the masking material 544 will thus be the top (as viewed) surface of the masking material 544 which is closest to the mask 508.
  • the slowest developing portion of the masking material 544 will thus be that portion which is immediately adjacent the substrate 546.
  • the development of the masking material 544 will be 5 uneven from its top surface (closest to the mask) to its bottom surface (farthest from the mask, closest to the substrate).
  • FIG. 5E which represents an interim product
  • portions 548a of the masking material 544 which are developed are indicated by wavy-line cross-hatching and, as mentioned above, can be washed away to provide the desired opening.
  • the opening would have the same o profile as the developed portion of the masking material.
  • one or more of the tapering techniques (a-e) disclosed o herein can be combined with one another to achieve the desired profile of the opening in the masking material.
  • Another technique for creating openings in a masking layer is to gradually move the mask (508) away from the substrate (506) during exposure. This will de-focus the mask image on the surface of the masking material, resulting in a situation that would resemble the interim product shown in Figure 5E.
  • the resulting opening may be larger than the transparent portion 514 of the mask 508. Therefore, the initial opening in the masking material may be undersized accordingly, so that the final dimension of the base of the opening has the desired dimensions (e.g., 200 ⁇ m diameter).
  • Figure 5F illustrates a technique for creating an opening with a tapered sidewall through a layer of masking material 554 (compare 544) on a substrate 556 (compare 546) by using the exemplary technique described with respect to Figure 5A.
  • a first mask is used to substantially fully develop a portion 558a of the masking material 554 in a first area having a first width dimension.
  • a second mask is used to substantially develop only a top portion 558b (e.g., half the thickness) of the masking material 554 in a second area having a second width dimension that is larger than the first width dimension.
  • the first exposure may result in the first area having a 200 ⁇ m diameter
  • the second exposure may result in the second area having a 225-250 ⁇ m diameter.
  • the second area is aligned over the first area so that they overlap, although they need not be concentric.
  • the masking material 554 having an opening 558 (compare 538) which is stepped, like an inverted wedding cake. It is within the scope of this invention that more than two masks can be used, each exposing a greater area than the previous one, to create an opening having more than one step. To remove sharp edges (if any) from the resulting opening 558, the masking material can be reflowed as in (a) above or otherwise treated to soften the slope of each sidewall. This figure shows that the opening 558 in the masking material 554 has a tapered region which, in this case, is stepped rather than smooth (compare 223, 323, 423).
  • the techniques (a-d) described hereinabove are primarily targeted at creating a tapered opening in a single layer of masking material. However, they may also be applied to each of a plurality of layers of masking material. For example, a first layer of masking material can be exposed, then a second masking layer applied on the first masking layer and exposed. After both masking layers are exposed, the masking layers would be washed to create the openings, whether the openings are the exposed areas of the masking material or the un-exposed areas of the masking material.
  • a final product such as is shown in Figure 5F may be fabricated by exposing a first layer of masking material to have a first area having a 200 ⁇ m diameter, then applying a second layer of masking material, then exposing the second layer of masking material to have a second area having a 225-250 ⁇ m diameter, then washing the masking material to have an opening which is stepped in the manner described hereinabove.
  • One or more of such multiple layers can be partially exposed, as described hereinabove with respect to Figure 5E, so that each of the exposed areas is, in and of itself, tapered.
  • the sidewall of the resulting opening in the masking material can be "smoothed", for example, by re-flowing, as described hereinabove.
  • having a smooth (rather than stepped) sidewall is beneficial, but is not required.
  • having a constant slope, or gradual change of slope, for the sidewall of the opening is beneficial, but is not required.
  • Multiple steps e.g., inverted wedding cake style
  • a useful average slope can be defined even with relatively steep sidewalls in each of the individual steps (tiers).
  • the objectives are generally to provide the mechanical benefits of a structure built with a sloped component.
  • a suitably sloped masking layer is readily coated (e.g., with seed layer 250) without mechanical or electrical discontinuities which otherwise would be a risk if the sidewall of the opening were tall and steep.
  • TIP GEOMETRIES The geometry of and patterns in the seed layer (250, 350, 450) upon which the contact structure (260, 360, 460, respectively) are built up is readily controlled, as is any desired patterning of the seed layer.
  • Base ends (262, 362, 462, respectively) of the contact structures (260, 360, 460, respectively) can be sized as large as desired.
  • Main body portions (266, 366, 466, respectively) of the contact structures (260, 360, 460, respectively) can be curved rather than straight.
  • Tip ends (264, 364, 464, respectively) of the contact structures (260, 360, 460, respectively) can have almost any desired shape.
  • the tip ends (264, 364, 464) illustrated hereinabove have been shown as having a circular profile (in plan view) (see, e.g., the top plan view of Figure 2K and the perspective view of Figure 2M). This has been described as corresponding to a generally hemispherical topology, but readily can be a conical or spheric section, and may be truncated, according to the shape of protruding feature 230 (or 430).
  • solder or braze the tip end 264 of the contact structure to a terminal 280 of an electronic component 282 such as a printed circuit board. It is evident from this illustration that the solder 284 forms a "fillet" which smoothly "flows" between the exposed area of the pad 280 and the exposed area of the tip 264 of the contact structure 260. As a general proposition, the greater the area for which the solder can form a fillet, the stronger the resulting solder joint will be.
  • the geometry of the conductive trace in the seed layer may be tailored so as to present an increased amount of surface area on the resulting tip end of the contact structure for fillet formation.
  • Figure 6A illustrates, in plan view, a one of many possible shapes for the tip end 614 (compare 264) of a contact structure 610 (compare 260).
  • the tip end 614 is formed as a ring, having a generally circular outside edge 614a, a generally circular inside edge 0 614b, and a gap 614c extending between the outside and inside edges 614a and 614b, respectively.
  • the entire outside and inside edges 614a and 614b, respectively would provide surface area to which the solder (compare 602) could adhere and form a fillet.
  • topology in one preferred form, this is in the form of a slotted disk, connected to the main body portion 616 by a 5 sloped section 613.
  • This sloped section is comparable to sloped region 263 (see Figure 2G) although 613 is between the main body portion and the tip portion.
  • the disk is generally flat, with gap 614c as shown.
  • Such a disk is formed on a protruding feature (see 230) in the form of a truncated cone, with an opening in the stencil (see 240) to define the slotted disk as shown.
  • the topology is a slotted hemisphere, built up on a hemispherical o protruding feature, using a stencil with the appropriate openings.
  • the tip is generally coplanar with main body portion 616.
  • Figure 6B illustrates, in plan view, another one of many possible shapes for the tip end 664 (compare 614) of a contact structure 660 (compare 610).
  • the tip end 614 is formed as a "cruciform" within an area (indicated by dashed lines) which is comparable to the 5 area of the tip 614. This is another way of augmenting the amount of tip surface area, hence fillet- formation area, for a tip of a given size.
  • the cruciform is made from a patterned disk, comparable to that described above with regard to Figure 6A. This includes a sloped section (not shown) comparable to sloped section 613.
  • the cruciform is simply an extension of and generally coplanar with the o main body portion of contact structure 660.
  • the cruciform is formed by appropriately masking a hemispherical protruding feature (see 230).
  • the emphasis is on increasing the useful wettable surface area (in the z-axis or, into the page, as viewed) of the tip end 614 and 664 of the contact structure 610 and 660, respectively.
  • the tip end has a thickness (into the sheet of the drawing, as viewed), and a side profile according to any of the embodiments of contact structures described hereinabove.
  • the protruding feature can be formed using a stencil or by screen printing.
  • One preferred method for forming a protruding feature is to use a stencil with specifically shaped and positioned openings.
  • stencil 810 is fabricated with one or more openings 815. These openings 815 can be patterned with high precision to correspond to the desired layout of protruding features on a finished article.
  • Each opening 815 also can be shaped to define a desired topology. In the example shown, the opening is tapered which would be useful for a truncated conic section or a truncated pyramidal section. Other shapes can be defined as desired.
  • the opening 815 is substantially filled with material 830 and the stencil is positioned on the masking layer (see 220 in Figure 2D) on an electronic component (see 202).
  • One preferred material 830 is photolithography resist material cured to have the desired mechanical and chemical properties. Materials for material 830 and for masking layer 220 can be selected so that the materials adhere such that stencil 810 can simply be lifted away from masking material 220 leaving protruding feature 230. An additional process such as heat or appropriate release conditions may be applied as needed.
  • Another preferred release mechanism is to drive the material 830 out of opening 815 by means of a post 825 mounted on release plate 820.
  • the stencil can be positioned against the masking layer (see 220) as before so material 830 contacts the masking material, then release plate 820 brought into position against the stencil 810, for example with post 825 just touching material 830. Moving the stencil toward release plate 820 (position 810'), post 825 will keep material 830 in contact with the masking material.
  • release plate 820 position 810'
  • post 825 will keep material 830 in contact with the masking material.
  • the resulting contact structures can be heat-treated to tailor their mechanical properties, as disclosed in commonly-owned, copending U.S. Patent Application No. 08/931,923 filed 17 Sep 97 (status: pending).
  • a contact structure(s) of nickel can be subjected to an "immersion gold" process known in the art to replace outer (exposed) portions of the nickel contact structure with gold. This will modify the ultimate contact properties of the contact structure(s) and or alter the metallurgy for the outer portions of the nickel contact structure and may serve to protect the contact structure in a subsequent selective etching process.
  • a contact structure is associated with (and electrically-connected to) a contact pad of the electronic component.
  • a number of variations have been described, such as including or not including protruding features (e.g., 230, 430) for altering the topology of the tip ends of the contact structures, fabricating the contact structure (e.g., 460) at a position remote from the corresponding contact pad, and controlling the geometry of the tip end (e.g., 614) so as to facilitate robust fillet formation during soldering.
  • the various techniques and structures disclosed herein can be "mixed and matched" with one another to create variations of the above, and various embodiments of contact structures can be disposed on any given electronic component.

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Abstract

Microelectronic contact structures (260, 360, 460) are lithographically defined and fabricated by applying a masking layer (220, 320, 420) on a surface of a substrate (202, 302, 402) such as an electronic component, creating an opening (222, 322, 422) in the masking layer, depositing a conductive trace of a seed layer (250, 350, 450) onto the masking layer and into the openings, and building up a mass of conductive material on the conductive trace. The sidewalls of the opening can be sloped (tapered). The conductive trace can be patterned by depositing material through a stencil or shadow mask (240, 340, 440). A protruding feature (230, 430) may be disposed on the masking layer so that a tip end (264, 364, 464) of the contact structure acquires a topography. All of these elements can be constructed as a group to form a plurality of precisely positioned resilient contact structures.

Description

LITHOGRAPHICALLY DEFINED MICROELECTRONIC CONTACT STRUCTURES
CROSS-REFERENCE TO RELATED APPLICATIONS
This patent application is a continuation-in-part of commonly-owned, copending U.S. s Patent Application entitled "MICROELECTRONIC CONTACT STRUCTURES", Serial No. 60/073,679 filed 04 Feb 98 by Pedersen and Khandros, incorporated by reference herein.
This patent application is also a continuation-in-part of commonly-owned, copending U.S. Patent Application No. 08/852,152 filed 06 May 97 by Eldridge, Khandros, Mathieu and Pedersen (status: pending) and its counterpart PCT Patent Application No. US97/08634 filed 15 0 May 97 (status: published as WO97/43654, 20 Nov 97), both of which are incorporated by reference herein, both of which are referred to hereinafter as the "PARENT CASE". TECHNICAL FIELD OF THE INVENTION
The present invention relates to resilient (spring) contact (interconnection) elements (structures) suitable for effecting pressure and/or compliant connections between electronic 5 components and, more particularly, to microminiature contact structures. BACKGROUND OF THE INVENTION
Commonly-owned, copending U.S. Patent Application No. 08/452,255 filed 26 May 95 by Eldridge, Grube, Khandros and Mathieu (status: pending) and its counterpart PCT patent application number PCT/US95/14909 filed 13 NOV 95 (status: published as WO95/14909, 06 o Jun 96) disclose methods for making resilient interconnection elements for microelectronics applications involving mounting an end of a flexible elongate core element (e.g., wire "stem" or "skeleton") to a terminal on an electronic component, coating the flexible core element and adjacent surface of the terminal with a "shell" of one or more materials having a predetermined combination of thickness, yield strength and elastic modulus to ensure predetermined force-to- 5 deflection characteristics of the resulting spring contacts. Exemplary materials for the core element include gold. Exemplary materials for the coating include nickel and its alloys. The resulting spring contact element may be used to effect pressure, or demountable, connections between two or more electronic components, particularly microelectronic components, including semiconductor devices. o The aforementioned PARENT CASE discloses fabricating spring contact elements by depositing at least one layer of metallic material into openings defined in multiple masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device. Each spring contact element has a base end, a contact end, and a central body portion. In an embodiment disclosed therein, the contact end may be offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end. In this manner, a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate. The spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween. In an exemplary application, the spring contact elements are disposed on a semiconductor devices resident on a semiconductor wafer so that temporary connections can be made with the semiconductor devices to burn-in and/or test the semiconductor devices prior to their being singulated from the semiconductor wafer. As in the PARENT CASE, the present invention addresses and is particularly well- suited to making interconnections to modern microelectronic devices having their terminals (bond pads) disposed at a fine-pitch. As used herein, the term "fine-pitch" refers to microelectronic devices that have their terminals disposed at a spacing of less than 5 mils, such as 2.5 mils or 65 μm. As will be evident from the description that follows, this is preferably achieved by taking advantage of the close tolerances that readily can be realized by using lithographic rather than mechanical techniques to fabricate the contact elements.
Commonly-owned, copending U.S. Patent Application No. 08/955,001 filed 20 Oct 97 by Eldridge, et al. (status: pending), incorporated by reference herein, also addresses and is particularly well-suited to making interconnections to modern microelectronic devices having their terminals (bond pads) disposed at a fine-pitch. As described therein, spring contact elements may be fabricated at areas on an electronic component which are remote from terminals to which they are electrically connected, and electrically connected to the terminals via conductive lines which extend from terminals of an electronic component to positions which are remote from the terminals. In this manner, a plurality of substantially identical spring contact elements can be mounted to the electronic component so that their free ends are disposed in a pattern and at positions which are spatially-translated from the pattern of the terminals on the component. The spring contact elements include, but are not limited to, composite interconnection elements and plated-up structures. The electronic component includes, but is not limited to, a semiconductor device, a memory chip, a portion of a semiconductor wafer, a space transformer, a probe card, a chip carrier, and a socket.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved technique for fabricating spring contact elements. Another object of the invention is to provide a technique for fabricating spring contact elements using processes that are inherently well suited to the fine-pitch, close-tolerance world of microelectronics.
Another object of the invention is to provide a technique for fabricating microminiature spring contact elements directly on active electronic components, such as semiconductor devices, without damaging the semiconductor devices. This includes fabricating microminiature spring contact elements on semiconductor devices resident on a semiconductor wafer, prior to the semiconductor devices being singulated from the semiconductor wafer.
Another object of the invention is to provide a technique for fabricating spring contact 0 elements that are suitable for socketing (one form of releasably connecting to) electronic components such as semiconductor devices, such as for performing burn-in on said devices.
According to the invention, microelectronic contact structures are fabricated by applying a masking layer on a surface of an electronic component, creating openings in the masking layer, depositing conductive traces onto the masking layer and into the openings, and building 5 up masses of conductive material on the conductive traces. The masses of conductive material each represent a contact structure having its base end extending up through the opening, having a main body portion extending across the masking layer (on the conductive trace), and having a tip end.
According to an aspect of the invention, the sidewalls of the openings in the masking o layer may preferably be tapered (sloped). Techniques for forming tapered (sloped) openings are disclosed herein.
According to an aspect of the invention, the conductive traces may be deposited onto the masking layer using a stencil (shadow mask).
According to an aspect of the invention, the openings in the masking layer defining the 5 base ends of selected ones of the contact structures can be located over contact pads of the electronic component. Alternatively, the openings in the masking layer defining base ends of selected ones of the contact structures can be located remote from the contact pads and connected to the contact pads by a patterned conductive layer underlying the masking layer.
According to an aspect of the invention, protruding features may be disposed on the o masking layer so that tip ends of the contact structures are offset from main body portions of the contact structures.
The electronic component may include, but is not limited to, an active semiconductor device, a memory chip, a portion of a semiconductor wafer, a space transformer, a probe card, a chip carrier, and a socket. In other words, the electronic component may be a passive device that supports one or more electronic connections. It is particularly preferred to add the microelectronic contact structures of this invention to an active electronic device, particularly a silicon semiconductor device.
The contact structures of this invention are suitable for making either temporary or permanent electrical connections to terminals of another electronic component such as a printed circuit board (PCB) interconnection substrate.
For making temporary connections, the component upon which the contact structures are fabricated is brought together with the other electronic component so that the tip ends of the contact structures make pressure connections with the terminals of the other electronic 0 component. The contact structures react resiliently (in elastic deformation mode) to maintain contact pressure and electrical connections between the two components.
For making permanent connections, the component upon which the contact structures are fabricated is brought together with the other electronic component, and the tip ends of the contact structures are joined, such as by soldering or brazing or with a conductive adhesive, to 5 the terminals of the other electronic component. The contact structures are compliant, and accommodate differential thermal expansion between the two electronic components.
The contact structures of the present invention can be fabricated directly on the surface of a semiconductor device, or on the surfaces of a plurality of semiconductor devices resident on a semiconductor wafer. In this manner, a plurality of semiconductor devices resident on a o semiconductor wafer can be "readied" for burn-in and/or test prior to being singulated from the semiconductor wafer.
According to an aspect of the invention, the tapered (sloped) openings in the masking layer manifest themselves as tapered (sloped) regions in the seed layer, as well as in tapered (sloped) regions of the resulting contact structures formed on the seed layer. 5 Other objects, features and advantages of the invention will become apparent in light of the following description thereof.
Briefly, the present invention is directed to the fabrication of one or more microelectronic contact structures. Such a structure may be fabricated by applying a masking layer on a surface of an electronic component, creating an opening in the masking layer, o depositing a seed layer (preferably as a conductive trace) onto the masking layer and into the opening, and building up a mass of conductive material on the conductive trace. The sidewalls of an opening can be tapered. Techniques for tapering the sidewalls of the opening are disclosed. The conductive traces can be deposited through a stencil (shadow mask), thereby obviating a need for an additional masking layer. A protruding feature, such as in the form of a dot of insulating material, may be disposed on the masking layer so that the tip end of the resulting contact structure has a topology. The mass of conductive material has a generally hemispherical lateral cross section as built up on the seed layer. The opening in the masking layer, defining a base end of the contact structure, can be over a contact pad of the electronic component, or remotely located therefrom and connected to the contact pad by a conductive trace.
Significant differences between the technique of the present invention and those disclosed in the PARENT CASE include, but are not limited to: a) In the PARENT CASE, the contact structure is built up in a multilevel trough in multilevel masking layers. The creation of such a multilevel trough is relatively complicated as compared with the relatively straightforward technique of the present invention that involves forming of openings (222) in a masking layer (220), preferably a single masking layer which can be patterned in a single step. b) The technique of the present invention facilitates the formation of tapered sidewalls (e.g., of the openings 222) which provide a smooth transition from one level of the contact structure (e.g., its base portion) to another level of the contact structure (e.g., its main body portion). c) The "third level" - namely the tip end of the contact structure is defined by the relatively straightforward instrumentality of a protruding feature (230) as opposed to another trough in another masking layer. d) The overall shape (geometry) of the contact structure is determined by and built up upon a conductive trace (250) rather than in a trough. As a general proposition, it is somewhat easier to reliably and controllably plate "onto" something (i.e., a conductive trace) than to plate "into" something (i.e., a trough). For implementing curved (versus linear) contact structures, this greatly simplifies pattern formation. e) The overall shape of the contact structure in the x and y dimensions (where the electronic component has a surface which is in the xy plane) is defined primarily by a stencil or shadow mask. In contrast, the x and y shape in the PARENT CASE is defined primarily by patterning various layers of masking material. BRIEF DESCRIPTION OF THE DRAWINGS
Reference will be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. The drawings are intended to be illustrative, not limiting. Although the invention will be described in the context of these preferred embodiments, it should be understood that it is not intended to limit the spirit and scope of the invention to these particular embodiments. Certain elements in selected ones of the drawings are illustrated not-to-scale, for illustrative clarity. Often, similar elements throughout the drawings are referred to by similar reference numerals. For example, the element 199 may be similar in many respects to the element 299 in another figure. Also, often, similar elements 5 are referred to with similar numbers in a single drawing. For example, a plurality of elements 199 may be referred to as 199a, 199b, 199c, etc.
Figure 1A is a side cross-sectional view of a technique for making a spring contact element, as disclosed in the PARENT CASE.
Figure IB is a side cross-sectional view of the spring contact element of Figure 1A, as o disclosed in the PARENT CASE.
Figure IC is a perspective view of the spring contact element of Figure IB, as disclosed in the PARENT CASE.
Figure 2A is a side cross-sectional view of a step in a first exemplary embodiment of a process for making a contact structure, according to the invention. 5 Figure 2B is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 2C is a top plan view of an interim product formed in the step shown in Figure 2B, according to the first exemplary embodiment of a process for making a contact structure, according to the invention. o Figure 2D is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 2E is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 2F is a top plan view of interim products formed in the step shown in Figure 2E, 5 according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 2G is a side cross-sectional view of another step in the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 2H is an end cross-sectional view of the product formed by the step shown in o Figure 2G, according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figures 21 and 2J are perspective views of two of many possible configurations for the contact structure of the present invention, highlighting its funnel-like base end. Figure 21 illustrates a structure resulting from partially coating the sidewalls of an opening, as shown in Figures 2E and 2G generally. Figure 2J shows a structure resulting from fully coating the sidewalls of an opening, as shown in Figures 4E and 4G.
Figure 2K is a top plan view of an interim product formed in the step shown in Figure 2G, according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figures 2L and 2M are side cross-sectional and perspective views, respectively of a completed contact structure formed on an electronic component, according to the first exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 2N is a side cross-sectional view of a contact structure of Figures 2L and 2M 0 with its tip end making contact with a contact pad of an electronic component, according to the invention.
Figure 2O is a side cross-sectional view of a contact structure of Figures 2L and 2M with its tip end soldered to a contact pad of an electronic component, according to the invention.
Figure 3 A is a side cross-sectional view of a step, comparable to the step shown in 5 Figure 2D, in a second exemplary embodiment of a portion of a process for making a contact structure, according to the invention.
Figure 3B is a side cross-sectional view of another step, comparable to the step shown in Figure 2E, in the second exemplary embodiment of a portion of a process for making a contact structure, according to the invention. o Figure 3C is a side cross-sectional view of another step, comparable to the step shown in Figure 2K, in the second exemplary embodiment of a portion of a process for making a contact structure, according to the invention.
Figure 3D is a side cross-sectional view of an optional enhanced structure, adding a tip and post structure to the structure of Figure 3C. 5 Figure 4A is a side cross-sectional view of a step, comparable to the step shown in
Figure 2A, in a third exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 4B is a side cross-sectional view of another step, comparable to the step shown in Figure 2B, in the third exemplary embodiment of a process for making a contact structure, o according to the invention.
Figure 4C is a top plan view of an interim product formed in the step shown in Figure 4B, according to the third exemplary embodiment of a process for making a contact structure, according to the invention. Figure 4D is a side cross-sectional view of another step, comparable to the step shown in Figure 2D, in the third exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 4E is a side cross-sectional view of another step, comparable to the step shown in Figure 2E, in the third exemplary embodiment of a process for making a contact structure, according to the invention.
Figures 4F is a top plan view of an interim product formed in the step shown in Figure 4E, according to the third exemplary embodiment of a process for making a contact structure, according to the invention. Figure 4G is a side cross-sectional view of another step, comparable to the step shown in Figure 2G, in the third exemplary embodiment of a process for making a contact structure, according to the invention.
Figure 5A is a side cross-sectional view of a technique for creating an opening in a masking layer on a substrate, according to the prior art. Figure 5B is a side cross-sectional view of an opening created in a masking layer on a substrate, according to the prior art.
Figure 5C is a side cross-sectional view of another technique for creating an opening in a masking layer on a substrate, according to the prior art.
Figure 5D is a side cross-sectional view of a technique for creating a tapered opening in a masking layer on a substrate, according to the invention.
Figure 5E is a side cross-sectional view of another technique for creating a tapered opening in a masking layer on a substrate, according to the invention.
Figure 5F is a side cross-sectional view of another technique for creating a tapered opening in a masking layer on a substrate, according to the invention. Figure 6A is a top plan view of an embodiment of a tip end of a contact structure, according to the invention.
Figure 6B is a top plan view of another embodiment of a tip end of a contact structure, according to the invention.
Figure 7 illustrates a top plan view of a preferred embodiment of a spring shape, according to the invention.
Figure 8 illustrates a stencil for forming and transferring a protruding feature according to this invention. DETAILED DESCRIPTION OF THE INVENTION
Prior to describing the techniques and resulting microelectronic contact structures of the present invention, a brief review of the techniques described in the PARENT CASE is useful. Although there is some commonality between the materials and processes employed by the 5 present invention and those of the PARENT CASE, and both are directed to fabricating microelectronic contact structures which may be spring contact elements, noticeable and dramatic differences will become evident in the discussion that follows.
Figures 1A-1C illustrate a technique of fabricating microelectronic contact structures which are spring contact elements, by depositing at least one layer of metallic material into o openings defined in multiple masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device, as disclosed in the aforementioned PARENT CASE. Generally, a number of insulating layers having openings formed therein are aligned and "seeded" with a layer of conductive material. A mass of conductive material can then be formed (or deposited) in the seeded opening(s), such as by 5 electroplating (or CVD, sputtering, electroless plating, etc.). After the insulating layers are removed, the masses can function as freestanding resilient contact structures which extend not only vertically above the surface of the component, but also laterally from the location whereat they are mounted. In this manner, the contact structures are readily engineered to be compliant in both the Z-axis as well as in the x-y plane (parallel to the surface of the component). Note 0 that in reference to Figures 1A, IB and IC "above" is to be read in the sense of the drawing only as the three dimension relationships can be transformed, translated and rotated generally and remain within the teachings of the invention.
Figure 1A is illustrative of an exemplary technique for fabricating one of a plurality of freestanding resilient (spring) contact elements 120 on a substrate 102. The substrate 102, for 5 example, may be an active electronic component, including semiconductor devices, including semiconductor devices resident on a semiconductor wafer.
The substrate 102 has a plurality (one of many shown) or areas 112 on its surface whereat the spring contact elements will be fabricated. In the case of the substrate 102 being an electronic component (such as a semiconductor device), these areas 112 preferably would be o terminals (such as bond pads) of the electronic component.
Generally, the technique involves applying a number (three shown) of patterned masking layers 104, 106 and 108 having openings onto the surface of the substrate. The layers are patterned to have openings (as shown) aligned with the areas 112, and the openings are sized and shaped so that an opening in a one layer (e.g., 108, 106) extends further from the area 112 than an opening in an underlying layer (e.g., 106, 104, respectively). In other words, the first layer 104 has an opening, which may be over the area 112. A portion of the opening in the second layer 106 is aligned over at least a portion of the opening in the first layer 104 and, conversely, a portion of the first layer 104 extends under a portion of the opening in the second layer 106. Similarly, a portion of the opening in the third layer 108 is aligned over at least a portion of the opening in the second layer 106 and, conversely, a portion of the second layer 106 extends under a portion of the opening in the third layer 108. The bottom portion of a given overall opening is over the selected area 112 and its top portion is elevated from its bottom portion. As will be discussed in greater detail hereinbelow, a conductive metallic material is deposited into the openings, and the masking layers are removed, resulting in a free-standing contact structure having been fabricated directly upon the substrate with its base end secured to the substrate 102 at the area 112 and its free end extending both above the surface of the substrate and laterally-displaced from the area 112.
If required, such as for electroplating, a thin (e.g., 4500 A) "seed" layer of conductive material 114 such as titanium-tungsten (Ti-W) may be deposited into the openings. Then, a mass of conductive metallic material (e.g., nickel) 120 can be deposited by electroplating into the openings.
Figures IB and IC illustrate a resulting spring contact element 120 having its base end 122 adjacent the area 112, and its free-end (tip) 124 elevated in the z-axis above the surface of the substrate 102 as well as laterally offset in the x-axis and y-axis from the base end 122.
As best viewed in Figure IC, the contact element 120 will react to pressure applied in the z-axis at its tip end 124, as indicated by the arrow 132, such as would result from making a temporary pressure electrical connection with a terminal (not shown) of another electronic component (not shown). Compliance in the z-axis ensures that contact force (pressure) will be maintained, and also accommodates non-planarities (if any) between terminals (not shown) on the other electronic component (not shown). Such temporary electrical connections are useful for making temporary connections to the electronic component 102, such as for performing burn-in and or testing of the component 102.
The tip end 124 may also be free to move compliantly in the x- and y- directions, as indicated by the arrows 136 and 134, respectively. This would be important in the context of joining (by soldering, or brazing, or with a conductive adhesive) the tip end 124 to a terminal (not shown) of another electronic component (not shown) which has a different coefficient of thermal expansion than the substrate (component) 102. Such permanent electrical connections are useful for assemblies of electronic components, such as a plurality of memory chips (each of which is represented by the substrate 102) to another electronic component such as an interconnection substrate such as a printed circuit board ("PCB"; not shown).
By suitable choice of material and geometry, these fabricated masses 120 can function as freestanding resilient contact structures that have been fabricated with very precise dimensions and very precise spacings from one another. For example, tens of thousands of such spring contact elements (120) are readily precisely fabricated on a corresponding number of terminals on semiconductor devices that are resident on a semiconductor wafer (not shown).
The resulting spring contact elements 120 are principally, preferably entirely, metallic, and may be formed (fabricated) as multilayer structures. Suitable materials for the one or more 0 layers of the contact structures are set forth in the PARENT CASE. A representative one of those materials is nickel (and its alloys).
Thus, the PARENT CASE describes a method of fabricating spring contact elements (120) directly on a substrate (102) such as an electronic component, such as a semiconductor device which may be resident on a semiconductor wafer, by applying at least one layer of s masking material (104, 106, 108) on a surface of the substrate (102) and patterning the masking layer to have openings extending from areas (112) on the substrate to positions which are spaced above the surface of the substrate and which also are laterally and/or transversely offset from the areas 112); by optionally seeding (114) the openings; by depositing at least one layer of a conductive metallic material into the openings; and by removing the masking material so that o the remaining conductive metallic material forms free-standing contact elements extending from the surface of the substrate, each contact element having a base end which is secured to a one of the areas of the substrate and having a tip end for making an electrical connection to a terminal of an electronic component. As will become evident from the description that follows, the techniques of the present invention, in at least certain respects, dramatically simplify the process 5 of fabricating microelectronic contact structures.
AN EXEMPLARY PROCESS OF THE PRESENT INVENTION
The process described hereinabove with respect to Figures 1A-1C utilizes three layers (104, 106, 108) of masking material which must be patterned and applied upon one another, resulting in a multi-level trench into which the material 120 must be deposited. o According to the present invention, a comparable microelectronic contact structure
(hereinafter "contact structure") can be fabricated with fewer layers of masking material (e.g. photoresist). Figures 2A-2L illustrate an embodiment of the technique of the present invention.
Figure 2A shows an exemplary electronic component 200 upon which a plurality of contact structures can be fabricated. In the main hereinafter, the fabrication of a single contact structure (260) will be described as exemplary of fabricating a plurality of such contact structures, preferably all at the same time on the same component. Typically, each of the contact structures fabricated on a single component will be substantially identical to one another (i.e., dimensions, shape, etc.), but it is within the scope of this invention that the dimensions and 5 shape of each contact structure can individually be controlled and determined by the designer for given application requirements.
In this example, the electronic component 200 is a semiconductor device comprising a silicon substrate 202, a passivation layer (e.g., polyimide, 4 μm thick) 204 disposed on the surface of the silicon substrate 202, and a plurality (one of many shown) of openings 206 0 extending through the passivation layer 204 to a metallic contact pad 208. Typically, there are a plurality of such contact pads on an electronic component. In a complete assembly, each contact pad is commonly (i.e., according to the prior art) connected (e.g., with a bond wire) to a corresponding contact pad on another electronic component (not shown), such as a thin small- outline package (TSOP). 5 As shown in Figure 2 A, in a first step of the process, a conductive layer 210 is deposited. The conductive layer 210 is, for example, titanium-tungsten (Ti-W) which may be deposited by sputtering to a thickness of about 3000-6000 A (Angstroms), such as to a thickness of about 4500A. The conductive layer 210 substantially conformally and contiguously covers the surface of the passivation layer 204, the sidewalls of the opening 206 and the exposed o (within the opening) surface of the metallic contact pad 208. The conductive layer 210 is preferably electrically conductive and, if deposited as a continuous "blanket" layer, will electrically short together all of the contact pads (208) of the electronic component. As will become evident from the description that follows, this shorting feature of the conductive layer 210 can advantageously be employed to establish an appropriate potential for an electrolytic 5 process (e.g., electroplating) for fabricating contact structures on the electronic component. It is within the scope of this invention that the conductive layer 210 can also be patterned, rather than continuous, and can be deposited as multiple, non-contiguous regions. In a preferred embodiment, the conductive layer 210 covers the exposed surface of terminal 208. In an alternative embodiment, the conductive layer 210 covers only a portion of terminal 208. In o another alternative embodiment, conductive layer 210 does not cover terminal 208 at all but is in the general area of terminal 208 such that when seed layer 250 is applied, it makes contact with conductive layer 210.
It is also within the scope of the invention that a second conductive layer (412, described hereinbelow), of another material (such as gold) can be deposited and patterned onto the conductive layer 210 (see the analogous conductive layer 410, described hereinbelow in the description of Figure 4A). This can be used, for example, to effect local interconnections and rerouting of signals from the contact pad 208 to the contact structure (260). In general, a dual layer may be preferred for many applications. Selection of suitable materials is within the skill in the art.
It is within the scope of the invention that the contact pad (208) is on or in (yet exposed) the surface of the substrate (202) itself, without there being a passivation layer (204), although a passivation layer is commonly present on semiconductor devices. Prior to depositing the conductive layer 210, the passivation layer 204 (if there is one present) may optionally first be "roughed up" to enhance adhesion of the conductive layer 210 to the passivation layer 204.
This can simply be accomplished by exposing the electronic component 200 to an oxygen (O2) plasma with suitable parameters (that may be determined readily by one skilled in the art) to obtain a desired surface texture on the passivation layer. Choice of materials will also affect adhesion of the seed layer to the passivation layer. Titanium-tungsten (Ti-W) or copper, for s example, are known to adhere well to polyimide.
As shown in Figure 2B, in a next step of the process, a layer of masking material (e.g., photoresist) 220 is deposited onto the surface of the component 202 (i.e., onto the conductive layer 210) and is patterned (e.g., using conventional photolithographic techniques) to include an opening 222 extending completely through the masking layer 220. The opening 222 may be o located either at a position which is over (as shown) the opening 206 in the passivation layer
204, or may be located at a position (as described hereinbelow) which is remote from the opening 206 and, consequently, remote from the contact pad 208.
As described in greater detail hereinbelow, by locating the openings 222 at positions remote from the contact pads 208, a plurality of contact structures can be fabricated on the 5 electronic component with a layout that differs from that of the contact pads of the electronic component. One particularly preferred configuration is to position openings 222 so that contact structures built thereon will have tips in an area array comparable to a ball grid array. The openings can be connected to contact pads on the electronic component arranged, for example, as peripheral pads. It may be advantageous to make the contact structures substantially identical o without displacement from the contact pads. In this instance, it is useful to locate openings 222 in an area array corresponding to the array of the tips of the ultimate contact structures.
Each opening 222 preferably has a larger area than the area of opening 206 over the contact pad 208. For example, a square contact pad 208 measuring 4 mils x 4 mils (i.e., 100 μm x 100 μm) would have an exposed area of 10.000 μm2. and a square opening 222 measuring 200 μm x 200 μm would have an area of 40.000 (four times the exposed area of the contact pad 208). A circular opening 222 having a diameter of 200 μm would have an area of 31.400 μm2 (approximately three times the exposed area of the contact pad 208). In general, it is preferred that the opening exposes an area of the terminal and/or substrate of between about 10,000 and about 40,000 μm2, most preferably in excess of about 30,000 μm2. Although not a key feature of the invention, as a general proposition, the footprint (base end area) of the contact structure should provide sufficient area for the mechanical securement (adhesion) of the contact structure to the electronic component.
Regarding the openings 222, it is preferred that they be tapered (as discussed in greater detail hereinbelow, with respect to Figures 5D-5F), and that the dimensions at the bottom of a tapered opening be on the order of 200 μm x 200 μm for a square opening, or 200 μm diameter for a circular opening. In applications that are space-constrained, and these dimensions are not possible, the available space can be used. For example, when dealing with an electronic component having 100 μm x 100 μm pads on 125 μm centers, the openings 222 can have dimensions on the order of 105 μm x 105 μm. 110 μm x 110 μm. or the like. Alternatively, in applications that are space-constrained, the bases of the contact structures can be remotely located (as described hereinbelow) from the pads to which they are electrically connected and have larger (e.g., 200 μm) preferred dimensions. The tapered (sloped) region of the opening 222 is designated by the reference numeral 223 in Figure 2B. The masking layer 220 is preferably deposited to a thickness of at least about 50 μm. including at least about 100 μm. at least about 150 μm. and at least about 200 μm. The masking layer 220 can be deposited as multiple layers. It is the overall thickness of the masking layer 220 that will determine primarily the distance that the main body portion of the contact structure is spaced away from the surface of the electronic component. Note the offset distance "d2" of the main body portion 266 from the base portion 262 of the spring contact element 260 shown in Figure 2L. Compare Figure 3A of the aforementioned PARENT CASE.
Preferably, the sidewalls (edgewalls) of the openings 222 are tapered so that the opening may be larger at the surface of the masking layer 220 than at the conductive layer 210. This is referred to as a "positive" taper. No taper would result in steep sidewalls having an angle of 90° (ninety degrees). Preferably, the sidewalls of the openings have an average taper angle of about
60-75°. This may readily be accomplished using photoresist as the material for the masking layer 220, and baking the photoresist and re-flowing it. One having ordinary skill in the art to which the present invention most nearly pertains will readily understand how to control the sidewall taper in light of the description presented herein. It is within the scope of this invention that the tapered opening can be formed in any suitable manner and may, in fact, be stepped like an inverted, stepped, truncated pyramid. Controlling the shape of the opening (222) in the masking layer (220) is discussed in greater detail hereinbelow.
Figure 2C is a top plan view of the electronic component 200 of Figure 2B, showing two openings 222a and 222b in the masking layer 220, each opening associated with a one of two contact pads 208a and 208b (shown in dashed lines), respectively. The tapered regions of the openings 222a and 222b are designated by the reference numerals 223 a and 223b, respectively, in this figure.
As shown in Figure 2D, in a next step of the process, for each of selected ones of the plurality of openings 222, a protruding feature 230 may be deposited onto the surface of the masking layer 220 with its center at a distance "L" from the a center of the opening 222. As will become evident, this feature 230 will define the contact (tip) end (264) of a resulting contact structure (260) being fabricated on the electronic component, and the distance "L" represents the straight-line distance between the base (262) and tip (264) ends of the contact structure (260) being fabricated on the electronic component. The protruding feature 230 can be a "dot" or "dollop" of material, for example exhibiting a squashed hemispherical shape, and may be a small quantity of epoxy, photoresist, or the like which may suitably be applied through a stencil or by using conventional screen printing techniques. The protruding feature 230 may also be of a conductive material. Suitable dimensions for a protruding feature 230 in the form of a squashed hemispherical dot are about 5-15 mils (125-375 μm in diameter and about 2 mils
(50 μm) in height. It is within the scope of this invention that the protruding feature can be skinnier (e.g., less than about 5 mils wide), or that it can be wider (e.g., greater than about 15 mils wide). Preferably, however, for most applications, it is preferred that its height be in the range of about 2.0 - 7.5 mils. As described in greater detail hereinbelow, other shapes for the protruding feature - more broadly, a variety of shapes for the resulting tip end (264) of the contact structure (260) being fabricated, including pyramidal, conical or hemispherical, and truncated versions of pyramidal, conical or hemispherical, and cruciform, rings and the like, are within the scope of the present invention. One having ordinary skill in the art to which the present invention most nearly pertains will readily understand how to apply and control the shape of the protruding features 230 in light of the description presented herein. For example, using photoresist and a stencil (not shown) to create the protruding features 230, with the stencil in place, the photoresist can be soft-baked to release the protruding feature from the stencil then, after removing the stencil, hard-baked.
The distance "L", between the base end (262) and tip end (264) of the resulting microelectronic spring contact structure may be, for example, in the range of about from IQ 5 1000 mils, preferably in the range of from 10-50 mils.
As shown in Figure 2E, in a next step of the process, a stencil (shadow mask) 240 may be disposed over the surface of the masking layer 220. The stencil 240 has a plurality (one of many shown) of openings 242. As illustrated, an opening 242 extends from opening 222 to a corresponding protruding feature 230. The stencil 240 may suitably be a thin (e.g., about 2 mil 0 thick) foil of stainless steel which may be punched or etched to have openings 242. Stencil 240 can be of any suitable material having any suitable thickness which will permit a seed layer 250 to be deposited onto the masking material 220 in a pattern of conductive traces corresponding to the shapes of the openings 242.
With the stencil 240 in place on the surface of the masking layer 220, a "seed" layer 250 5 is deposited, such as by sputtering, onto the exposed surfaces of the masking layer 220 and protruding features 230. The seed layer 250 is deposited within the exposed portions of opening 222 and onto the surface of the conductive layer 210 within opening 222. The seed layer 250 has a sloped region 253 where it is deposited on the sloped region 223 of the opening 222 in the masking material 220. o The seed layer 250 may be deposited as a pattern of a plurality of "traces", each of which is a physical realization of the pattern of openings 242 in the overlying stencil 240. The seed layer 250, as patterned, serves as a precursor for a contact structure to be fabricated on the electronic component. For example, in an electroplating process, the conductive traces of the seed layer 250 will each serve as an electroform whereupon the substance (mass) of the contact 5 structure (260) can be fabricated.
The selection of masking material 220 and process for deposition of seed layer 250 need to be considered together. The masking material needs to be stable in the environment of the deposition method. For example, a typical positive photoresist material contains some solvent and may outgas under high vacuum conditions. It is preferable in this instance to modify the o material, for example by baking or exposure to light in order to cross-link or otherwise rigidify the masking material. Polyimide is a useful masking material and will tolerate a sputtering environment without significant degradation. Deposition also can be by means of chemical vapor deposition (CVD) or e-beam processes. These require less vacuum than does sputtering. For these, traditional Novolac photoresist resins can be used, perhaps with some moderate cross- linking. Another consideration is that any modification to the masking material to make it stable under vacuum may make it more difficult to remove later in the process. A suitable material and process can be selected by one skilled in the art. One particularly preferred process is to use Novolac photoresist, patterned as described above, then partially cross-linked by heating. Deposition of seed layer 250 is performed using CVD.
Figure 2F illustrates the result of the steps described in Figure 2E in top view, and shows two openings 242a and 242b in a stencil 240, each opening 242a and 242b extending from over an associated one of two contact pads 208a and 208b (shown in dashed lines) to a selected one of two protruding features 230a and 230b (shown in dashed lines), respectively. 0 Figure 2F also illustrates two patterned traces 250a and 250b of the seed layer having been deposited through the openings 242a and 242b, respectively, in the stencil 240. The traces 250a and 250b are illustrated with cross-hatching, for illustrative clarity, but it should clearly be understood that this cross-hatching does not indicate a cross-section in this figure.
Each of the traces 250a and 250b illustrated in Figure 2F has a base end 252a and 252b, 5 a tip end 254a and 254b, and a central body portion 256a and 256b, respectively, corresponding to the base ends (262), tip ends (264) and main body portions (266), respectively, of contact structures (260) that will be built up onto the conductive traces 250a and 250b. The sloped regions 253a and 253b of the traces 250a and 250b, respectively, are illustrated in this figure. Figure 2G illustrates a next step of the process, wherein the shadow mask 240 has been o removed and a plurality (one of many shown) of contact structures 260 are built up, such as by plating (e.g., electroplating), as a mass of conductive material upon the plurality (one of many shown) of traces 230. Each contact structure 260 has a base end portion 262 (compare 302 of the PARENT CASE), a tip end portion 264 (compare 304 of the PARENT CASE), and a main body portion 266 (compare 306 of the PARENT CASE) extending between the base end portion 5 262 and the tip end portion 264. As illustrated, the contact structure 260 has a sloped region 263 between its base end 262 and its main body portion 266, the sloped region 263 being built on the sloped region 253 of the seed layer 250 which, in turn, is built on the sloped region 223 of the opening 222 in the masking material 220.
Figure 2H is a cross-sectional view of the electronic component 200 of Figure 2H, o taken on a line 2H-2H, illustrating the profile (transverse cross-section) of a contact structure
(260) made according to one preferred implementation of the invention. The profile is roughly semicircular or mushroom-shaped. This section, taken through the main body portion 266 is representative of the profile of the contact structure throughout its entire length. This structure is a result of electroplating on an exposed seed layer that is approximately planar. As best viewed in Figure 2G (see also Figure 2M), the overall height "H" of the resulting contact structure 260, in other words the height of its tip end 264 away from the surface of the substrate 202, is preferably at least about 4.0 mils, and may be about 8.0 mils or greater. As best viewed in Figure 2H, the thickness "t" of the contact structure 260 itself- in other words, of the mass of conductive material on the trace 250 - is preferably at least about 0.5 mils and may be about 1.5 mils or greater.
As best viewed in Figure 2H, the width "w" of the contact structure 260 itself - in other words, of the mass of conductive material on the trace 250 - is preferably at least about 0.5 mils 0 and may be about 4.0 mils or greater. The width may be constant along the main body portion 266, or the main body portion may be tapered in width, for example, from wider near the base end 264 to narrower near the tip end 266 of the main body portion 266.
As mentioned hereinabove, the length "L", between the base end (262) and tip end (264) of the resulting microelectronic contact structure (260) is suitably at least about 10 mils and may 5 be as long as about 50 mils or greater.
The general requirements for the design of a spring shape are generally known in the art. Details such as dimensions, bending moment, shape to allow flexibility in various dimensions, and the like can be selected by the designer and implemented according to the teachings of this invention. One particularly preferred shape approximates a circular section with a tapered inner o and outer radius of curvature. Such a shape is illustrated in Figure 7.
Figures 21 and 2J are perspective views of two of many possible configurations for the contact structure 260 of Figure 2G, disassociated from the component 200, for illustrative clarity. These figures illustrate two important variations that can be selected using this invention. In Figure 21, the contact structure has a square base end 262. In Figure 2J, the 5 contact structure has a round (circular) base end 262. In both of these figures, the funnel shape of the base end in the sloped region 263 is readily appreciated, said shape having been imparted to the base end by the sloping sidewalls (223) of the opening 222 in the masking layer 220. In Figure 2J, the sloped region 263 of the base end 262 is completely covered (360°), and a small "lip" extends around the entire base end. This complete funnel shape is readily obtained using a o stencil 440 that allows deposition of a seed layer along all of the side walls and a portion of the surface of masking layer 420. Such a stencil is illustrated in Figure 4E, and the resulting structure is illustrated in Figure 4G. Figure 21 shows the result of depositing a seed layer on only a portion of the sidewalls of opening 222. This is readily obtained using a stencil that covers a portion of opening 222, as illustrated in Figure 2E. More or less of the sidewalls can be covered according to the mask and deposition conditions selected. This may include only a portion of one sidewall, an entire sidewall as illustrated in Figure 21, portions of more than one sidewall (a preferred embodiment), or all of the sidewall area as illustrated in Figure 2J, forming a complete funnel (a particularly preferred embodiment). The resulting structure after plating is illustrated in cross section in Figure 2G. If the base is square, a perspective view of Figure 2G could resemble the view shown in Figure 21.
For convenience of illustration, top plan views 2F and 2K show complete funnel embodiments, alternative to the partial funnel embodiments of detailed cross sections of Figures 2E, 2G and 2L. One skilled in the art will recognize that Figures 2F and 2K can be modified 0 slightly to correspond to the specific embodiments of Figures 2E, 2G and 2L. A resulting structure would resemble a partial funnel, as shown in Figure 21, with a circular base, as shown in Figure 2J.
Figure 2K is a top plan view of the electronic component 200 of Figure 2G illustrating two of a plurality of contact structures 260a and 260b, each contact structure 260a and 260b 5 associated with a one of two contact pads 208a and 208b (shown in dashed lines). The contact structures 260a and 260b each have a base end 262a and 262b, a tip end 264a and 264b and a central body portion 266a and 266b, respectively. The sloped regions 263 a and 263b of the contact structures 260a and 260b, respectively, are illustrated in this figure.
As is evident in Figure 2K, the resulting contact structures are suitably tapered o (widthwise) from wider at their base ends 262a and 262b to narrower at their tip ends 264a and
264b, respectively, in a manner comparable to the tapered contact structures shown and described in the aforementioned PARENT CASE. The contact structures 260a and 260b are illustrated with double cross-hatching, for illustrative clarity, but it should clearly be understood that this double cross-hatching does not indicate a cross-section in this figure. 5 As is evident from the illustration of Figure 2G, the base end portion 262, hence the entire contact structure 260, is electrically connected to an associated one of the contact pads 208 of the electronic component via the seed layer 250 and the conductive layer 210. As is also evident, from the description set forth hereinabove, a group of the contact pads 208 of the electronic component may be shorted to one another by the conductive layer 210 to facilitate o building up the contact structures 260 by an electroplating process.
In final processing steps of the process, the masking layer 220 can be removed, such as by washing it away with a suitable solvent. For example, a masking layer 220 of photoresist can selectively be washed away with acetone, without adversely affecting any of the other elements described hereinabove. And finally, all portions of the conductive layer 210 that are not covered by another material (i.e., by the seed layer 250) can selectively be etched away using appropriate chemistry.
Figures 2L and 2M illustrate, in cross-section and perspective views, respectively, the final product of a free-standing contact structure 260 attached at its base end 262 to an electronic component, its main body portion 266 positioned away the surface of the electronic component 202, and its tip end portion 264 having a topography extending even farther from the level of the main body portion 266. The sloped region 263 of the base end 262 of the resulting contact structure 260 is clearly visible in these figures, as well as in Figures 2N and 2O, described hereinbelow. In essence, for each contact structure 260, an elongate mass of conductive material is deposited onto the masking material so as to have a base end 262, a tip end 264 opposite the base end 262, and a main body portion 266 between the base end 262 and the tip end 264, wherein the main body portion 266 is in a plane which is preferably approximately parallel to the surface of the substrate 202 and which is offset (in the z-axis) from the base end 262. The tip end 264, as a result of the protruding feature 230, is further offset from the main body portion 266. When the masking material 220 is removed, the resulting contact structure 260 is freestanding, secured by its base end 262 to the substrate 202, with its tip end 264 free to make contact with a terminal (e.g., 270 or 280) of another electronic component (e.g., 272 or 282, respectively, described hereinbelow). MATERIALS AND PROCESSES
In a manner comparable to that of the PARENT CASE, the contact structures of the present invention are principally, preferably entirely, metallic, and may be formed (fabricated) as multilayer structures. Suitable materials for the one or more layers of the mass of conductive material for the contact structures include but are not limited to: nickel, and its alloys; copper, cobalt, iron, and their alloys; gold (especially hard gold) and silver, both of which exhibit excellent current-carrying capabilities and good contact resistivity characteristics; elements of the platinum group; noble metals; semi-noble metals and their alloys, particularly elements of the palladium group and their alloys; and tungsten, molybdenum and other refractory metals and their alloys. Use of nickel and nickel alloys is particularly preferred. In cases where a solder-like finish is desired, tin, lead, bismuth, indium and their alloys can also be used.
Suitable processes for depositing the material for the conductive layer 210, the seed layer 250, and contact structure 260 include, but are not limited to: various processes involving deposition of materials out of aqueous solutions; electrolytic plating; electroless plating; chemical vapor deposition (CVD); physical vapor deposition (PVD); processes causing the deposition of materials through induced disintegration of liquid or solid precursors; and the like, all of these techniques for depositing materials being generally well known.
Suitable materials for the conductive layer 210 include titanium-tungsten (Ti-W) which may be deposited by sputtering to a thickness of 3000-6000 A. such as to a thickness of 4500A. An optional but preferred addition to the conductive layer 210 is a layer of gold, which may be deposited to a thickness of 2500-4500 A thick, for example 3500 A thick. The purpose of the conductive layer 210 is principally to provide an electrical connection to the conductive trace(s) 250 for the purpose of utilizing an electroplating process to build up a mass of conductive material which will become the resulting contact structure (260) on the seed layer. However, it is within the scope of this invention that the conductive layer 210 is omitted. Another process such as electroless plating may be employed for building up the mass of conductive material that will become the resulting contact structure.
The seed layer 250 can be, for example, gold (Au) which may be deposited by sputtering to a thickness of about 2500-4000A. In another preferred embodiment, the seed layer is copper (Cu) which may be deposited by sputtering to a thickness of about 1000-3000A. Alternatively, the seed layer 250 may another suitable material upon which the mass of the resulting contact structure (260) can be built up.
Suitable materials for the masking material (220, 320, 420) include a variety of lithographic photoresists, Novolac resin, and polyimide. COMPLIANCE AND RESILIENCE
Figure 2N illustrates a case wherein it is desired to make a pressure contact connection between a tip end 264 of a contact structure 260 and a contact pad 270 of another electronic component 272 such as a printed circuit board (PCB). In this case, the contact structure 260 should react resiliently (i.e., elastically, rather than plastically) in the "z-axis" which is normal (at ninety degrees) to the surface of the substrate 202. Such would be the case, for example, wherein it is desired to make socketable, readily removable, connections between the substrate 202 and the electronic component 272. Figure 2O illustrates a case wherein it is desired to more permanently join, such as with solder 284, the tip end 264 of contact structure 260 to a contact pad 280 (compare 270) of another electronic component 282 (compare 272) such as a printed circuit board (PCB). In this case, the contact structures 260 should react compliantly in the "x-axis" and/or "y-axis", both of which are parallel to the surface of the substrate 202. Such would be the case wherein it is desired to accommodate differences in thermal expansion coefficients between two electronic components.
It is within the scope of this invention that the contact structure (260) reacts to applied forces by resiliently and/or compliantly deflecting in any or all of the x-, y- and z-axes. Such a resilient contact structure can be enhanced by adding additional components.
Copending, commonly assigned United States Patent Application S.N. 08/819,464, entitled "Contact Tip Structures for Microelectronic Interconnection Elements and Methods of Making Same", and corresponding PCT application S.N. PCT US97/08606, published November 20, 1997 as WO97/43653, describes a method for defining a tip structure on a sacrificial substrate and transferring that structure to an electronic component. This tip structure can be transferred using the techniques described in that application to the structure of Figure 2L. ANOTHER EXEMPLARY CONTACT STRUCTURE
A useful feature of the contact structure (260) of the present invention is that the tip end 264 is offset from the main body portion 266. This offset is a result of the presence of the protruding feature 230. Note the offset distance "dl" of the tip end portion 264 from the main body portion 266 of the spring contact element 260 shown in Figure 2L. Compare Figure 3A of the aforementioned PARENT CASE.
In certain applications, however, it is contemplated that such an offset of the tip portion from the main body portion of a contact structure would not be required. According to an embodiment of the invention, a contact structure may have a main body portion that extends to a tip end of the contact structure without the tip end being offset from the main body portion. For example, the tip end can be generally coplanar with the main body portion. The process of fabricating such a contact structure would proceed largely in the manner described hereinabove, with respect to Figures 2A-2L, with the following variations. Figure 3A (compare Figure 2D) illustrates a masking layer 320 (compare 220) having an opening 322 (compare 222) applied over a conductive layer 310 (compare 210) on a substrate (compare 202) having a contact pad 308 (compare 208) exposed through an opening 306 (compare 206) in a passivation layer 304 (compare 204). As distinguished from Figure 2D, a protruding feature (230) is not provided. In a manner similar to that described hereinabove with respect to Figure 2B, the tapered region of the opening 322 is designated by the reference numeral 323 in this figure.
Figure 3B (compare Figure 2E also illustrates a stencil (shadow mask) 340 (compare 240) disposed over the masking layer 320, the stencil 340 having an opening 342 (compare 242) through which a seed layer 350 (compare 250) is deposited onto the masking layer 320, including into the openings 310 and 306 and onto the contact pad 308. Since a protruding feature (230) is not provided in this embodiment, it can be observed that the seed layer 350 does not "bump up" towards what will be the tip end portion of the resulting contact structure, but rather is essentially in line (coplanar) with what will be the main body portion of the resulting contact structure. The seed layer 350 has a sloped region 353 where it is deposited on the sloped region 323 of the opening 322 in the masking material 320.
Further processing steps would proceed as described with respect to the previous embodiment, including depositing the material that will form the contact structure 360, removing the masking layer 320, and removing exposed (not covered) portions of the conductive layer 310. Figure 3C (compare Figure 2K) illustrates the contact structure 360 (compare 260) resulting from such a process, after the aforementioned plating, washing off masking layer 320 and selectively etching away portions of the conductive layer 310 have occurred. The resulting contact structure 360 has a base end 362 (compare 262) a tip end 364 (compare 264) and a main body portion 366 (compare 266). As illustrated, the contact structure 360 has a sloped region 363 between its base end 362 and its main body portion 366. The sloped region 363 is on the sloped region 353 of the seed layer 350 which, in turn, is on the sloped region 323 of the opening 322 in the masking material 320.
This structure can be further processed by adding additional components to form a more complex structure. Copending, commonly assigned United States Patent Application S.N. 08/819,464, entitled "Contact Tip Structures for Microelectronic Interconnection Elements and Methods of Making Same", and corresponding PCT application S.N. PCT/US97/08606, published November 20, 1997 as WO97/43653, describes a method for defining a tip structure on a sacrificial substrate and transferring that structure to an electronic component. This tip structure can be transferred using the techniques described in that application to the structure of Figure 3C.
Another useful enhancement to this structure is to include a spacer element so that the added tip element protrudes further away from main body portion 366. Copending, commonly assigned United States Patent Application 08/ <not yet assigned>, filed January 29, 1998, entitled "MICROELECTRONIC CONTACT STRUCTURES, AND METHODS OF MAKING SAME" describes making a post structure, making a tip structure, joining the two together and to a supporting structure. This would work well with the resilient contact structure of Figure 3C, providing a resilient contact structure with a precisely defined tip structure. In one preferred embodiment, a tip-post combination prepared as described in the copending application is brazed to the tip portion of main body portion 366 and the tip-post combination is released as described in the copending application. Referring to Figure 3D, tip portion 364 is secured by brazing material 381 to post 382, which is secured by brazing material 383 to tip body 384. Tip body 384 is illustrated with a preferred tip point 385, but this feature is optional. REMOTELY LOCATING THE CONTACT STRUCTURES There has been described, hereinabove, a technique for fabricating contact structures
(260) having their base ends (262) generally directly on the locations of contact pads (208) of an electronic component such as a semiconductor device. In certain applications for the electronic component, it is desirable to locate a contact structure, particularly its base end, remotely from the contact pad to which it is connected. In this manner, the tip end (264) of the contact structure (260) can have a different layout (pattern, pitch, etc.) than the contact pads to which they are connected.
The aforementioned U.S. Patent Application No. 08/955,001 discloses fabricating a spring contact element at an area on an electronic component which is remote from a terminal (contact pad) with which it is associated (to which it is electrically connected). Generally, the spring contact element may be mounted to a conductive line that extends from a terminal (contact pad) of the electronic component to a position remote from the terminals. In this manner, a plurality of substantially identical spring contact elements can be mounted to the electronic component so that their free (distal) ends are disposed in a pattern and at positions which are not dependent on the pattern of the terminals on the electronic component. In a particularly useful embodiment, the free ends of the spring contact terminals may be spatially translated from the terminals to which they are electrically connected.
The concept of locating spring contact elements remotely from the terminals of the electronic component can be incorporated into the technique(s) of the present invention so that the microelectronic contact structures of the present invention can be fabricated at positions remote from the terminals with which they are associated (electrically connected).
Figure 4A is comparable to Figure 2A, and illustrates an exemplary electronic component 400 (compare 200) upon which a plurality of contact structures can be fabricated. The fabrication of a single contact structure (460, compare 260) will be described as exemplary of fabricating a plurality of such contact structures, preferably all at the same time on the same component. Typically, each of the contact structures fabricated on a single component will be substantially identical to one another (i.e., dimensions, shape, etc.), but it is within the scope of this invention that the dimensions and shape of each contact structure can individually be controlled and determined by the designer for given application requirements. As in the previously-described example, in this example, the electronic component 400 is a semiconductor device comprising a silicon substrate 402 (compare 202), a passivation layer 404 (compare 204) disposed on the surface of the silicon substrate 402, and an opening 406 (compare 206) extending through the passivation layer 404 to a metallic contact pad 408 (compare 208). As in the previously-described example, as shown in Figure 4A (comparable to Figure
2 A), in a first step of the process, a conductive layer 410 (compare 210) is deposited, such as a conformal, contiguous layer of titanium-tungsten (Ti-W) deposited by sputtering to a thickness of about 4500 A and covering the surface of the passivation layer 404, the sidewalls of the opening 406 and the exposed (within the opening) surface of the metallic contact pad 408. In contrast to the previously-described example, in this example, a second conductive layer 412 can be deposited onto the conductive layer 410 and patterned to cover an area extending from a position on the contact pad 408 to a position 422 which is remote from the contact pad 408. Depositing and patterning the second conductive layer 412 is done with conventional semiconductor processing techniques including, but not limited to: (a) the second conductive layer 412 is deposited as a blanket layer, and subsequently patterned (e.g. using conventional photolithographic techniques);
(b) the second conductive layer 412 is deposited as a patterned layer, using, for example, a stencil such as stencil 240 described above; or
(c) the second conductive layer 412 is deposited as a blanket layer, covering all, or perhaps a region of, the conductive layer 410. This second conductive layer 412 can be patterned in a subsequent step, for example using techniques described in the aforementioned U.S. Patent Application No. 08/955,001.
The second conductive layer 412 preferably is a 2500-4500 A thick, for example 3500 A thick, layer of gold (Au). The design of and specific dimensions for second conductive layer 412 may correspond generally to a conventional trace and suitable dimensions can be selected readily by one skilled in the art.
Various techniques for providing a patterned second conductive layer 412 are discussed in the aforementioned U.S. Patent Application No. 08/955,001, incorporated by reference herein. As shown in Figure 4B (comparable to Figure 2B), in a next step of the process, a layer of masking material (e.g., photoresist) 420 is deposited onto the surface of the silicon substrate 402 (i.e., onto the conductive layer 410 and onto the second conductive layer 412) and is patterned (e.g., using conventional photolithographic techniques) to include an opening 422 (compare 222) extending completely through the masking layer 420. In this example, the opening 422 is located at a position which is remote from the opening 406 and, consequently, remote from the contact pad 408, rather than being over (as described with respect to the previous example) the opening 406 in the passivation layer 404. By locating a plurality of such openings 422 at positions which are remote from the contact pads 408, a plurality of substantially identical contact structures (460) can be fabricated on the electronic component with a layout that differs from that of the contact pads of the electronic component.
As in the previously-described example, in this example, each opening 422 preferably has a larger area than the area of opening 406 over the contact pad 408. For example, the opening 422 may have an area of 40.000 μm2 (four times the exposed area of the contact pad 408). Again, although not a key feature of the invention, as a general proposition, the footprint (base end area) of the contact structure, should be sufficiently large (given spacing constraints) for mechanical securement (adhesion) of the contact structure to the electronic component.
As in the previously-described example, in this example the masking layer 420 is preferably deposited to a thickness of at least about 50 μm. including at least about 100 μm. at least about 150 μm. and at least about 200 μm. As in the previously-described example, in this example the sidewalls (edgewalls) of the openings 422 are preferably positively tapered. In a manner similar to that described hereinabove with respect to Figure 2B, the tapered region of the opening 422 is designated by the reference numeral 423 in this figure.
Figure 4C (comparable to Figure 2C) is a top plan view of the electronic component 400 of Figure 4B, showing the opening 422 in the masking layer 420, and an associated contact pad 408 (shown in dashed lines). In this view, the patterned portion of the second conductive layer 412 is also shown in dashed lines, extending from the contact pad 408 to within the opening 422. In a manner similar to that described hereinabove with respect to Figure 2C, the tapered region of the opening 422 is designated by the reference numeral 423 in this figure. In a manner comparable to that of the previously-described example, in this example, as shown in Figure 4D (comparable to Figure 2D), in a next step of the process, a protruding feature 430 may be deposited onto the surface of the masking layer 420 at a distance " L' " (comparable to the distance " L ") from the opening 422. As in the previously described example, in this example the feature 430 defines the basic geometry of a contact (tip) end (464) of a resulting contact structure (460) being fabricated on the electronic component 400. As in the previously described example, in this illustrative example, the protruding feature 430 is a "dot" or "dollop" of material such as epoxy, photoresist, or the like.
As in the previously-described example, in this example, as shown in Figure 4E, in a next step of the process, a stencil (shadow mask) 440 (compare 240) is disposed over the surface of the masking layer 420 and has an opening 442 (compare 242). With the stencil 440 in place on the surface of the masking layer 420, a "seed" layer 450 (e.g., of gold) is deposited (e.g., by sputtering) onto the exposed (through the openings 442) surfaces of the masking layer 420 and protruding feature 430, including extending down into the opening 422 in the masking layer 420 and onto the exposed surface of the second conductive layer 412. The patterned portion seed layer 450 can be considered a "trace" which serves as a base for defining a contact structure 460 to be fabricated on the electronic component 400. The seed layer 450 has a sloped region 453 where it is deposited on the sloped region 423 of the opening 422 in the masking material 420.
Figure 4F (comparable to Figure 2F) is a top plan view of the electronic component 400 of Figure 4E, showing the opening 442 in the stencil 440, the opening 442 extending from a position (the opening 422) which is remote from the contact pads 408 (shown in dashed lines) to the protruding feature 430 (shown in dashed lines).
Figure 4F also illustrates a patterned trace of the seed layer 450 having been deposited through the opening 442 in the stencil 440. The trace is illustrated with cross-hatching, for illustrative clarity, but it should clearly be understood that this cross-hatching does not indicate a cross-section in this figure. The trace has a base end 452, a tip end 454, and a central body portion 456.
Figure 4G (comparable to Figure 2G) illustrates the result after a next step of the process, wherein a contact structure 460 (compare 260) is built up upon the conductive trace of seed layer 450. The contact structure 460 has a base end portion 462 (compare 262), a tip end portion 464 (compare 264) and a main body portion 466 (compare 266) extending between the base end portion 462 and the tip end portion 464. As illustrated, the contact structure 460 has a sloped region 463 between its base end 462 and its main body portion 466, the sloped region 463 built on the sloped region 453 of the seed layer 450 which, in turn, is on the sloped region 423 of the opening 422 in the masking material 420. A cross-sectional view of the contact structure 460, taken through the main body portion 466, would look comparable to the cross- sectional view of the contact structure 260 shown in Figure 21.
In most respects, the contact structure 460 can be identical to the contact structure 260, with the notable exception that its base end 462 is remotely located from the contact pad 408 with which it is associated. In other words, the contact structure 460 can have the same range and variety of geometries, dimensions and materials as the contact structure 260.
As in the previously-described example (compare Figure 2K), in the final processing steps of the process in this example, the masking layer 420 can be removed, such as by washing it away with a suitable solvent, without adversely affecting any of the other elements described hereinabove. And finally, all portions of the conductive layer 210 which are not covered by another material (in this example, by the second conductive layer 412) can selectively be etched away using appropriate chemistry, resulting in a final product of a free-standing contact structure 460 attached at its base end 462 to an electronic component 400 at a location which is 0 remote from the contact pad 408 to which it is electrically connected, its main body portion 466 being positioned away from the surface of the electronic component 400, and its tip end portion 464 having a topography positioned farther away from the level of the main body portion 466.
As in the previously-described example, the contact structure of this example can be fabricated without first disposing the dot 430 on the masking layer, resulting in a contact 5 structure (compare 360) in which the tip end is in line with the main body portion. Again, however, the base end of such a contact structure would be remotely located from the contact pad to which it is electrically connected by the second conductive layer 412.
It is within the scope of this invention that any combination of the various contact structures (e.g., 260, 360, 460) described hereinabove can be mounted to a single electronic o component.
ROUTING AND SPACE TRANSLATION
With regard to the remotely located contact structures (460), various and complex routing schemes can be implemented in the manner contemplated by the aforementioned U.S. Patent Application No. 08/955,001. 5 In other words, a technique has been described for fabricating microelectronic contact structures on an electronic component that provides "space translation" from the contact pads (terminals) of the electronic component to which the contact structures are mounted. As used herein, the term "space translation" means that the tip (distal) ends of the contact structures are disposed at a different spacing (pitch) and or orientation than the terminals of the electronic o component to which they are electrically connected.
In this manner, a plurality of contact structures can be mounted to an electronic component and electrically connected to a corresponding plurality of terminals on the electronic component in a manner that the layout and/or pitch of the contact structures is different than that of the component terminals. For example, the component terminals may be disposed at a first pitch in a peripheral pattern and the tip ends of the contact structures may be disposed in an area array at a second pitch, or vice-versa.
Preferably, for a plurality of contact structures on an electronic component, each of the contact structures are fabricated to be substantially similar (such as identical) to one another. One advantage of using similar structures is that the mechanical and resilient properties of the structures can be similar. Space translation can be effected by process steps that have minimal impact on the fabrication of the contact structures.
The conductive traces of second conductive layer 412 which effect the space translation can extend in a straight line (linearly) along the surface of the electronic component to the base end of the contact structures to effect "simple" space translation such as fan-out (or fan-in). Or, the conductive traces which effect the space translation can be routed along the surface of the electronic component including, if desired, crossing over one another to effect more complex space-translation schemes.
A benefit of the present invention is that the contact layout of an existing electronic component can be modified, after the electronic component has already been completely manufactured. For example, a completed (finished) semiconductor device has a number of bond pad terminals accessible on a surface thereof through openings in a passivation layer. If a plurality of identical contact structures were mounted to or fabricated upon those terminals, the tip ends of the contact structures "mirror" the layout of the bond pads. The present invention essentially "relocates" the terminals (at least a portion thereof) so that the tip ends of the contact structures can have a completely different layout than the bond pads of the semiconductor device.
TAPERING THE HOLE(S) IN THE MASKING LAYER
As discussed hereinabove, it is preferred that the hole (222, 322, 422) in the masking layer (220, 320, 420) be tapered. Openings that are tapered can be implemented in a number of ways.
Figures 5A and 5B illustrate a prior art technique for creating an opening 502 through a layer of masking material 504 on a substrate 506. The masking layer 504 may be a photosensitive material, such as photoresist. A photolithography mask 508 is disposed over the masking layer 504. The mask 508 is transparent to (transmissive of) light from a preferably actinic light source 510. The mask 508 has a pattern of opaque material 512 (e.g., iron oxide or chrome) on a surface thereof.
Typically, the mask 508 is placed as close as possible to the masking material 504 in what may be analogized to "contact printing" in the photographic industry. In an area 514 where there is no opaque material 512 on the surface of the mask 508, light from the source 510 can pass through the mask 508 onto the masking material 504. In the areas where there is opaque material 512 on the surface of the mask 508, light from the source 510 cannot pass through the mask 508 onto the masking material 504. In this manner, "non- exposed" areas 522 of the masking material 504 under the opaque material 512 are shielded from light, and an "exposed" area 524 of the masking material 504 under the non-opaque area 514 of the mask 508 where there is no opaque material 512 will be exposed to light. Generally, the area 524 of the masking material 504 which is exposed to light passing through the mask 508 becomes "developed", and the areas 522 shielded from light passing through the mask 508 are not "developed". This exemplifies a "positive" photoresist, since the remaining masking material replicates the pattern of opaque material on the mask. Depending on whether the masking material 504 is "positive" or "negative", at the completion of exposure to light, either the areas 522 or the area 524 can selectively be washed away (removed) with a suitable solvent, such as acetone. As best viewed in Figure 5B, the developed area 524 of the masking material 504 is washed away at the completion of exposure to light.
Figure 5C illustrates an alternate prior art technique for creating an opening (502) through a layer of masking material 504' (compare 504) on a substrate 506. A photolithography mask 508 is disposed over the masking layer 504, and has a pattern of opaque material 514' (compare 512) on a surface thereof. In this example, the opaque material 514' is over area 524' of the masking material 504' whereat it is desired to create the opening (502). Remaining areas 512' (compare 514) of the mask 508 are not covered by opaque material so that light from the source 510 can pass through these areas onto underlying areas 522' of the masking material 504'. In this example, the areas 522' are exposed to light and become "developed", and the area 524' is not exposed to light. The area 524' can thus be washed away at the completion of exposure to light, resulting in the desired opening (502) in the layer of masking material 504'. This exemplifies a "negative" photoresist, since the remaining masking material is the antithesis of the pattern of opaque material on the mask.
As is known, for a given masking material (including "positive" and "negative" photoresist materials) there is an optimal exposure intensity and time to ensure that certain areas (e.g., 524) of the masking material (504) become fully developed. As best viewed in Figure 5B, such techniques can lead to very steep sidewalls in the resulting openings 502 created in the masking material 504. In most existing applications, steep sidewall openings are considered to be highly desirable. As mentioned above, preferably, the sidewalls (edgewalls) of the openings (222, 322, 422) in the masking layer(s) of the present invention are tapered, and have a "positive" taper such as in the range of 60-75°. The possibility of using photoresist for the material of the masking layer (220, 320, 420) and, starting with an opening having a steep sidewall (see, e.g., Figure 5B), then gently reflowing the photoresist to taper the sidewall was discussed hereinabove.
According to an aspect of the invention, tapered sidewalls in an opening in a masking material can be achieved, for example, by:
(a) gently reflowing the masking material to taper the sidewalls of openings; or (b) controlling the exposure intensity and/or time; or
(c) during exposure, varying the distance of the mask from the masking layer (essentially "de-focusing" the mask during exposure); or
(d) exposing the masking layer two or more times, once with a mask having a small transparent area (e.g., 514) and separately with a mask having a larger transparent area (essentially resulting in a stepped opening). A stepped masking layer may optionally be reflowed to smooth out the step(s); or
(e) creating overlying openings in each of multiple masking layers, each successively larger (or smaller) than the opening in the previous masking layer, again resulting in a stepped masking layer. This may optionally be reflowed to smooth out the one or more step(s); or (f) combinations of the above (a-e).
The descriptions (a)-(e) that follow expand upon the examples (a)-(e), respectively, set forth hereinabove.
(a tapering by reflowing
As illustrated in Figure 5D, commencing with a traditional opening 532 in a layer of masking material 534 on a substrate 536, the opening 532 exhibiting steep sidewalls (compare Figure 5B), in post-finishing steps the masking material 534 can be heated in a controlled manner and/or immersed in a dilute solvent. This can "soften" the angle of the steep sidewalls of the opening, resulting in an opening 538 (compare 222, 322, 422) which curves (tapers) gently (e.g. sinusoidal, as shown) from its base (at the surface of the substrate 536) to the top (as viewed) surface of the masking material 534. It is evident, however, that the area of the base of the opening will have diminished. Therefore, the initial opening in the masking material should be oversized accordingly, so that the final "re-flowed" dimension of the base of the opening has the desired dimensions (e.g., 200 μm diameter). This figure shows that the opening 538 in the masking material 534 has a tapered region 539 (compare 223, 323, 423). (b) tapering by controlling exposure
Figure 5E illustrates a technique for creating an opening with a tapered sidewall through a layer of masking material 544 (compare 534) on a substrate 546 (compare 536) by using the exemplary technique described with respect to Figure 5A, and controlling the dose (exposure and duration) of light passing through the transparent area 514 of the mask 508. Generally, portions of the masking material 544 closest to its surface (top, as viewed) will develop more quickly than portions of the masking material 544 which are "deeper" in the layer. The fastest developing portion of the masking material 544 will thus be the top (as viewed) surface of the masking material 544 which is closest to the mask 508. Conversely, the slowest developing portion of the masking material 544 will thus be that portion which is immediately adjacent the substrate 546.
By limiting the exposure to a fraction, such as half, of the exposure otherwise required to fully develop the entire area of the masking material 544 immediately underneath the transparent area 514 of the mask 508, the development of the masking material 544 will be 5 uneven from its top surface (closest to the mask) to its bottom surface (farthest from the mask, closest to the substrate).
In Figure 5E, which represents an interim product, portions 548a of the masking material 544 which are developed are indicated by wavy-line cross-hatching and, as mentioned above, can be washed away to provide the desired opening. The opening would have the same o profile as the developed portion of the masking material. Portions 548b of the masking material
544 which are not developed are indicated by no cross-hatching and, after washing away the developed portion, will define the sidewalls (shown as dashed lines) of the resulting opening. As in the previous example (a), since the sidewalls of the opening will taper from larger at the surface of the masking material to smaller at the surface of the substrate, the initial opening in 5 the masking material should be oversized accordingly, so that the final dimension of the base of the opening has the desired dimensions (e.g., 200 μm diameter). This figure shows that that portion 548a of the masking material 544 that will become an opening has a tapered region 549 (compare 223, 323, 423).
As mentioned hereinabove (f), one or more of the tapering techniques (a-e) disclosed o herein can be combined with one another to achieve the desired profile of the opening in the masking material.
(cl tapering by varying the mask distance
Another technique for creating openings in a masking layer, said openings having tapered sidewalls, is to gradually move the mask (508) away from the substrate (506) during exposure. This will de-focus the mask image on the surface of the masking material, resulting in a situation that would resemble the interim product shown in Figure 5E. By controlling how the distance from the mask to the masking material is varied, during exposure of the masking material, the resulting opening may be larger than the transparent portion 514 of the mask 508. Therefore, the initial opening in the masking material may be undersized accordingly, so that the final dimension of the base of the opening has the desired dimensions (e.g., 200 μm diameter).
(d) multiple exposures
Figure 5F illustrates a technique for creating an opening with a tapered sidewall through a layer of masking material 554 (compare 544) on a substrate 556 (compare 546) by using the exemplary technique described with respect to Figure 5A. In this example, a first mask is used to substantially fully develop a portion 558a of the masking material 554 in a first area having a first width dimension. A second mask is used to substantially develop only a top portion 558b (e.g., half the thickness) of the masking material 554 in a second area having a second width dimension that is larger than the first width dimension. For example, the first exposure may result in the first area having a 200 μm diameter, and the second exposure may result in the second area having a 225-250 μm diameter. Preferably, the second area is aligned over the first area so that they overlap, although they need not be concentric.
This will result in the masking material 554 having an opening 558 (compare 538) which is stepped, like an inverted wedding cake. It is within the scope of this invention that more than two masks can be used, each exposing a greater area than the previous one, to create an opening having more than one step. To remove sharp edges (if any) from the resulting opening 558, the masking material can be reflowed as in (a) above or otherwise treated to soften the slope of each sidewall. This figure shows that the opening 558 in the masking material 554 has a tapered region which, in this case, is stepped rather than smooth (compare 223, 323, 423).
(e) tapering by using multiple layers
The techniques (a-d) described hereinabove are primarily targeted at creating a tapered opening in a single layer of masking material. However, they may also be applied to each of a plurality of layers of masking material. For example, a first layer of masking material can be exposed, then a second masking layer applied on the first masking layer and exposed. After both masking layers are exposed, the masking layers would be washed to create the openings, whether the openings are the exposed areas of the masking material or the un-exposed areas of the masking material. For example, a final product such as is shown in Figure 5F may be fabricated by exposing a first layer of masking material to have a first area having a 200 μm diameter, then applying a second layer of masking material, then exposing the second layer of masking material to have a second area having a 225-250 μm diameter, then washing the masking material to have an opening which is stepped in the manner described hereinabove. One or more of such multiple layers can be partially exposed, as described hereinabove with respect to Figure 5E, so that each of the exposed areas is, in and of itself, tapered. And in a final postprocessing step, the sidewall of the resulting opening in the masking material can be "smoothed", for example, by re-flowing, as described hereinabove. Regarding creating an opening having a tapered sidewall, having a smooth (rather than stepped) sidewall is beneficial, but is not required. Also, having a constant slope, or gradual change of slope, for the sidewall of the opening is beneficial, but is not required. Multiple steps (e.g., inverted wedding cake style) can advantageously be employed, particularly if there are many, relatively thin steps. A useful average slope can be defined even with relatively steep sidewalls in each of the individual steps (tiers). The objectives are generally to provide the mechanical benefits of a structure built with a sloped component. A suitably sloped masking layer is readily coated (e.g., with seed layer 250) without mechanical or electrical discontinuities which otherwise would be a risk if the sidewall of the opening were tall and steep. TIP GEOMETRIES The geometry of and patterns in the seed layer (250, 350, 450) upon which the contact structure (260, 360, 460, respectively) are built up is readily controlled, as is any desired patterning of the seed layer. Base ends (262, 362, 462, respectively) of the contact structures (260, 360, 460, respectively) can be sized as large as desired. Main body portions (266, 366, 466, respectively) of the contact structures (260, 360, 460, respectively) can be curved rather than straight. Tip ends (264, 364, 464, respectively) of the contact structures (260, 360, 460, respectively) can have almost any desired shape. The tip ends (264, 364, 464) illustrated hereinabove have been shown as having a circular profile (in plan view) (see, e.g., the top plan view of Figure 2K and the perspective view of Figure 2M). This has been described as corresponding to a generally hemispherical topology, but readily can be a conical or spheric section, and may be truncated, according to the shape of protruding feature 230 (or 430).
As mentioned hereinabove, for example with respect to Figure 2O, in certain applications it is desirable to solder (or braze) the tip end 264 of the contact structure to a terminal 280 of an electronic component 282 such as a printed circuit board. It is evident from this illustration that the solder 284 forms a "fillet" which smoothly "flows" between the exposed area of the pad 280 and the exposed area of the tip 264 of the contact structure 260. As a general proposition, the greater the area for which the solder can form a fillet, the stronger the resulting solder joint will be.
Therefore, according to an aspect of the invention, the geometry of the conductive trace in the seed layer (250, 350, 450) may be tailored so as to present an increased amount of surface area on the resulting tip end of the contact structure for fillet formation.
Figure 6A illustrates, in plan view, a one of many possible shapes for the tip end 614 (compare 264) of a contact structure 610 (compare 260). In this example, the tip end 614 is formed as a ring, having a generally circular outside edge 614a, a generally circular inside edge 0 614b, and a gap 614c extending between the outside and inside edges 614a and 614b, respectively. In this manner, for a given thickness (not visible in this view, would be into the page), the entire outside and inside edges 614a and 614b, respectively, would provide surface area to which the solder (compare 602) could adhere and form a fillet. In topology, in one preferred form, this is in the form of a slotted disk, connected to the main body portion 616 by a 5 sloped section 613. This sloped section is comparable to sloped region 263 (see Figure 2G) although 613 is between the main body portion and the tip portion. The disk is generally flat, with gap 614c as shown. Such a disk is formed on a protruding feature (see 230) in the form of a truncated cone, with an opening in the stencil (see 240) to define the slotted disk as shown. In a second preferred form, the topology is a slotted hemisphere, built up on a hemispherical o protruding feature, using a stencil with the appropriate openings. In a third preferred form, the tip is generally coplanar with main body portion 616.
Figure 6B illustrates, in plan view, another one of many possible shapes for the tip end 664 (compare 614) of a contact structure 660 (compare 610). In this example, the tip end 614 is formed as a "cruciform" within an area (indicated by dashed lines) which is comparable to the 5 area of the tip 614. This is another way of augmenting the amount of tip surface area, hence fillet- formation area, for a tip of a given size. In topology, in one preferred form, the cruciform is made from a patterned disk, comparable to that described above with regard to Figure 6A. This includes a sloped section (not shown) comparable to sloped section 613. In another preferred embodiment, the cruciform is simply an extension of and generally coplanar with the o main body portion of contact structure 660. In yet another preferred embodiment, the cruciform is formed by appropriately masking a hemispherical protruding feature (see 230).
In the top plan views of Figures 6A and 6B, the emphasis is on increasing the useful wettable surface area (in the z-axis or, into the page, as viewed) of the tip end 614 and 664 of the contact structure 610 and 660, respectively. The tip end has a thickness (into the sheet of the drawing, as viewed), and a side profile according to any of the embodiments of contact structures described hereinabove.
As mentioned above, the protruding feature can be formed using a stencil or by screen printing. One preferred method for forming a protruding feature is to use a stencil with specifically shaped and positioned openings. Referring to Figure 8, stencil 810 is fabricated with one or more openings 815. These openings 815 can be patterned with high precision to correspond to the desired layout of protruding features on a finished article. Each opening 815 also can be shaped to define a desired topology. In the example shown, the opening is tapered which would be useful for a truncated conic section or a truncated pyramidal section. Other shapes can be defined as desired.
The opening 815 is substantially filled with material 830 and the stencil is positioned on the masking layer (see 220 in Figure 2D) on an electronic component (see 202). One preferred material 830 is photolithography resist material cured to have the desired mechanical and chemical properties. Materials for material 830 and for masking layer 220 can be selected so that the materials adhere such that stencil 810 can simply be lifted away from masking material 220 leaving protruding feature 230. An additional process such as heat or appropriate release conditions may be applied as needed. Another preferred release mechanism is to drive the material 830 out of opening 815 by means of a post 825 mounted on release plate 820. The stencil can be positioned against the masking layer (see 220) as before so material 830 contacts the masking material, then release plate 820 brought into position against the stencil 810, for example with post 825 just touching material 830. Moving the stencil toward release plate 820 (position 810'), post 825 will keep material 830 in contact with the masking material. By this method, protruding features in a wide variety of shapes can be applied to a masking material. OTHER VARIATIONS Various extensions of the teaching of this invention will be available to one skilled in the art, taken in combination with these teachings. For example, rather than using a stencil (240) to define the electroform traces (250), appropriate materials and laser pantography can be employed to define and create the traces.
Commonly-owned, copending U.S. Patent Application No. 08/819,464 filed 06 Mar 97 by Eldridge, et al. (status: pending) and its counterpart PCT Patent Application No. US97/08606 filed 15 May 97 (status: published as WO07/43653, 20 Nov 97, discloses techniques for fabricating contact tip structures on a sacrificial substrate, mounting the pre-fabricated contact tip structures to ends of resilient contact structures, and removing the sacrificial substrate. Such techniques could be employed, for example, with the contact structure 360 described hereinabove, to impart a topology to the tip end 362 of the contact structure.
The resulting contact structures can be heat-treated to tailor their mechanical properties, as disclosed in commonly-owned, copending U.S. Patent Application No. 08/931,923 filed 17 Sep 97 (status: pending).
A contact structure(s) of nickel can be subjected to an "immersion gold" process known in the art to replace outer (exposed) portions of the nickel contact structure with gold. This will modify the ultimate contact properties of the contact structure(s) and or alter the metallurgy for the outer portions of the nickel contact structure and may serve to protect the contact structure in a subsequent selective etching process. CONCLUSION
Techniques are described hereinabove for fabricating microelectronic contact structures on an electronic component, wherein a contact structure is associated with (and electrically- connected to) a contact pad of the electronic component. A number of variations have been described, such as including or not including protruding features (e.g., 230, 430) for altering the topology of the tip ends of the contact structures, fabricating the contact structure (e.g., 460) at a position remote from the corresponding contact pad, and controlling the geometry of the tip end (e.g., 614) so as to facilitate robust fillet formation during soldering. The various techniques and structures disclosed herein can be "mixed and matched" with one another to create variations of the above, and various embodiments of contact structures can be disposed on any given electronic component.
Although the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character - it being understood that only preferred embodiments have been shown and described, and that all changes and modifications that come within the spirit of the invention are desired to be protected. Undoubtedly, many other variations on the themes set forth hereinabove will occur to one having ordinary skill in the art to which the present invention most nearly pertains, and such variations are intended to be within the scope of the invention, as disclosed herein.

Claims

CLAIMS Claims:
1. A method of making a contact structure, the method comprising providing an electronic component with a surface and a terminal adjacent the surface, depositing a masking layer on the electronic component with an opening adjacent the surface, depositing a seed layer of conductive material over at least a portion of the terminal to form a base region of the seed layer and over at least a portion of the masking layer to form a main body region of the seed layer, connecting the base region and main body region, and depositing on the seed layer a bulk layer of conductive material to form a contact structure electrically connected to the terminal.
2. The method of claim 1 further comprising: before depositing the masking layer, depositing an initial conductive layer of conductive material over at least a portion of the electronic component and over at least a portion of the terminal, then depositing the masking layer over at least a portion of the initial conductive layer.
3. The method of claim 1 further comprising removing the masking layer to free the resulting contact structure.
4. The method of claim 1 further comprising patterning the seed layer to define an outline of a resilient member.
5. The method of claim 1 further comprising patterning the main body region of the seed layer to include an approximately circular region, with an inner curve which is approximately circular with an inner radius and with an outer curve which is approximately circular with an outer radius, the outer radius greater than the inner radius, with the center point of the inner radius suitably offset from the center point of the outer radius so that the approximately circular region outlines a resilient member.
6. The method of claim 1 further comprising placing on the masking layer a protruding element, then depositing the seed layer to at least partially cover the protruding element, whereby when the bulk layer of conductive material is deposited on the seed layer, a portion of the bulk layer is deposited on the seed layer on the protruding element, providing a conductive region which is farther removed from the electronic component than other portions of the bulk layer.
7. The method of claim 1 wherein the main body region of the seed layer is approximately parallel to and displaced from the surface of the electronic component.
8. The method of claim 7 wherein the main body region is displaced from the surface of the electronic component by a distance of between about 125 ╬╝m and 5 mm.
9. The method of claim 7 wherein the main body region is displaced from the surface of the electronic component by a distance of between about 50 and 200 ╬╝m.
10. The method of claim 1 further comprising patterning the seed layer by depositing the seed layer through a shadow mask with one or more openings to define the shape of the desired seed layer.
11. The method of claim 1 further comprising fabricating the opening in the masking layer to include a sloped region between the surface of the electronic component and the surface of the masking layer away from the electronic component.
12. The method of claim 1 1 further comprising a connecting region of the seed layer that includes at least a portion of the sloped region, connecting between the main body region and the base region.
13. The method of claim 1 wherein the masking material has a thickness of between about 50 and 200 microns.
14. The method of claim 1 wherein the opening in the masking layer includes an area on the surface of the electronic component, which may include some or all of the terminal, with an area of about 10,000 to about 42,000 square microns.
15. The method of claim 1 wherein the opening in the masking layer includes an area on the surface of the electronic component, which may include some or all of the terminal, sufficient to secure the ultimate contact structure.
16. The method of claim 11 where the sloped region has an average angle of between about 60 and about 75 degrees.
17. The method of claim 6 wherein the protruding element protrudes between about 50 and 175 ╬╝m from the masking layer.
18. The method of claim 6 wherein the protruding element has a base dimension of between about 125 and about 375 ╬╝m.
19. The method of claim 1 wherein the seed layer has a thickness of between about 1000 and 4200 angstroms.
20. The method of claim 1 wherein the seed layer comprises gold with a thickness of about 2500 to about 4200 angstroms.
21. The method of claim 1 wherein the seed layer comprises copper with a thickness of about 1000 to about 3000 angstroms.
0 22. The method of claim 2 wherein the initial conductive layer has a thickness of between about 3000 and about 6000 angstroms.
23. The method of claim 2 wherein the initial conductive layer comprises an alloy of titanium and tungsten. 5
24. The method of claim 2 further comprising depositing a second conductive layer on the initial conductive layer.
25. The method of claim 24 wherein the second conductive layer is gold, with a thickness of o between about 2500 and about 4500 angstroms.
26. The method of claim 1 wherein the masking material comprises a material selected from the group consisting of polyimide, Novolac resin, and a photoresist.
27. The method of claim 1 wherein the opening has sidewalls and the seed layer substantially covers the sidewalls.
28. The method of claim 1 wherein the opening has sidewalls and the seed layer only partially covers the sidewalls.
29. The method of claim 1 wherein the seed layer is deposited by a process selected from the group consisting of sputtering, chemical vapor deposition, physical deposition, and e-beam deposition.
30. The method of claim 1 wherein the bulk layer of conductive material is deposited by electrolytic plating.
31. The method of claim 1 wherein the bulk layer of conductive material is deposited by a process selected from the group consisting of electrolytic plating, electroless plating, chemical vapor deposition, physical vapor deposition, a process involving the deposition of material out or aqueous solution, and a process causing the deposition of material through induced disintegration of a precursor, liquid or solid.
0 32. The method of claim 1 wherein the bulk layer of conductive material comprises nickel.
33. The method of claim 1 wherein the bulk layer of conductive material comprises a material selected from the group consisting of nickel, copper, cobalt, iron, gold, silver, elements of the platinum group, noble metals, semi-noble metals, elements of the palladium group, tungsten, 5 and molybdenum.
34. The method of claim 1 further comprising forming a conductive component between the terminal of the electronic component and a remote terminal on the surface of the electronic component, disposed away from the terminal, then depositing the masking layer with the o opening over the remote terminal rather than the original terminal, and further depositing the seed layer and the bulk layer to contact the remote terminal according to the opening in the masking layer.
35. The method of claim 1 further comprising fabricating a separate tip structure and joining it permanently to the contact structure to make a second, modified contact structure.
36. The method of claim 35 further comprising fabricating a post structure connected to the separate tip structure and joining the post structure to the contact structure to make a third, modified contact structure.
37. The method of claim 1 wherein the electronic component is a semiconductor device.
38. The method of claim 1 wherein the electronic component is a semiconductor device which has not been singulated from a wafer.
39. The method of claim 1 wherein the electronic component is selected from the group consisting of a semiconductor device, a memory device, a portion of a semiconductor wafer, a full semiconductor wafer, a space transformer, a ceramic device, a probe card, a chip carrier and a socket.
40. The method of claim 1 wherein the base region of the seed layer is in physical contact with the terminal.
41. The method of claim 1 wherein the base region of the seed layer is displaced from the terminal but is in electrical contact with the terminal.
42. A contact structure of conductive material, comprising a base region connected to an electronic component, the electronic component having a surface and a terminal adjacent the surface, a main body region, displaced away from the surface, and connected to the base region, each of the base and main body regions comprising the conductive material, whereby the contact structure is secured to the electronic component and electrically connected to the terminal.
43. The contact structure of claim 42 further comprising the main body region comprising an approximately circular region, with an inner curve which is approximately circular with an inner radius which is smaller than an outer curve which is approximately circular with an outer radius, with the center point of the inner radius suitably offset from the center point of the outer radius so that the approximately circular region outlines a resilient member.
44. The contact structure of claim 42 further comprising a tip region, connected to the main body region and protruding away from the main body region and away from the surface of the electronic component, electrically connected to the terminal.
45. The contact structure of claim 42 wherein the main body region is approximately parallel to and displaced from the surface of the electronic component.
46. The contact structure of claim 45 wherein at least a portion of the main body region is displaced from the surface of the electronic component by a distance of between 125 ╬╝m and 5 mm.
47. The contact structure of claim 45 wherein at least a portion of the main body region is displaced from the surface of the electronic component by a distance of between 50 and 200 ╬╝m.
48. The contact structure of claim 42 further comprising a sloped region within the connected base region and main body region .
49. The contact structure of claim 42 wherein the base region is connected to the surface of the electronic component, which may include some or all of the terminal, with an area of about 10,000 to about 42,000 square microns.
50. The contact structure of claim 42 wherein the base region is connected to the surface of the electronic component, which may include some or all of the terminal, with at least an area sufficient to secure the contact structure.
51. The contact structure of claim 48 where the sloped region has an average angle of between about 60 and about 75 degrees.
52. The contact structure of claim 44 wherein the tip region protrudes between about 50 and 175 ╬╝m from the main body region away from the surface of the electronic component.
53. The contact structure of claim 44 wherein the tip region has a base width of between 125 and about 375 ╬╝m, measured generally parallel to the surface of the electronic component.
54. The contact structure of claim 42 wherein the base has sidewalls that substantially form a funnel-type structure.
55. The contact structure of claim 42 wherein the base has sidewalls that substantially form a partial funnel-type structure.
56. The contact structure of claim 42 wherein the conductive material comprises nickel.
57. The contact structure of claim 42 wherein the conductive material comprises a material selected from the group consisting of nickel, copper, cobalt, iron, gold, silver, elements of the platinum group, noble metals, semi-noble metals, elements of the palladium group, tungsten, and molybdenum.
58. The contact structure of claim 42 further comprising a remote terminal adjacent the surface of the electronic component, and a conductive component connecting the remote terminal to the terminal of the electronic component, wherein the base region is secured to and connected to at least a portion of the remote terminal, and electrically connected to the terminal of the electronic component.
59. The contact structure of claim 42 wherein the electronic component is a semiconductor device. 5
60. The contact structure of claim 42 wherein the electronic component is a semiconductor device which has been singulated from a wafer.
61. The contact structure of claim 42 wherein the electronic component is selected from the o group consisting of a semiconductor device, a memory device, a portion of a semiconductor wafer, a full semiconductor wafer, a space transformer, a ceramic device, a probe card, a chip carrier and a socket.
62. The contact structure of claim 42 further comprising a separate tip structure joined permanently to the contact structure to make a second, modified contact structure.
63. The contact structure of claim 62 further comprising a post structure connected to the separate tip structure and joined to the contact structure to make a third, modified contact structure.
64. A method of using the contact structure of claim 42 by providing a second electronic component with a second terminal thereon and contacting the contact structure to the second terminal.
65. The method of claim 64 further comprising effecting a pressure connection between the contact structure and the second terminal so as to effect an electrical connection between the first and the second terminals.
66. The method of claim 64 further comprising effecting a permanent connection between the contact structure and the second terminal so as to effect an electrical connection between the first and the second terminals.
67. A method of fabricating a sloped sidewall in an opening in a layer of masking material for the preparation of a contact structure, the method comprising: providing a substrate, applying a masking material to the substrate, forming an opening in the masking material with a sloping sidewall.
5 68. The method of claim 67 wherein the masking material is photosensitive, and the masking material is applied to a first surface of the substrate to give a second surface of the masking material which is more or less at some distance from the first surface, and further comprising: exposing a first region of the material to a first depth with a first dimension parallel to the first surface, o exposing a second region of the material to a second depth with a second dimension parallel to the first surface, the second depth shallower than the first depth, measured from the second surface of the masking material, and the second dimension parallel to the first surface greater than the first dimension parallel to the first surface, and removing masking material from the first and second exposed regions, whereby a stepped opening is created in the masking material which is narrower at its deepest extent than at the second surface.
69. The method of claim 67 wherein a plurality of exposures to different depths each have a corresponding dimension parallel to the first surface which is increasingly greater with corresponding shallower depth, whereby removing the masking material from the exposed regions forms an opening with a generally sloping sidewall.
70. The method of claim 67 wherein process of preparing a generally sloping sidewall leaves some discontinuities from a smooth slope, the method further comprising reflowing the masking material to some extent to lessen at least some of the discontinuities.
71. A method of fabricating a sloped sidewall in an opening in a layer of masking material for the preparation of a contact structure, the method comprising: providing a substrate, applying a masking material to the substrate, forming an opening in the masking material, the opening having a sidewall, reflowing the masking material in the region of the opening so that the sidewall of the opening becomes more sloped.
72. A method of fabricating a sloped sidewall in an opening in a layer of masking material for the preparation of a contact structure, the method comprising: providing a substrate, the substrate having a surface applying a masking material to the surface of the substrate, exposing the masking material in varying degrees such that exposure deepest in the material have a dimension parallel to the surface of the substrate which is smaller than the dimension of the exposure in the shallowest exposure of the material, and removing exposed masking material to form an opening that is generally narrower closer to the surface of the substrate.
73. The method of claim 72 further comprising varying the intensity of exposure at different depths in the masking material.
74. The method of claim 72 further comprising varying patterns for exposing the masking material such that narrower patterns are used for deeper exposures and wider patterns are used for shallower exposures.
75. The method of claim 69 or claim 72 further comprising forming a shaped member within the opening such that a first portion of the shaped member is attached to the surface of the substrate and a second portion of the shaped member generally follows the shape of the opening in the masking material.
76. The method of claim 75 further comprising removing the masking material to leave a shaped member attached to the surface of the substrate.
77. An electronic component with a masking material with a pattern of sloped openings comprising: an electronic component, with a surface, a masking material on the surface, a plurality of openings in the masking material, at least some ones of the plurality of openings having at least one sloping sidewall, the sloping sidewall having an average angle different than approximately vertical.
78. The electronic component of claim 77 wherein the sloping sidewall is at an average angle of about 60 to 75 degrees from vertical.
79. The electronic component of claim 77 where the electronic component is selected from the group consisting of a semiconductor device, a memory device, a portion of a semiconductor 5 wafer, a full semiconductor wafer, a space transformer, a ceramic device, a probe card, a chip carrier and a socket.
80. A method of making a contact structure with a sloped region, the method comprising providing an electronic component with a surface and a terminal adjacent the surface, o applying a masking layer on the electronic component with an opening adjacent the terminal, the opening including a sloped region between the surface of the electronic component and the surface of the masking layer away from the electronic component, and applying a bulk layer of resilient material to connect to at least a portion of the terminal to form a base region of the bulk layer and over at least a portion of the masking layer to form a main body region of the bulk layer, connecting the base region and main body region along at least a portion of the sloped region, to form a contact structure electrically connected to the terminal and mechanically connected in a fixed relationship to the substrate.
81. The method of claim 80 further comprising removing the masking layer to free the resulting contact structure.
82. The method of claim 80 further comprising depositing a seed layer before applying the bulk layer, the seed layer connecting at least a portion of the terminal to form a base region of the seed layer and over at least a portion of the masking layer to form a main body region of the seed layer, connecting the base region and main body region along at least a portion of the sloped region.
83. The method of claim 82 further comprising patterning the seed layer to define an outline of a resilient member.
84. The method of claim 80 further comprising patterning the seed layer by depositing the seed layer through a shadow mask with one or more openings to define the shape of the desired seed layer.
85. The method of claim 80 further comprising patterning the main body region of the seed layer to include an approximately circular region, with an inner curve which is approximately circular with an inner radius and with an outer curve which is approximately circular with an outer radius, the outer radius greater than the inner radius, with the center point of the inner radius suitably offset from the center point of the outer radius so that the approximately circular region outlines a resilient member.
86. The method of claim 80 further comprising placing on the masking layer a protruding element, then depositing the bulk layer to at least partially cover the protruding element, providing a conductive region which is farther removed from the electronic component than other portions of the bulk layer.
87. The method of claim 80 wherein the main body region of the bulk layer is approximately parallel to and displaced from the surface of the electronic component.
88. The method of claim 87 wherein the main body region is displaced from the surface of the electronic component by a distance of between about 50 and 200 ╬╝m.
89. The method of claim 80 where the sloped region has an average angle of between about 60 and about 75 degrees.
90. The method of claim 86 wherein the protruding element protrudes between about 50 and 175 ╬╝m from the masking layer.
91. The method of claim 82 wherein the seed layer comprises gold with a thickness of about 2500 to about 4200 angstroms.
92. The method of claim 82 wherein the seed layer comprises copper with a thickness of about 1000 to about 3000 angstroms.
93. The method of claim 80 wherein the bulk layer of conductive material is deposited by electrolytic plating.
94. The method of claim 80 wherein the bulk layer of conductive material is deposited by a process selected from the group consisting of electrolytic plating, electroless plating, chemical vapor deposition, physical vapor deposition, a process involving the deposition of material out or aqueous solution, and a process causing the deposition of material through induced disintegration of a precursor, liquid or solid.
95. The method of claim 80 wherein the bulk layer of conductive material comprises a material selected from the group consisting of nickel, copper, cobalt, iron, gold, silver, elements of the platinum group, noble metals, semi-noble metals, elements of the palladium group, tungsten, and molybdenum.
96. The method of claim 80 further comprising forming a conductive component between the terminal of the electronic component and a remote terminal on the surface of the electronic component, disposed away from the terminal, then depositing the masking layer with the opening over the remote terminal rather than the original terminal, and further depositing the seed layer and the bulk layer to contact the remote terminal according to the opening in the masking layer.
97. The method of claim 80 wherein the electronic component is a semiconductor device.
98. The method of claim 80 wherein the electronic component is selected from the group consisting of a semiconductor device, a memory device, a portion of a semiconductor wafer, a full semiconductor wafer, a space transformer, a ceramic device, a probe card, a chip carrier and a socket.
99. A contact structure of conductive material, comprising a base region connected to an electronic component, the electronic component having a surface and a terminal adjacent the surface, a main body region, displaced away from the surface, and connected to the base region, a sloped region, connected to the base region and to the main body region and forming a portion of one or both of the base region and main body region, each of the base, sloped and main body regions comprising the conductive material, whereby the contact structure is secured to the electronic component and electrically connected to the terminal.
100. The contact structure of claim 99 further comprising the main body region comprising an approximately circular region, with an inner curve which is approximately circular with an inner radius which is smaller than an outer curve which is approximately circular with an outer radius, with the center point of the inner radius suitably offset from the center point of the outer radius so that the approximately circular region outlines a resilient member.
101. The contact structure of claim 99 further comprising a tip region, connected to the main body region and protruding away from the main body region and away from the surface of the electronic component, electrically connected to the terminal.
102. The contact structure of claim 99 wherein the main body region is approximately parallel to and displaced from the surface of the electronic component.
103. The contact structure of claim 99 wherein the base region is connected to the surface of the electronic component, which may include some or all of the terminal, with at least an area sufficient to secure the contact structure.
104. The contact structure of claim 99 where the sloped region has an average angle of between about 60 and about 75 degrees.
105. The contact structure of claim 101 wherein the tip region protrudes between about 50 and 175 ╬╝m from the main body region away from the surface of the electronic component.
106. The contact structure of claim 99 wherein the base has sidewalls that substantially form at least part of a funnel-type structure.
107. The contact structure of claim 99 wherein the conductive material comprises nickel.
108. The contact structure of claim 99 wherein the conductive material comprises a material selected from the group consisting of nickel, copper, cobalt, iron, gold, silver, elements of the platinum group, noble metals, semi-noble metals, elements of the palladium group, tungsten, and molybdenum.
109. The contact structure of claim 99 further comprising a remote terminal adjacent the surface of the electronic component, and a conductive component connecting the remote terminal to the terminal of the electronic component, wherein the base region is secured to and connected to at least a portion of the remote terminal, and electrically connected to the terminal of the electronic component.
110. The contact structure of claim 99 wherein the electronic component is a semiconductor device.
111. The contact structure of claim 99 wherein the electronic component is selected from the group consisting of a semiconductor device, a memory device, a portion of a semiconductor wafer, a full semiconductor wafer, a space transformer, a ceramic device, a probe card, a chip carrier and a socket.
112. In a lithographically defined contact structure, a method of defining a protuberant region on a base material, the method comprising: positioning a protuberant element on the base material, forming a contact structure to cover some portion of the protuberant element and to cover some portion of the base material.
1 13. The method of claim 1 12 further comprising removing the base material after the contact structure is formed.
1 14. The method of claim 1 12 further comprising removing the protuberant element after the contact structure is formed.
1 15. The method of claim 1 12 wherein the base material is a masking material which can be patterned lithographically.
1 16. The method of claim 1 12 further comprising an electronic component on which the base material is secured.
117. The method of claim 1 12 further comprising securing the contact structure relative to the electronic component.
1 18. The method of claim 1 12 further comprising forming the contact structure by applying a seed layer to cover some portion of the protuberant element and to cover some portion of the base material, then forming a bulk material conforming to the position of the seed layer.
1 19. In a lithographically defined contact structure, a product comprising a base component and a protuberant region on the base component.
120. The product of claim 119 further comprising an electronic component, the base component secured relative to the electronic component and electrically connected to the electronic component.
121. The product of claim 120 wherein the protuberant region is a contact area extending away from the base component and extending away from the electronic component.
PCT/US1998/009999 1997-05-15 1998-05-14 Lithographically defined microelectronic contact structures WO1998052224A1 (en)

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EP98922344A EP0985231A1 (en) 1997-05-15 1998-05-14 Lithographically defined microelectronic contact structures
KR1020047003178A KR100577131B1 (en) 1997-05-15 1998-05-14 Microelectronic contact structure and the production and use method thereof
KR1019997010532A KR100577132B1 (en) 1997-05-15 1998-05-14 Microelectronic contact structure and the production and use method thereof
JP54959498A JP3378259B2 (en) 1997-05-15 1998-05-14 How to create a contact structure
AU74915/98A AU7491598A (en) 1997-05-15 1998-05-14 Lithographically defined microelectronic contact structures

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PCT/US1997/008634 WO1997043654A1 (en) 1996-05-17 1997-05-15 Microelectronic spring contact elements
USPCT/US97/08634 1997-05-15
US7367998P 1998-02-04 1998-02-04
US60/073,679 1998-02-04
US3247398A 1998-02-26 1998-02-26
US09/032,473 1998-02-26

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Cited By (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000033089A2 (en) * 1998-12-02 2000-06-08 Formfactor, Inc. Lithographic contact elements
WO2001009952A2 (en) * 1999-07-30 2001-02-08 Formfactor, Inc. Interconnect assemblies and methods
US6255126B1 (en) 1998-12-02 2001-07-03 Formfactor, Inc. Lithographic contact elements
WO2001048870A2 (en) * 1999-12-28 2001-07-05 Formfactor, Inc. Interconnect for microelectronic structures with enhanced spring characteristics
WO2001048818A1 (en) * 1999-12-29 2001-07-05 Formfactor, Inc. Resilient interconnect structure for electronic components and method for making the same
WO2001080315A2 (en) * 2000-04-12 2001-10-25 Formfactor, Inc. Shaped springs and methods of fabricating and using shaped springs
WO2002063682A2 (en) * 2000-11-09 2002-08-15 Formfactor, Inc. Lithographic type microelectronic spring structures with improved contours
US6441315B1 (en) 1998-11-10 2002-08-27 Formfactor, Inc. Contact structures with blades having a wiping motion
US6448865B1 (en) 1999-02-25 2002-09-10 Formfactor, Inc. Integrated circuit interconnect system
US6459343B1 (en) 1999-02-25 2002-10-01 Formfactor, Inc. Integrated circuit interconnect system forming a multi-pole filter
US6491968B1 (en) 1998-12-02 2002-12-10 Formfactor, Inc. Methods for making spring interconnect structures
US6501343B2 (en) 1999-02-25 2002-12-31 Formfactor, Inc. Integrated circuit tester with high bandwidth probe assembly
US6520778B1 (en) 1997-02-18 2003-02-18 Formfactor, Inc. Microelectronic contact structures, and methods of making same
EP1327605A2 (en) * 2002-01-10 2003-07-16 Infineon Technologies AG Process for forming a structure on a wafer
US6606014B2 (en) 1999-02-25 2003-08-12 Formfactor, Inc. Filter structures for integrated circuit interfaces
WO2003066515A2 (en) * 2002-02-08 2003-08-14 Microsaic Systems Limited Microengineered electrical connectors
US6616966B2 (en) 1998-12-02 2003-09-09 Formfactor, Inc. Method of making lithographic contact springs
US6640432B1 (en) 2000-04-12 2003-11-04 Formfactor, Inc. Method of fabricating shaped springs
US6672875B1 (en) 1998-12-02 2004-01-06 Formfactor, Inc. Spring interconnect structures
US6713374B2 (en) 1999-07-30 2004-03-30 Formfactor, Inc. Interconnect assemblies and methods
US6729019B2 (en) 2001-07-11 2004-05-04 Formfactor, Inc. Method of manufacturing a probe card
US6780001B2 (en) 1999-07-30 2004-08-24 Formfactor, Inc. Forming tool for forming a contoured microelectronic spring mold
US6807734B2 (en) 1998-02-13 2004-10-26 Formfactor, Inc. Microelectronic contact structures, and methods of making same
US6888362B2 (en) 2000-11-09 2005-05-03 Formfactor, Inc. Test head assembly for electronic components with plurality of contoured microelectronic spring contacts
US6891385B2 (en) 2001-12-27 2005-05-10 Formfactor, Inc. Probe card cooling assembly with direct cooling of active electronic components
US6939474B2 (en) * 1999-07-30 2005-09-06 Formfactor, Inc. Method for forming microelectronic spring structures on a substrate
US7047638B2 (en) 2002-07-24 2006-05-23 Formfactor, Inc Method of making microelectronic spring contact array
US7064953B2 (en) 2001-12-27 2006-06-20 Formfactor, Inc. Electronic package with direct cooling of active electronic components
US7063541B2 (en) 1997-03-17 2006-06-20 Formfactor, Inc. Composite microelectronic spring structure and method for making same
US7168160B2 (en) 2001-12-21 2007-01-30 Formfactor, Inc. Method for mounting and heating a plurality of microelectronic components
US7189077B1 (en) 1999-07-30 2007-03-13 Formfactor, Inc. Lithographic type microelectronic spring structures with improved contours
US7196531B2 (en) 2001-07-11 2007-03-27 Formfactor, Inc. Method of manufacturing a probe card
WO2008021227A2 (en) * 2006-08-15 2008-02-21 Qualcomm Mems Technologies, Inc. High profile contacts for microelectromechanical systems
EP1940213A2 (en) 2001-12-27 2008-07-02 FormFactor, Inc. Cooling assembly with direct cooling of active electronic components
US7402460B1 (en) 1999-10-08 2008-07-22 Andreas Plettner Method for production of contactless chip cards and for production of electrical units comprising chips with contact elements
US7458816B1 (en) 2000-04-12 2008-12-02 Formfactor, Inc. Shaped spring
US7497694B2 (en) 2005-12-09 2009-03-03 Ibiden Co., Ltd. Printed board with a pin for mounting a component
US7528618B2 (en) 2006-05-02 2009-05-05 Formfactor, Inc. Extended probe tips
WO2009157957A1 (en) * 2008-06-26 2009-12-30 Marcoux Phil P Semiconductor with top-side wrap-around flange contact
US7674112B2 (en) 2006-12-28 2010-03-09 Formfactor, Inc. Resilient contact element and methods of fabrication
US7684106B2 (en) 2006-11-02 2010-03-23 Qualcomm Mems Technologies, Inc. Compatible MEMS switch architecture
US7773388B2 (en) 2005-12-09 2010-08-10 Ibiden Co., Ltd. Printed wiring board with component mounting pin and electronic device using the same
US7858512B2 (en) 2008-06-26 2010-12-28 Wafer-Level Packaging Portfolio Llc Semiconductor with bottom-side wrap-around flange contact
US8409461B2 (en) 2005-12-09 2013-04-02 Ibiden Co., Ltd. Method of manufacturing printed wiring board with component mounting pin
US8964280B2 (en) 2006-06-30 2015-02-24 Qualcomm Mems Technologies, Inc. Method of manufacturing MEMS devices providing air gap control
US8963159B2 (en) 2011-04-04 2015-02-24 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
US9134527B2 (en) 2011-04-04 2015-09-15 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
ITUB20160027A1 (en) * 2016-02-01 2017-08-01 St Microelectronics Srl PROCEDURE FOR PRODUCING SEMICONDUCTOR AND CORRESPONDING DEVICES
US10566283B2 (en) 2017-07-28 2020-02-18 Stmicroelectronics S.R.L. Semiconductor device and a corresponding method of manufacturing semiconductor devices
US10593625B2 (en) 2017-07-28 2020-03-17 Stmicroelectronics S.R.L. Semiconductor device and a corresponding method of manufacturing semiconductor devices
US10790226B2 (en) 2017-07-28 2020-09-29 Stmicroelectronics S.R.L. Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation
US11469194B2 (en) 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002286758A (en) * 2001-03-28 2002-10-03 Yamaha Corp Probe unit and its manufacturing method
WO2004015432A1 (en) * 2002-07-15 2004-02-19 Formfactor, Inc. Fiducial alignment marks on microelectronic spring contacts
CN100555752C (en) * 2005-09-16 2009-10-28 鸿富锦精密工业(深圳)有限公司 Arrangement for resilient contacting and use the electronic equipment of this arrangement for resilient contacting
US7534652B2 (en) * 2005-12-27 2009-05-19 Tessera, Inc. Microelectronic elements with compliant terminal mountings and methods for making the same
ITMI20060478A1 (en) * 2006-03-16 2007-09-17 Eles Semiconductor Equipment Spa SYSTEM FOR CONTACTING ELECTRONIC DEVICES AND ITS PRODUCTION METHOD BASED ON WIRED CONDUCTOR IN INSULATING MATERIAL
JP2008292500A (en) * 2008-07-17 2008-12-04 Yamaichi Electronics Co Ltd Probe unit and method for manufacturing the same
JP5673181B2 (en) * 2011-02-15 2015-02-18 トヨタ自動車株式会社 Semiconductor device
TWI811053B (en) * 2022-08-04 2023-08-01 矽品精密工業股份有限公司 Carrier structure

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH661129A5 (en) * 1982-10-21 1987-06-30 Feinmetall Gmbh CONTACT DEVICE.
US5172050A (en) * 1991-02-15 1992-12-15 Motorola, Inc. Micromachined semiconductor probe card
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits
US5391521A (en) * 1992-12-30 1995-02-21 Hyundai Electronics Industries Co., Ltd. Method for fabricating low resistance contacts of semiconductor device
US5476211A (en) * 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
WO1996002068A1 (en) * 1994-07-07 1996-01-25 Tessera, Inc. Microelectronic mounting with multiple lead deformation
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH661129A5 (en) * 1982-10-21 1987-06-30 Feinmetall Gmbh CONTACT DEVICE.
US5172050A (en) * 1991-02-15 1992-12-15 Motorola, Inc. Micromachined semiconductor probe card
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits
US5391521A (en) * 1992-12-30 1995-02-21 Hyundai Electronics Industries Co., Ltd. Method for fabricating low resistance contacts of semiconductor device
US5476211A (en) * 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
WO1996002068A1 (en) * 1994-07-07 1996-01-25 Tessera, Inc. Microelectronic mounting with multiple lead deformation
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"ROBUST METHOD USING SIMPLE UNIT PROCESSES FOR THIN FILM CU-POLYIMIDE PACKAGING STRUCTURES", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 34, no. 10A, 1 March 1992 (1992-03-01), pages 368 - 369, XP000302335 *
"THIN FILM SUBSTRATE FOR WIRE BONDING", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 32, no. 10A, 1 March 1990 (1990-03-01), pages 80/81, XP000083170 *
KONG L C ET AL: "INTEGRATED ELECTROSTATICALLY RESONANT SCAN TIP FOR AN ATOMIC FORCE MICROSCOPE", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, vol. 11, no. 3, 1 May 1993 (1993-05-01), pages 634 - 641, XP000383159 *
O. R. ABOLAFIA: "Tapered Vias in a Photosensitive Dielectric Film", IBM TDB, vol. 21, no. 12, 31 May 1979 (1979-05-31), pages 4787, XP002071051 *

Cited By (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6520778B1 (en) 1997-02-18 2003-02-18 Formfactor, Inc. Microelectronic contact structures, and methods of making same
US7063541B2 (en) 1997-03-17 2006-06-20 Formfactor, Inc. Composite microelectronic spring structure and method for making same
US6807734B2 (en) 1998-02-13 2004-10-26 Formfactor, Inc. Microelectronic contact structures, and methods of making same
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US6825422B2 (en) 1998-11-10 2004-11-30 Formfactor, Inc. Interconnection element with contact blade
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US6441315B1 (en) 1998-11-10 2002-08-27 Formfactor, Inc. Contact structures with blades having a wiping motion
US7553165B2 (en) 1998-12-02 2009-06-30 Formfactor, Inc. Spring interconnect structures
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US6606014B2 (en) 1999-02-25 2003-08-12 Formfactor, Inc. Filter structures for integrated circuit interfaces
US6501343B2 (en) 1999-02-25 2002-12-31 Formfactor, Inc. Integrated circuit tester with high bandwidth probe assembly
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US6448865B1 (en) 1999-02-25 2002-09-10 Formfactor, Inc. Integrated circuit interconnect system
US6939474B2 (en) * 1999-07-30 2005-09-06 Formfactor, Inc. Method for forming microelectronic spring structures on a substrate
US7189077B1 (en) 1999-07-30 2007-03-13 Formfactor, Inc. Lithographic type microelectronic spring structures with improved contours
WO2001009952A3 (en) * 1999-07-30 2001-11-15 Formfactor Inc Interconnect assemblies and methods
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US6780001B2 (en) 1999-07-30 2004-08-24 Formfactor, Inc. Forming tool for forming a contoured microelectronic spring mold
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US7402460B1 (en) 1999-10-08 2008-07-22 Andreas Plettner Method for production of contactless chip cards and for production of electrical units comprising chips with contact elements
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US7325302B2 (en) 1999-12-28 2008-02-05 Formfactor, Inc. Method of forming an interconnection element
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US7048548B2 (en) 1999-12-28 2006-05-23 Formfactor, Inc. Interconnect for microelectronic structures with enhanced spring characteristics
WO2001048818A1 (en) * 1999-12-29 2001-07-05 Formfactor, Inc. Resilient interconnect structure for electronic components and method for making the same
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US7458816B1 (en) 2000-04-12 2008-12-02 Formfactor, Inc. Shaped spring
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WO2002063682A2 (en) * 2000-11-09 2002-08-15 Formfactor, Inc. Lithographic type microelectronic spring structures with improved contours
US7245137B2 (en) 2000-11-09 2007-07-17 Formfactor, Inc. Test head assembly having paired contact structures
US6888362B2 (en) 2000-11-09 2005-05-03 Formfactor, Inc. Test head assembly for electronic components with plurality of contoured microelectronic spring contacts
WO2002063682A3 (en) * 2000-11-09 2003-12-31 Formfactor Inc Lithographic type microelectronic spring structures with improved contours
US7168162B2 (en) 2001-07-11 2007-01-30 Formfactor, Inc. Method of manufacturing a probe card
US6864105B2 (en) 2001-07-11 2005-03-08 Formfactor, Inc. Method of manufacturing a probe card
US7196531B2 (en) 2001-07-11 2007-03-27 Formfactor, Inc. Method of manufacturing a probe card
US7400157B2 (en) 2001-07-11 2008-07-15 Formfactor, Inc. Composite wiring structure having a wiring block and an insulating layer with electrical connections to probes
US6729019B2 (en) 2001-07-11 2004-05-04 Formfactor, Inc. Method of manufacturing a probe card
US7168160B2 (en) 2001-12-21 2007-01-30 Formfactor, Inc. Method for mounting and heating a plurality of microelectronic components
US7064953B2 (en) 2001-12-27 2006-06-20 Formfactor, Inc. Electronic package with direct cooling of active electronic components
US7863915B2 (en) 2001-12-27 2011-01-04 Formfactor, Inc. Probe card cooling assembly with direct cooling of active electronic components
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US7768777B2 (en) 2001-12-27 2010-08-03 Formfactor, Inc. Electronic package with direct cooling of active electronic components
US7433188B2 (en) 2001-12-27 2008-10-07 Formfactor, Inc. Electronic package with direct cooling of active electronic components
US7579847B2 (en) 2001-12-27 2009-08-25 Formfactor, Inc. Probe card cooling assembly with direct cooling of active electronic components
US6891385B2 (en) 2001-12-27 2005-05-10 Formfactor, Inc. Probe card cooling assembly with direct cooling of active electronic components
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WO2003066515A3 (en) * 2002-02-08 2003-12-24 Microsaic Systems Ltd Microengineered electrical connectors
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US7047638B2 (en) 2002-07-24 2006-05-23 Formfactor, Inc Method of making microelectronic spring contact array
US7497694B2 (en) 2005-12-09 2009-03-03 Ibiden Co., Ltd. Printed board with a pin for mounting a component
US8409461B2 (en) 2005-12-09 2013-04-02 Ibiden Co., Ltd. Method of manufacturing printed wiring board with component mounting pin
US7891089B2 (en) 2005-12-09 2011-02-22 Ibiden Co., Ltd. Printed board with component mounting pin
US7731504B2 (en) 2005-12-09 2010-06-08 Ibiden Co., Ltd. Printed board with component mounting pin
US7773388B2 (en) 2005-12-09 2010-08-10 Ibiden Co., Ltd. Printed wiring board with component mounting pin and electronic device using the same
US7528618B2 (en) 2006-05-02 2009-05-05 Formfactor, Inc. Extended probe tips
US8964280B2 (en) 2006-06-30 2015-02-24 Qualcomm Mems Technologies, Inc. Method of manufacturing MEMS devices providing air gap control
WO2008021227A3 (en) * 2006-08-15 2008-06-12 Qualcomm Mems Technologies Inc High profile contacts for microelectromechanical systems
WO2008021227A2 (en) * 2006-08-15 2008-02-21 Qualcomm Mems Technologies, Inc. High profile contacts for microelectromechanical systems
US7684106B2 (en) 2006-11-02 2010-03-23 Qualcomm Mems Technologies, Inc. Compatible MEMS switch architecture
US7674112B2 (en) 2006-12-28 2010-03-09 Formfactor, Inc. Resilient contact element and methods of fabrication
WO2009157957A1 (en) * 2008-06-26 2009-12-30 Marcoux Phil P Semiconductor with top-side wrap-around flange contact
US7858512B2 (en) 2008-06-26 2010-12-28 Wafer-Level Packaging Portfolio Llc Semiconductor with bottom-side wrap-around flange contact
US9134527B2 (en) 2011-04-04 2015-09-15 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
US8963159B2 (en) 2011-04-04 2015-02-24 Qualcomm Mems Technologies, Inc. Pixel via and methods of forming the same
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US10483220B2 (en) 2016-02-01 2019-11-19 Stimicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding device
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US11469194B2 (en) 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
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JP3378259B2 (en) 2003-02-17
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KR20040034685A (en) 2004-04-28
KR100577131B1 (en) 2006-05-10
KR20010012575A (en) 2001-02-15
AU7491598A (en) 1998-12-08
JP2002231718A (en) 2002-08-16
JP2003031289A (en) 2003-01-31

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