CN214797334U - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN214797334U
CN214797334U CN202022877683.2U CN202022877683U CN214797334U CN 214797334 U CN214797334 U CN 214797334U CN 202022877683 U CN202022877683 U CN 202022877683U CN 214797334 U CN214797334 U CN 214797334U
Authority
CN
China
Prior art keywords
die
plastic
mounting location
metal
die mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202022877683.2U
Other languages
English (en)
Inventor
F·G·齐格利奥利
A·平图斯
P·马格尼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of CN214797334U publication Critical patent/CN214797334U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49506—Lead-frames or other flat leads characterised by the die pad an insulative substrate being used as a diepad, e.g. ceramic, plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85455—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85464—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本公开的各实施例涉及半导体器件。半导体器件，包括：塑料衬底，被图案化为具有引线框架的形状，引线框架包括塑料裸片安装位置和多个塑料引线；经激活的激光直接成型材料的金属迹线，在多个塑料引线的所选择的区域处；在金属迹线上的镀覆件，以提供导电路径；以及半导体裸片，被附接在裸片安装位置处；电键合件，在半导体裸片和导电路径中的所选择的导电路径之间；以及封装材料，被模制到附接于裸片安装位置上的半导体裸片上和经图案化的塑料衬底上。利用本公开的实施例有利地用较便宜的塑料引线框架代替金属引线框架，这提供了改进的布线灵活性来简化封装的主体内部的接线键合，并且提供了对集成电路的低成本封装。

Description

半导体器件
技术领域
本公开涉及半导体器件。
背景技术
当前有各种技术可用于制造诸如集成电路的半导体器件。
该技术领域中的期望特征可以包括降低的组装成本、利用定制的衬底代替引线框架的可能性、衬底制造中的高灵活性、针对多个裸片的模块化配置以及可以免除接线键合的能力。
本领域需要沿着前面讨论的路线做出进一步的改进。
实用新型内容
本公开至少实现了上述期望特征中的一些特征。
根据本公开的方面，提供了一种半导体器件，包括：塑料衬底，被图案化为具有引线框架的形状，引线框架包括塑料裸片安装位置和多个塑料引线；经激活的激光直接成型材料的金属迹线，在多个塑料引线的所选择的区域处；在金属迹线上的镀覆件，以提供导电路径；以及半导体裸片，被附接在裸片安装位置处；电键合件，在半导体裸片和导电路径中的所选择的导电路径之间；以及封装材料，被模制到附接于裸片安装位置上的半导体裸片上和经图案化的塑料衬底上。
在一些实施例中，半导体器件还包括在裸片安装位置处的至少一个金属区域，其中半导体裸片被附接到至少一个金属区域。
在一些实施例中，至少一个金属区域包括：第一金属区域，在裸片安装位置处的经图案化的塑料衬底的后表面上；第二金属区域，在裸片安装位置处的经图案化的塑料衬底的前表面上；以及热过孔，延伸穿过裸片安装位置，以将第一金属区域热耦合到第二金属区域。
在一些实施例中，至少一个金属区域包括：在裸片安装位置处的经图案化的塑料衬底的后表面上的金属区域；在裸片安装位置处的经图案的塑料衬底中的开口，开口暴露金属区域；并且其中半导体裸片被附接到所暴露的金属区域上。
在一些实施例中，塑料衬底的厚度在80μm至150μm的范围内。
在一些实施例中，金属迹线的厚度在50μm至150μm的范围内。
在一些实施例中，多个塑料引线的一部分从经模制的封装材料的外围边缘向外延伸，并且其中导电路径的一部分存在于多个塑料引线的一部分上。
利用本公开的实施例有利地用较便宜的塑料引线框架代替金属引线框架，这提供了改进的布线灵活性来简化封装的主体内部的接线键合，并且提供了对集成电路的低成本封装。
附图说明
现在将参考附图，仅通过示例的方式描述一个或多个实施例，其中：
图1是根据实施例的半导体器件的截面图，
图2A至图6B是根据实施例的可能制造步骤的示例，
图7是示例性实施例的半导体器件的某些元件的平面图，
图8是示例性实施例的半导体器件的某些元件的截面图，以及
图9A至图9D是根据实施例的可能制造步骤的示例。
具体实施方式
一个或多个实施例可以涉及一种方法。
一个或多个实施例可以涉及一种对应的半导体器件(例如，集成电路)。
一个或多个实施例可以提供一种制造诸如集成电路的半导体器件的方法，方法包括提供引线框架，该引线框架具有包括塑料材料的芯或衬底，并且具有在引线区域处的选择性表面金属件(metallization)。
一个或多个实施例可以包括在引线框架的塑料芯或衬底中提供适于激光直接成型(LDS)的塑料材料。
因此，一个或多个实施例可以有助于用较便宜的塑料引线框架代替金属引线框架，这提供了改进的布线灵活性来简化封装的主体内部的接线键合，并且提供了对集成电路的低成本封装。
在随后的描述中，说明了一个或多个具体细节，旨在提供对本描述的实施例的示例的深入理解。可以在没有一个或多个特定细节的情况下，或在其他方法、组件、材料等的情况下获得实施例。在其他情况下，未详细示出或描述已知的结构、材料或操作，因此实施例的某些方面将不要被遮盖。
在本描述的框架中对“一实施例”或“一个实施例”的引用旨在指示相对于该实施例描述的特定配置、结构或特性被包括在至少一个实施例中。因此，可以在本描述的一个或多个点中出现的诸如“在一实施例中”或“在一个实施例中”的短语不一定指代同一个实施例。此外，在一个或多个实施例中，可以以任何适当的方式来组合特定的构造、结构或特性。
贯穿本文所附的附图，相同的部件或元件用相同的附图标记/数字指示，并且为了简洁起见将不再重复对应的描述。
应当理解，为了清楚和易于表示，各种附图可以未按比例绘制并且可以未全部按相同比例绘制。
本文使用的附图标记仅出于方便起见而被提供，并且因此不限定保护的程度或实施例的范围。
激光直接成型(LDS)是一种基于激光的加工技术，目前被广泛用于工业和消费电子市场的各个领域，例如用于高性能天线集成，其中天线设计可以被直接形成在经模制的塑料部件上。
在一个示例性过程中，可以用可商购获得的树脂来制造经模制的部件，该树脂包括适于LDS过程的添加剂。对于该目的，宽泛范围的树脂目前可用，诸如聚合物树脂，如聚碳酸酯(PC)、聚碳酸酯/丙烯腈丁二烯苯乙烯(PC/ABS)、ABS、液晶聚合物(LCP)。
在LDS中，可以使用激光束将所需的导电图案转移到塑料材料上，然后对塑料材料进行金属化(例如，经由利用铜或其他金属进行无电镀 (electroless plating))来最终完成所需的导电图案。无电镀之后可以跟随有铜或其他金属的电解沉积，例如，以将导电图案的厚度增加到某个 (例如，限定的)值。
本文所例示的一个或多个实施例是基于以下认识：LDS有助于在塑料(模制)化合物中提供导电结构，诸如过孔和线，而无需附加的制造步骤并且在可以获得的形状方面具有高灵活性。
一个或多个实施例可以有助于提供包括具有塑料材料的引线框架的半导体器件。
当前，使用名称“引线框架(leadframe)”(或“引线框(lead frame)”) (例如，参见美国专利商标局USPC术语的合并词汇表)来指示为集成电路芯片或裸片提供支持以及电引线的金属框架，以将裸片或芯片中的集成电路互连到其他电子组件或接触。
本质上，引线框架包括导电结构(引线)的阵列，导电结构(引线) 从轮廓位置在半导体芯片或裸片的方向上向内延伸，从而从裸片焊垫形成导电结构的阵列，裸片焊垫被配置成使至少一个半导体芯片或裸片附接在其上。
图1是根据一个或多个实施例的集成电路10的截面图。集成电路 10包括塑料(例如，聚合物)材料的箔100，箔100提供引线框架12 的芯或衬底。塑料材料可以包括适于LDS处理的材料，诸如液晶聚合物 (LCP)、聚四氟乙烯(PTFE)或热固性树脂(环氧甲酚新戊酸酯-ECN、联苯、二环戊二烯-DCP、多芳烃)。
引线框架12的(例如，中心)部分102可以被配置作为裸片焊垫位置，以容纳经由裸片附接材料106(例如，包含银(Ag)的环氧胶或包含银的膜)被附接在引线框架12上的一个或多个裸片104。
通过在塑料箔100的所选择的部分上形成(例如，镀覆(例如，经由无电镀，可能跟随有电解沉积))金属层108a、108b，在塑料箔100 上提供导电结构(即，引线框架12的引线)。例如，金属层108a可以形成在箔100的前(例如，上)表面(的一部分)上，和/或金属层108b 可以形成在箔100的后(例如，下)表面(的一部分)上。
金属层108a和/或108b可以包括选自铜(Cu)、银(Ag)、铝(Al)、镍(Ni)、钯(Pd)、金(Au)中的至少一种金属。
裸片104可以通过键合线(或任何其他类型的互连，例如铜凸块或焊料凸块)电耦合到引线框架12的引线，该键合线将被提供在裸片104 的前表面104a上的裸片焊垫耦合到被提供在例如金属层108a中的导电结构。
集成电路10还可以包括封装110，封装110包括例如模制化合物(诸如，环氧树脂模制化合物(EMC))，其封装裸片104、键合线和引线框架12的一部分。塑料箔100的、具有金属层108a和/或108b的部分从封装110的外围侧横向地向外延伸(即，在外部)，以形成外部引线。
在一个或多个实施例中，塑料箔100的厚度可以在大约80μm至 150μm的范围内。
在一个或多个实施例中，金属层108a、108b的厚度可以在大约50μm 至150μm的范围内。
对于薄四方扁平封装(TQFP)，金属层108a、108b的厚度可以在大约5密耳至6密耳的范围内(1密耳＝0.001英寸＝25.4μm)。
可以选择塑料箔100和/或金属层108a、108b的厚度，以有助于集成电路10的正确形成。
图2A至图6B是一个或多个实施例中可能的制造步骤的示例。特别地，以字母“A”指定的图是根据实施例的后续制造步骤的示例性(俯视)平面图，并且以字母“B”指定的图是相应的截面侧视图。
如在图2A(俯视图)和图2B(侧视图)中例示的，可以提供(平面)塑料箔100作为塑料引线框架12的芯或衬底。塑料箔100可以被成形(例如，通过冲压(stamping)或冲孔(punching))成“引线框架状”结构，该结构具有提供裸片安装位置102的中心部分，其中多个引线形状的部分远离每个中心部分延伸，其中所述引线形状的部分彼此间隔开。塑料箔100可以包括适于LDS处理的材料。
如集成电路制造中常规的，在制造流程的早期步骤中，引线框架12 可以包括用于相应多个裸片104的多个安装位置102。可以通过沿着图 2A中指示的锯线200进行锯切或切割，将器件分离(在模制材料的模制之前或之后)。
为了清楚和便于说明，下面的图3A至图6B仅参考两个相邻的安装位置102(即，引线框架12的有限部分，诸如在图2A和图2B中例示的部分202)图示了根据实施例的制造方法的另外的步骤。
如图3A(俯视图)和图3B(侧视图)中所例示的，可以通过在引线框架12的引线区域300上扫描激光辐射来选择性地激活塑料箔100 的LDS可激活材料。在箔100的前侧和/或后侧上扫描激光辐射，从而分别提供与引线区域300相对应的经激光激活的区域100a和/或100b。经激光激活的区域100a和/或100b可以在深度上延伸从箔100的表面起大约5μm至10μm的厚度。
一旦塑料引线框架12的所选择的区域300已经被激光激活，则所选择的区域300可以被覆盖如图4A(俯视图)和图4B(侧视图)中所例示的金属层(例如，通过无电镀)，以提供金属层108a和/或108b。
备选地，经激光激活的区域100a、100b可以提供足够的导电性并且可以不涉及表面金属化108a、108b。
备选地，箔100的塑料材料可以不包括LDS可激活材料。在这种情况下，可以跳过图3A、图3B中例示的制造步骤，并且可以借助于标准掩模技术(例如，物理掩模或光刻胶)在箔100的引线区域300处选择性地形成金属层108a和/或108b。
将理解，在一个或多个实施例中，塑料箔100可以不被冲压或冲孔来提供物理上分离的引线区域300，只要可以通过适当地选择塑料箔100 的要被激光激活和/或被金属覆盖的区域，将引线彼此电绝缘即可。
一旦在引线区域300上形成了金属层108a和/或108b，集成电路10 的制造流程就可以包括常规步骤，诸如将裸片104附接在相应的裸片安装位置102处(例如，借助于软焊料附接材料)，并且将裸片104的裸片焊垫接线到被提供在塑料引线框架12上的相应引线(例如，金属结构 108a)，如图5A(俯视图)和图5B(侧视图)中所例示的。
如在图6A(俯视图)和图6B(侧视图)中所例示的，可以在器件 10的分离步骤(例如，沿线200锯切)之前或之后，提供模制化合物110 (例如，环氧树脂模制化合物EMC)来封装被附接到引线框架12的裸片104。
在一个或多个实施例中，在模制封装110之后，引线框架12可以进一步被金属(例如，锡)的附加层镀覆、修整和形成(具有在本文所附附图中不可见的这种步骤)。
在如图7中例示的一个或多个实施例中，可以选择引线区域300，以便例如通过减小(例如，最小化)将裸片焊垫耦合到引线的键合线的长度，来减小接线键合的复杂度，这种改进被用于图案化引线区域300 的LDS技术(或在变型实施例中，掩模技术)的灵活性促进。
在如图8中例示的一个或多个实施例中，金属层108a、108b也可以被提供在裸片焊垫区域(或安装位置102)处，例如通过在图3A和图 3B中例示的激光激活步骤期间激光激活那些区域。被提供在安装位置 102处的上金属层108a和下金属层108b可以通过制造一个或多个热过孔112而被热耦合，一个或多个热过孔112延伸穿过塑料箔100的厚度，这种热过孔可以通过激光直接成型来制造。
备选地，如图9A至图9D中所例示的，在安装位置102处的塑料箔 100可以选择性地被移除，以在操作期间改善从裸片104的散热。例如，根据实施例的方法可以包括：
-在引线区域300处和安装位置102处的塑料箔100的后侧上形成金属层108b(图9A)，
-选择性地移除在安装位置102处的塑料箔100，从而使金属裸片焊垫102’暴露(图9B)，
-在引线区域300处的塑料箔100的前(例如，上)侧和金属裸片焊垫102’的前(例如，上)侧上形成金属层108a(图9C)，以及
-将裸片104附接在金属裸片焊垫102’处(图9D)。
因此，一个或多个实施例可以提供以下优点中的一个或多个优点：
-利用较便宜的塑料引线框架代替金属引线框架的可能性，
-提供布线的高灵活性，以简化封装110的主体内部的接线键合，以及
-为大批量运行的小尺寸集成电路(SOIC)旧设备提供低成本封装。
如本文所例示的，一种制造半导体器件(例如，10)的方法可以包括：
-提供具有至少一个用于半导体裸片(例如104)的裸片安装位置(例如102)的塑料材料衬底(例如100)，
-在上述塑料材料衬底的所选择的区域(例如300)上形成(例如镀覆)金属迹线(例如108a、108b)，其中上述金属迹线提供用于耦合到所述半导体裸片的导电路径(例如，线路)，
-将上述半导体裸片附接到上述至少一个裸片安装位置上，
-将被附接在上述至少一个裸片安装位置上的上述半导体裸片键合到形成在塑料材料衬底上的上述金属迹线中的所选择的金属迹线，
-将封装材料(例如110)模制到被附接到上述至少一个裸片安装位置上的上述半导体裸片上。
如本文所例示的，所述塑料材料衬底可以包括激光直接成型材料，并且在所述塑料材料衬底的选择区域上形成金属迹线可以包括激光激活所述激光直接成型材料。
如本文所例示的，方法可以包括：在上述塑料材料衬底的所述选择区域处向所述激光直接成型材料施加激光辐射能量，以提供所述塑料材料衬底的激活区域，以及将导电材料镀覆(例如，通过无电镀)到所述塑料材料衬底的所述激活区域上。
如本文所例示的，方法可以包括：通过在所述塑料材料衬底上施加掩模层，而在所述塑料材料衬底的所述选择区域上选择性地形成所述金属迹线。
如本文所例示的，方法可以包括：在上述选择区域的由上述封装材料暴露的部分上提供(例如镀覆)另外的金属层，其中上述另外的金属层优选地包括锡。
如本文所例示的，方法可以包括：在将上述相应的至少一个半导体裸片附接到上述至少一个裸片安装位置上之前，在上述塑料材料衬底的上述至少一个裸片安装位置处形成(例如，镀覆)金属区域(例如，108a、 108b)。
如本文所例示的，方法可以包括：
-在上述至少一个裸片安装位置处的上述塑料材料衬底的后(例如，下)表面上形成第一金属区域(例如，108b)，
-在上述至少一个裸片安装位置处的上述塑料材料衬底的前(例如，上)表面上形成第二金属区域(例如，108a)，以及
-提供热过孔，该热过孔通过上述塑料材料衬底将上述第一金属区域和上述第二金属区域热耦合。
如本文所例示的，方法可以包括：在将上述相应的至少一个半导体裸片附接到上述至少一个裸片安装位置之前，选择性地移除在上述至少一个裸片安装位置处的上述塑料材料衬底。
如本文所例示的，方法可以包括：
-在上述至少一个裸片安装位置处的上述塑料材料衬底的后表面上形成第一金属区域，
-选择性地移除在上述至少一个安装位置处的上述塑料材料衬底，
-在上述至少一个裸片安装位置处的上述第一金属区域上形成第二金属区域，
-将上述至少一个半导体裸片附接到在上述相应的至少一个裸片安装位置处的上述第二金属区域上。
如本文所例示的，上述塑料材料衬底的厚度可以在80μm至150μm 的范围内。
如本文所例示的，上述金属迹线的厚度可以在50μm至150μm的范围内。
如本文所例示的，半导体器件可以包括：
-塑料材料衬底，具有用于相应的半导体裸片的裸片安装位置，
-金属迹线，形成在上述塑料材料衬底的所选择的区域上，其中上述金属迹线提供用于耦合到上述半导体裸片的导电路径，
-半导体裸片，经由裸片附接材料被附接到上述裸片安装位置上，该半导体裸片被键合到形成在塑料材料衬底上的上述金属迹线中的所选择的金属迹线，
-封装材料，被模制到被附接到上述裸片安装位置(102)上的上述半导体裸片上。
在不影响基本原理的情况下，细节和实施例可以相对于仅通过示例描述的内容变化，甚至显著变化，而不背离保护的范围。
权利要求是本文关于实施例提供的技术教导的组成部分。
保护范围由所附权利要求限定。

Claims (7)

1.一种半导体器件，其特征在于，包括：
塑料衬底，被图案化为具有引线框架的形状，所述引线框架包括塑料裸片安装位置和多个塑料引线；
经激活的激光直接成型材料的金属迹线，在所述多个塑料引线的所选择的区域处；
在所述金属迹线上的镀覆件，以提供导电路径；以及
半导体裸片，被附接在所述裸片安装位置处；
电键合件，在所述半导体裸片和所述导电路径中的所选择的导电路径之间；以及
封装材料，被模制到附接于所述裸片安装位置上的所述半导体裸片上和经图案化的所述塑料衬底上。
2.根据权利要求1所述的半导体器件，其特征在于，还包括在所述裸片安装位置处的至少一个金属区域，其中所述半导体裸片被附接到所述至少一个金属区域。
3.根据权利要求2所述的半导体器件，其特征在于，所述至少一个金属区域包括：
第一金属区域，在所述裸片安装位置处的经图案化的所述塑料衬底的后表面上；
第二金属区域，在所述裸片安装位置处的经图案化的所述塑料衬底的前表面上；以及
热过孔，延伸穿过所述裸片安装位置，以将所述第一金属区域热耦合到所述第二金属区域。
4.根据权利要求2所述的半导体器件，其特征在于，所述至少一个金属区域包括：
在所述裸片安装位置处的经图案化的所述塑料衬底的后表面上的金属区域；
在所述裸片安装位置处的经图案的所述塑料衬底中的开口，所述开口暴露所述金属区域；并且
其中所述半导体裸片被附接到所暴露的所述金属区域上。
5.根据权利要求1所述的半导体器件，其特征在于，所述塑料衬底的厚度在80μm至150μm的范围内。
6.根据权利要求1所述的半导体器件，其特征在于，所述金属迹线的厚度在50μm至150μm的范围内。
7.根据权利要求1所述的半导体器件，其特征在于，所述多个塑料引线的一部分从经模制的所述封装材料的外围边缘向外延伸，并且其中所述导电路径的一部分存在于所述多个塑料引线的所述一部分上。
CN202022877683.2U 2019-12-02 2020-12-02 半导体器件 Active CN214797334U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT102019000022632 2019-12-02
IT102019000022632A IT201900022632A1 (it) 2019-12-02 2019-12-02 Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente

Publications (1)

Publication Number Publication Date
CN214797334U true CN214797334U (zh) 2021-11-19

Family

ID=69811827

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202011399633.6A Pending CN112992687A (zh) 2019-12-02 2020-12-02 制造半导体器件的方法和对应的半导体器件
CN202022877683.2U Active CN214797334U (zh) 2019-12-02 2020-12-02 半导体器件

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202011399633.6A Pending CN112992687A (zh) 2019-12-02 2020-12-02 制造半导体器件的方法和对应的半导体器件

Country Status (4)

Country Link
US (2) US11417590B2 (zh)
EP (1) EP3832701A1 (zh)
CN (2) CN112992687A (zh)
IT (1) IT201900022632A1 (zh)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6544820B2 (en) * 1997-06-19 2003-04-08 Micron Technology, Inc. Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
JP4819471B2 (ja) * 2005-10-12 2011-11-24 日本電気株式会社 配線基板及び配線基板を用いた半導体装置並びにその製造方法
JP5286893B2 (ja) * 2007-04-27 2013-09-11 日立化成株式会社 接続端子、接続端子を用いた半導体パッケージ及び半導体パッケージの製造方法
TWI415293B (zh) * 2007-12-14 2013-11-11 Advanced Optoelectronic Tech 光電元件之製造方法及其封裝結構
CN102157510B (zh) * 2010-02-12 2013-11-06 亿光电子工业股份有限公司 近接传感器封装结构及其制作方法
US20190043794A1 (en) * 2017-08-03 2019-02-07 General Electric Company Electronics package including integrated structure with backside functionality and method of manufacturing thereof

Also Published As

Publication number Publication date
US20210167000A1 (en) 2021-06-03
EP3832701A1 (en) 2021-06-09
US11842954B2 (en) 2023-12-12
US11417590B2 (en) 2022-08-16
CN112992687A (zh) 2021-06-18
US20220392830A1 (en) 2022-12-08
IT201900022632A1 (it) 2021-06-02

Similar Documents

Publication Publication Date Title
CN213583700U (zh) 半导体器件
CN215220710U (zh) 半导体设备
EP1235272B1 (en) Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
US6291274B1 (en) Resin molded semiconductor device and method for manufacturing the same
US7772681B2 (en) Semiconductor die package and method for making the same
US7816187B2 (en) Method for fabricating semiconductor package free of substrate
US8487424B2 (en) Routable array metal integrated circuit package fabricated using partial etching process
US7410830B1 (en) Leadless plastic chip carrier and method of fabricating same
US20040089933A1 (en) Folded-flex bondwire-less multichip power package
CN114388375A (zh) 形成芯片封装体的方法和芯片封装体
CN116110807A (zh) 半导体器件的制造方法和对应的半导体器件
US7354796B2 (en) Method for fabricating semiconductor package free of substrate
CN214797334U (zh) 半导体器件
US10840172B2 (en) Leadframe, semiconductor package including a leadframe and method for forming a semiconductor package
CN217521997U (zh) 半导体器件
JP2001127228A (ja) ターミナルランドフレーム及びその製造方法、並びに樹脂封止型半導体装置及びその製造方法
CN103824820A (zh) 引线框区域阵列封装技术
US20220199477A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
US20230005803A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
US20230386980A1 (en) Method of manufacturing semiconductor devices and corresponding semiconductor device
KR100460048B1 (ko) 범프 칩 케리어 패키지 및 그의 제조방법
JP2002237559A (ja) 半導体装置の製造方法およびそれを用いた混成集積回路装置の製造方法
CN118738008A (zh) 混合四方扁平无引线qfn集成电路封装件
JP2001127196A (ja) ターミナルランドフレーム及びその製造方法、並びに樹脂封止型半導体装置及びその製造方法
JP2001127195A (ja) ターミナルランドフレーム及びその製造方法、並びに樹脂封止型半導体装置及びその製造方法

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant