CN103915405B - 半导体器件和制造半导体器件的方法 - Google Patents
半导体器件和制造半导体器件的方法 Download PDFInfo
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Abstract
本发明涉及半导体器件和制造半导体器件的方法。根据本发明的一个实施例,一种半导体器件具有衬底,该衬底具有第一表面和与第一表面相对的第二表面。而且,衬底具有第一孔。多条引线被置放在衬底的第一表面之上并且管芯焊盘被置放在第一孔中。另外地,封装剂被置放在管芯焊盘和该多条引线上。
Description
技术领域
本发明一般地涉及半导体封装,并且更加具体地涉及多芯片半导体封装及其组装。
背景技术
电子元件封装通常是半导体器件制造的最后阶段。封装可以使得能够在半导体芯片和另一个电气元件诸如印刷电路板(PCB)或者母板之间电互连。而且,封装可以针对破坏或者污染实际地保护芯片。另外地,封装可以针对可能妨碍芯片的化学品、湿气和/或气体保护芯片。此外,当芯片在操作中时,封装可以从芯片散热。
表面安装技术是用于将电子器件直接地安装到PCB的表面上的技术。表面安装器件可以在本体上具有各种型式的短的插脚或者引线、扁平触点、焊球矩阵诸如球栅阵列(BGA)或者末端。
一种类型的表面安装器件包括安装在金属支撑件或者引线框架上的半导体器件。半导体器件触点使用接合线电连接到引线框架。半导体器件的后侧也可以连接到引线框架。在将半导体器件连接到引线框架之后,系统利用模塑料封装。因为它们具有低制造成本和高可靠性,所以在封装半导体芯片中使用引线框架封装。
发明内容
根据本发明的一个实施例,一种半导体器件具有衬底,该衬底具有第一表面和与第一表面相对的第二表面。而且,衬底具有第一孔。多条引线被置放在衬底的第一表面之上并且管芯焊盘(die paddle)被置放在第一孔中。另外地,封装剂被置放在管芯焊盘和该多条引线上。
根据本发明的另一个实施例,一种半导体器件具有第一芯片支撑件,该第一芯片支撑件具有第一表面和与第一表面相对的第二表面。而且,第一芯片支撑件具有第一孔。半导体器件还具有联结到第一芯片支撑件并且置放在第一芯片支撑件的第一孔中的第二芯片支撑件。另外地,该半导体器件具有置放在第一芯片支撑件的第一表面上的多条引线。此外,该半导体器件具有联结到第一芯片支撑件的第一表面的第三芯片支撑件。
根据本发明的又一个实施例,一种制造半导体器件的方法包括提供带有联结的引线框架的衬底,其中该衬底具有第一表面、与第一表面相对的第二表面和孔。而且,引线框架具有置放在衬底的孔中的管芯焊盘和联结到衬底的第一表面的多条引线。另外地,该方法包括将第一芯片联结到衬底的第一表面和该多条引线中的第一引线。此外,该方法包括封装引线框架和第一芯片。
附图说明
为了更加完全地理解本发明及其优点,现在参考与附图结合进行的以下说明,其中:
图1a、1b和1c示意根据本发明的一个实施例的半导体封装,其中图1a示意顶视图,图1b示意截面视图,并且图1c示意后视图;
图2a、2b、2c和2d示意根据本发明的实施例使用的衬底,其中图2a示意顶视图,图2b和2d示意截面视图,并且图2c示意后视图;
图3a、3b和3c示意根据本发明的实施例使用的引线框架,其中图3a示意顶视图,图3b示意截面视图,并且图3c示意后视图;
图4a、4b和4c示意根据本发明的一个实施例联结到衬底的引线框架,其中图4a示意顶视图,图4b示意截面视图,并且图4c示意后视图;
图5a、5b和5c示意根据本发明的一个实施例在第一芯片联结到管芯焊盘之后在制造期间的半导体封装,其中图5a示意顶视图,图5b示意截面视图,并且图5c示意后视图;
图6a、6b和6c示意根据本发明的一个实施例在第二芯片联结到第一芯片之后在制造期间的半导体封装,其中图6a示意顶视图,图6b示意截面视图,并且图6c示意后视图;
图7a、7b和7c示意根据本发明的一个实施例在第三芯片联结到衬底和多条引线之后在制造期间的半导体封装,其中图7a示意顶视图,图7b示意截面视图,并且图7c示意后视图;
图8a、8b和8c示意根据本发明的一个实施例在第四芯片联结到衬底和多条引线之后在制造期间的半导体封装,其中图8a示意顶视图,图8b示意截面视图,并且图8c示意后视图;
图9a、9b和9c示意根据本发明的一个实施例在接合线被联结连接在第一芯片和多条引线之间之后在制造期间的半导体封装,其中图9a示意顶视图,图9b示意截面视图,并且图9c示意后视图;
图10a、10b和10c示意根据本发明的一个实施例在接合线被联结连接在第二芯片和多条引线之间之后在制造期间的半导体封装,其中图10a示意顶视图,图10b示意截面视图,并且图10c示意后视图;
图11a、11b和11c示意根据本发明的一个实施例在接合线被联结连接在第三芯片和多条引线之间之后在制造期间的半导体封装,其中图11a示意顶视图,图11b示意截面视图,并且图11c示意后视图;
图12a、12b和12c示意根据本发明的一个实施例在接合线被联结连接在第四芯片和多条引线之间之后在制造期间的半导体封装,其中图12a示意顶视图,图12b示意截面视图,并且图12c示意后视图;
图13a、13b和13c示意根据本发明的一个实施例在第五芯片联结到衬底和多条引线之后在制造期间的半导体封装,其中图13a示意顶视图,图13b示意截面视图,并且图13c示意后视图;
图14a、14b和14c示意根据本发明的一个实施例在热沉联结到衬底和第五芯片之后在制造期间的半导体封装,其中图14a示意顶视图,图14b示意截面视图,并且图14c示意后视图;
图15a、15b和15c示意根据本发明的一个实施例在模塑料在第五芯片和管芯焊盘之间并且在热沉和衬底之间形成之后在制造期间的半导体封装,其中图15a示意顶视图,图15b示意截面视图,并且图15c示意后视图;
图16a、16b和16c示意根据本发明的一个实施例分离的半导体封装,其中图16a示意顶视图,图16b示意截面视图,并且图16c示意后视图;
图17a、17b和17c示意根据本发明的一个实施例在多个焊球联结到衬底之后分离的半导体封装,其中图17a示意顶视图,图17b示意截面视图,并且图17c示意后视图;并且
图18a和18b示意根据本发明的其它实施例的半导体封装。
在不同的图中相应的数字和符号通常指代相应的部分,除非另有指示。图被绘制用于清楚地示意实施例的有关方面而并不是必要地按照比例绘制。
具体实施方式
在下面详细地讨论了目前优选的实施例的实现和使用。然而,应该理解,本发明提供很多能够在多种具体场合中体现的、可应用的创造性概念。将关于在一种具体场合中的实施例即一种制造半导体器件的方法描述本发明。所讨论的具体实施例仅仅示意用于实现并且使用本发明的具体方式,而非限制本发明的范围。
将多个芯片集成到单一半导体封装中要求使用大的管芯垫以支撑所有的芯片。可替代地,使用多个管芯垫从而每一个管芯垫支撑特定的芯片。然而,所有的这些集成方法都增加了封装尺寸,由此要求使用昂贵的封装技术。例如,较大的封装要求使用更加昂贵的腔成型工艺;而较小的封装能够使用还被称为MAP成型工艺的、较不那么昂贵的模封阵列处理(MAP)制造。在各种实施例中,本发明通过使用一种新颖的集成方案减小多芯片半导体封装的封装尺寸。这允许使用较不那么昂贵的MAP成型工艺。在各种实施例中,本发明通过部分地堆叠芯片以由此减小封装尺寸而减小封装尺寸。
将使用图1描述一种半导体封装的结构实施例,而将使用图2-17描述根据本发明的实施例的一种制造半导体封装的方法。将使用图18描述可替代的结构实施例。
在图1a-1c中根据本发明的一个实施例示意了一种半导体封装。图1a示意半导体封装150的顶视图,图1b示意半导体封装150沿着线1b-1b的截面视图,并且图1c示意半导体封装150的底视图。半导体封装150包括衬底100,衬底100可以是一种陶瓷材料,例如印刷电路板(PCB)或者印刷线路板(PWB)。例如,衬底100可能具有连接半导体封装150上的触点的电路。如在图1c中所示意地,多个焊球142联结到衬底100的底表面。提供到封装的电连接的该多个焊球142可以被形成为矩阵诸如球栅阵列(BGA)。
管芯焊盘106被置放在衬底100中的孔中,并且包括第一引线110和第二引线112的多条引线被置放在衬底100的顶表面上的凹陷中。在一个实施例中,管芯焊盘106的顶表面处于与衬底100的底部相同的平面中,并且管芯焊盘106的底表面处于与该多个焊球142的底部相同的平面中以便于在同一表面上安装管芯焊盘106和该多个焊球142。而且,在另一个实例中,该多条引线在衬底100中嵌入从而该多条引线的顶表面处于与衬底100的顶表面相同的平面中。衬底100中的电路连接该多个焊球142、管芯焊盘106和该多条引线。
可以是分立器件、集成电路或者片上系统的第一芯片118被置放在管芯焊盘106的顶表面上。例如,第一芯片118可以包含分立器件诸如MOSFET、BJT、SCR,或者p-n结。在其它实例中,第一芯片118包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,第一芯片118包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者第一芯片118可以包含片上系统。接合线诸如多条第一接合线128将第一芯片118连接到该多条引线中的某条引线,诸如第一引线110。另外地,第二芯片120被置放在第一芯片118的顶表面上。
类似地,第二芯片120被接合线连接到该多条引线中的某条引线。例如,第二芯片120被多条第二接合线130连接到第二引线112。在一个实例中,第二芯片120可以是分立器件、集成电路或者片上系统。第二芯片120可以包含分立器件诸如MOSFET、BJT、SCR或者p-n结。在其它实例中,第二芯片120包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,第二芯片120包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者第二芯片120可以包含片上系统。
第三芯片122被置放在衬底100的顶表面上和该多条引线中的某条引线上。在一个实例中,第三芯片122被电耦合到第一引线110。第三芯片122可以是分立器件、集成电路或者片上系统。第三芯片122可以包含分立器件诸如MOSFET、BJT、SCR或者p-n结。在其它实例中,第三芯片122包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,第三芯片122包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者它可以包含片上系统。
类似地,第四芯片124被置放在衬底100的顶表面上和包括第二引线112的该多条引线中的某条引线上,从而第四芯片124被电耦合到第二引线112。第四芯片124可以是分立器件、集成电路或者片上系统。第四芯片124可以包含分立器件诸如MOSFET、BJT、SCR或者p-n结。在其它实例中,第四芯片124包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,第四芯片124包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者第四芯片124可以包含片上系统。
在衬底100的顶表面上,部分地在该多条引线上,置放倒装芯片136。倒装芯片136在管芯焊盘106、第一芯片118和第二芯片120之上但是并不直接地接触它们。在某些实施例中,倒装芯片136可以是分立器件、集成电路或者片上系统。倒装芯片136可以包含分立器件诸如MOSFET、BJT、SCR或者p-n结。在其它实例中,倒装芯片136包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,倒装芯片136包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者倒装芯片136可以包含片上系统。在一个实施例中,倒装芯片136被物理地并且被电连接到该多条引线。
另外地,热沉138被物理地并且热连接到倒装芯片136和衬底100。热沉138可以被配置为在操作期间将热远离倒装芯片136地传送。在一个实例中,热沉138由热传导材料诸如铜、银或者另一种热传导材料构成。另外的热沉可以被热耦合到热沉138(未予图示)。
此外,模塑料140可以被置放在包围第一芯片118、第二芯片120、第三芯片122、第四芯片124和倒装芯片136的空间或者腔中以保护它们。在一个实例中,模塑料140是电绝缘粘结剂诸如聚合物、环氧树脂或者填充有氧化硅填料的环氧树脂。
图2-17示意用于形成半导体封装的过程的实施例。图2-17中的每一幅均包含子图,包括示意给定过程步骤的顶视图的子图a、示意其截面视图的子图b和示意其底视图的子图c。首先,图2a、2b和2c示意带有通过衬底100置放的孔102的衬底100和在衬底100的顶表面中的多个凹陷103。在一个实例中,粘结剂材料可以被添加到多个凹陷103中。在于图2d中示意的可替代实施例中,该多个凹陷103并不延伸到孔102的边缘,而在由图2d示意的实施例中,该多个凹陷103延伸到孔102的边缘。
而且,图3a、3b和3c示意包含管芯焊盘106和包括第一引线110、第二引线112、第三引线114和第四引线116的多条引线的引线框架104。引线框架104是用于可靠地联结集成电路(IC)芯片或者半导体器件的芯片的传导支撑件或者框架结构。
引线框架104如在图4中描述地联结到衬底100。首先,图4a、4b和4c示意引线框架104联结到衬底100从而该多条引线被置放在衬底100的该多个凹陷103中并且管芯焊盘106被置放在孔102中从而管芯焊盘106的顶表面处于与衬底100的底表面相同的平面中。将引线框架104联结到衬底100可以通过可能地在将粘结剂施加到衬底100之后拾取并且置放引线框架104而执行。棒保持管芯焊盘。
接着,第一芯片118和第二芯片120被联结到集成的引线框架-衬底。图5a、5b和5c示意第一芯片118,第一芯片的顶表面包含联结到管芯焊盘106的顶表面的多个第一接触垫119。将第一芯片118联结到管芯焊盘106可以使用胶合剂诸如环氧胶合剂、扩散焊料或者管芯贴装薄膜执行。然后,图6a、6b和6c示意将第二芯片120联结到第一芯片118的顶表面,这可以使用胶合剂诸如环氧胶合剂、扩散焊料或者管芯贴装薄膜执行。在一个实施例中,第二芯片120的顶表面包含多个第二接触垫121。
在这之后,如在图7a、7b和7c中所示意地,第三芯片122被联结到衬底100的顶表面。包括第一引线110和第三引线114的该多条引线中的某条引线可以被用于将第三芯片122电连接到这些引线。将第三芯片122联结到衬底100的顶表面和该多条引线可以使用胶合剂诸如环氧胶合剂、扩散焊料或者管芯贴装薄膜执行。在一个实施例中,第三芯片122具有置放在它的顶表面上的多个第三接触垫123。
类似地,图8a、8b和8c示意将第四芯片124联结到衬底100的顶表面和包括第二引线112和第四引线116的该多条引线中的某引线,从而第四芯片124被电耦合到这些引线。所述联结可以使用胶合剂诸如环氧胶合剂、扩散焊料或者管芯贴装薄膜执行。而且,第四芯片124具有置放在它的顶表面上的多个第四接触垫125。
图9a、9b和9c示意将多条第一接合线128联结到第一芯片118上的多个第一接触垫119、管芯焊盘106和包括第一引线110的该多条引线中的某条引线。联结该多条第一接合线128可以通过使用焊球-针脚-焊球(BSOB)执行。在执行BSOB时,首先在多个第一接触垫119之一上形成球焊。接着,在该多条第一接合线128中的第一个的相对端上形成针脚式键合,从而将该多条第一接合线128中的该第一个联结到例如第一引线110和管芯焊盘106。
类似地,图10a、10b和10c示意将多条第二接合线130联结到第二芯片120上的多个第二接触垫121和包括第三引线114、第四引线116和第二引线112的该多条引线中的某条引线。可以使用BSOB接合执行联结。
在这之后,图11a、11b和11c示意多个第三接合线132将第三芯片122上的多个第三接触垫123连接到该多条引线中的某条引线和衬底100。联结该多个第三接合线132也可以使用BSOB接合执行。
类似地,图12a、12b和12c示意将多个第四接合线134联结到第四芯片124上的多个第四接触垫125、该多条引线中的某条引线和衬底100。所述联结可以使用BSOB执行。
接着,图13a、13b和13c示意联结到衬底100和该多条引线的倒装芯片136。倒装芯片136可以与包括第一引线110、第二引线112、第三引线114和第四引线116的该多条引线物理地并且电接触。倒装芯片136被联结到多条第一接合线128之一和多条第二接合线130之一的针脚式键合。在一个实施例中,联结倒装芯片136可以由拾取倒装芯片136并且使其倒装在引线上的针脚式键合上的倒装芯片接合器的操纵臂执行。
而且,图14a、14b和14c示意联结到衬底100和倒装芯片136的热沉138。在一个实例中,联结热沉138可以使用扩散焊料或者管芯贴装薄膜执行。可替代地,可以在将倒装芯片136联结到衬底100和引线之前将热沉138联结到倒装芯片136。在这之后,热沉138和倒装芯片136被联结到衬底100和该多条引线。在各种实施例中热沉138可以具有不同的设计类型以便于从所联结的倒装芯片136有效率地散热。
图15a、15b和15c示意置放于在倒装芯片136和管芯焊盘106之间和在热沉138和衬底100之间的间隙中的模塑料140。在一个实例中,当注射液体环氧树脂以填充间隙时引入模塑料140,随后进行可以在大约200℃到大约400℃之间的温度下执行的固化过程。在另一个实例中,模塑料材料在从大约160℃到大约185℃的温度下熔化并且流动到成型盒中。在这之后,模塑料材料可以固化以形成模塑料140。
如在图16a、16b和16c中所示,半导体封装被分开或者分离。在一个实施例中,通过锯切来分离封装。可替代地,可以使用化学过程将封装分离处分开的单元。最后,如由图17a、17b和17c所示意地,多个焊球142被联结到衬底100的底表面。
图18a和18b示意了包含另外的芯片的可替代实施例半导体封装。除了倒装芯片136,在图18a中示意的实施例包括倒装芯片137。除了以下差别,在图18a中示意的半导体封装151类似于在图1b中示意的半导体封装150。替代如在图1b的半导体封装150中将第二芯片120耦合到第二引线112,在于图18a中示意的半导体封装151中,多条第二接合线130将第二芯片120耦合到第三引线111。而且,第五芯片117被置放在第二管芯焊盘107的顶表面上,而第六芯片127被置放在第五芯片117的顶表面上。多条第五接合线131将第五芯片117连接到包括第二引线112的该多条引线中的某条引线,而多条第六接合线129将第六芯片127连接到包括第三引线111的该多条引线中的某条引线。另外地,第二倒装芯片137被置放在衬底100的顶表面上,部分地在包括第二引线112和第三引线111的该多条引线中的某条引线上。类似倒装芯片136,第二倒装芯片137在第二管芯焊盘107、第五芯片117和第六芯片127之上,但是并不直接地接触它们。
第五芯片117、第六芯片127和第二倒装芯片137可以是分立器件、集成电路或者片上系统。例如,第五芯片117、第六芯片127和第二倒装芯片137可以包含分立器件诸如MOSFET、BJT、SCR或者p-n结。在其它实例中,第五芯片117、第六芯片127和第二倒装芯片137包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,第五芯片117、第六芯片127和第二倒装芯片137包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者它们可以包含片上系统。热沉138被物理地并且热连接到第二倒装芯片137。另外地,模塑料140被置放在包围第五芯片117、第六芯片127和第二倒装芯片137的空间或者腔中。
图18b示意包含另外的芯片的另一个实施例半导体封装。除了以下差别,在图18b中示意的半导体封装153类似于在图1b中示意的半导体封装150。为了清楚起见,在图18b中热沉138和模塑料140未予图示,但是存在于半导体封装153中。替代半导体封装150中的第三芯片122,第七芯片152和第八芯片154被置放在衬底100上和半导体封装153中的该多条引线上。多个第五触点166被置放在第七芯片152的顶表面上,并且多条第七接合线168将第七芯片152连接到该多条引线中的某条引线。类似地,多个第六触点162被置放在八个芯片154的顶表面上,并且多条第八接合线164将第八芯片154连接到该多条引线中的某条引线。第七芯片152和第八芯片154可以是分立器件、集成电路或者片上系统。例如,第七芯片152和第八芯片154可以包含分立器件诸如MOSFET、BJT、SCR或者p-n结。在其它实例中,第七芯片152和第八芯片154包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,第七芯片152和第八芯片154包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者它们可以包含片上系统。
另外地,替代半导体封装150中的第四芯片124,半导体封装153具有置放在衬底100的顶表面上和该多条引线中的某条引线上的第九芯片156和第十芯片158。第九芯片156具有置放在它的顶表面上的多个第七触点174,而第十芯片158具有置放在它的顶表面上的多个第八触点170。多条第九接合线176将第九芯片156的该多个第七触点174连接到该多条引线中的某条引线,而多条第十接合线172将第十芯片158的该多个第八触点170连接到该多条引线中的某条引线。第九芯片156和第十芯片158可以是分立器件、集成电路或者片上系统。例如,第九芯片156和第十芯片158可以包含分立器件诸如MOSFET、BJT、SCR或者p-n结。在其它实例中,第九芯片156和第十芯片158包含无源元件诸如电容器、电感器或者电阻器。在进一步的实施例中,第九芯片156和第十芯片158包含可以包含存储器、逻辑或者专用集成电路的集成电路,或者它们可以包含片上系统。
本发明的优点包括良好的电气性能和热冷却性能。另外地,实施例使得能够在单一封装中实现良好的器件功能性。
虽然已经参考示意性实施例描述了本发明,但是并非旨在以限制性的意义理解该描述。在参考该描述时,本领域技术人员将会清楚示意性实施例的各种修改和组合以及本发明的其它实施例。因此所附权利要求旨在涵盖任何的这种修改或者实施例。
Claims (15)
1.一种半导体器件,包括:
具有第一表面和与所述第一表面相对的第二表面的球栅阵列陶瓷衬底,所述球栅阵列陶瓷衬底包括将第一表面上的触点耦合到第二表面上的触点的电路,其中所述球栅阵列陶瓷衬底具有第一孔;
多条引线,置放在所述球栅阵列陶瓷衬底的所述第一表面之上,所述多条引线中的一条或多条引线被耦合到第一表面上的触点;
管芯焊盘,置放在所述第一孔中;
置放在所述球栅阵列陶瓷衬底、所述管芯焊盘和所述多条引线之上的封装剂;
置放在管芯焊盘之上的第一芯片,其中第一芯片被电耦合到所述多条引线中的第一引线;和
置放在第一芯片之上的第二芯片,其中第二芯片被电耦合到所述多条引线中的第二引线。
2.根据权利要求1所述的半导体器件,进一步包括置放在所述球栅阵列陶瓷衬底的所述第二表面处和被耦合到所述球栅阵列陶瓷衬底的第二表面上的触点的多个焊球。
3.根据权利要求1所述的半导体器件,进一步包括置放在所述球栅阵列陶瓷衬底的所述第一表面之上的第三芯片,其中所述第三芯片被电耦合到所述多条引线中的第三引线。
4.根据权利要求3所述的半导体器件,进一步包括:
置放在所述球栅阵列陶瓷衬底的所述第一表面之上的第四芯片,其中所述第四芯片被电耦合到所述多条引线中的第四引线;和
置放在所述球栅阵列陶瓷衬底的所述第一表面之上和所述多条引线之上的第五芯片,其中所述第五芯片被电耦合到所述多条引线中的第五引线。
5.一种半导体器件,包括:
具有第一表面和与所述第一表面相对的第二表面的球栅阵列陶瓷衬底,所述球栅阵列陶瓷衬底包括将第一表面上的触点耦合到第二表面上的触点的电路,其中所述球栅阵列陶瓷衬底具有第一孔;
多条引线,置放在所述球栅阵列陶瓷衬底的所述第一表面之上,所述多条引线中的一条或多条引线被耦合到第一表面上的触点;
管芯焊盘,置放在所述第一孔中;
置放在所述球栅阵列陶瓷衬底、所述管芯焊盘和所述多条引线之上的封装剂;
置放在管芯焊盘之上的第一芯片,其中第一芯片被电耦合到所述多条引线中的第一引线;
置放在所述球栅阵列陶瓷衬底的所述第一表面之上和所述多条引线之上的第二芯片,其中所述第二芯片被电耦合到所述多条引线中的第二引线,其中所述第二芯片具有包括接触垫的主表面;和
用于保持所述第二芯片的芯片支撑件,所述芯片支撑件置放在所述第二芯片之上,其中所述芯片支撑件被耦合到所述球栅阵列陶瓷衬底的所述第一表面。
6.根据权利要求5所述的半导体器件,其中所述芯片支撑件包括导体。
7.根据权利要求5所述的半导体器件,其中所述接触垫被耦合到所述多条引线中的所述第二引线并且其中所述第一芯片具有主表面,其中所述第一芯片的所述主表面面对所述第二芯片的所述主表面。
8.一种半导体器件,包括:
具有第一表面和与所述第一表面相对的第二表面的球栅阵列陶瓷衬底,所述球栅阵列陶瓷衬底包括将第一表面上的触点耦合到第二表面上的触点的电路,其中所述球栅阵列陶瓷衬底具有第一孔;
多条引线,置放在所述球栅阵列陶瓷衬底的所述第一表面之上,所述多条引线中的一条或多条引线被耦合到第一表面上的触点;
管芯焊盘,置放在所述第一孔中;
置放在所述球栅阵列陶瓷衬底、所述管芯焊盘和所述多条引线之上的封装剂;
置放在所述球栅阵列陶瓷衬底的所述第一表面之上和所述多条引线之上的第二芯片,其中所述第二芯片被电耦合到所述多条引线中的第二引线;
用于保持所述第二芯片的芯片支撑件,所述芯片支撑件置放在所述第二芯片之上,其中所述芯片支撑件被耦合到所述球栅阵列陶瓷衬底的所述第一表面;和
置放在所述球栅阵列陶瓷衬底的所述第一表面上的第三芯片,其中所述第三芯片被电耦合到所述多条引线中的第三引线。
9.一种半导体器件,包括:
包括球栅阵列陶瓷衬底且具有第一表面和与所述第一表面相对的第二表面的第一芯片支撑件,所述球栅阵列陶瓷衬底包括将第一表面上的触点耦合到第二表面上的触点的电路,其中所述第一芯片支撑件具有第一孔;
联结到所述第一芯片支撑件并且置放在所述第一芯片支撑件的所述第一孔中的第二芯片支撑件,其中所述第二芯片支撑件包括引线框架的管芯焊盘;
置放在所述第一芯片支撑件的所述第一表面上的多条引线,所述多条引线中的一条或多条引线耦合到第一表面上的触点;和
联结到所述第一芯片支撑件的所述第一表面的第三芯片支撑件。
10.根据权利要求9所述的半导体器件,进一步包括置放在所述第一芯片支撑件的所述第一表面之上和所述多条引线之上的第一芯片。
11.根据权利要求9所述的半导体器件,其中所述第三芯片支撑件包括传导热沉。
12.根据权利要求9所述的半导体器件,进一步包括置放在所述第二芯片支撑件和所述多条引线之上的封装剂。
13.根据权利要求12所述的半导体器件,进一步包括置放在所述第一芯片支撑件的所述第二表面处和被耦合到所述球栅阵列陶瓷衬底的第二表面上的触点的多个焊球。
14.根据权利要求9所述的半导体器件,进一步包括:
置放在所述第二芯片支撑件之上的第一芯片;和
置放在所述第一芯片支撑件的所述第一表面之上的第二芯片。
15.根据权利要求14所述的半导体器件,进一步包括:
置放在所述第一芯片之上的第三芯片;和
置放在所述第一芯片支撑件的所述第一表面之上的第四芯片。
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US9543226B1 (en) | 2015-10-07 | 2017-01-10 | Coriant Advanced Technology, LLC | Heat sink for a semiconductor chip device |
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US20200168534A1 (en) * | 2018-11-28 | 2020-05-28 | Texas Instruments Incorporated | Multi-chip module including standalone capacitors |
US11139268B2 (en) * | 2019-08-06 | 2021-10-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method of manufacturing the same |
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