CN102341899B - 具有多种ic封装构造的无引线阵列塑料封装 - Google Patents

具有多种ic封装构造的无引线阵列塑料封装 Download PDF

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CN102341899B
CN102341899B CN2010800105906A CN201080010590A CN102341899B CN 102341899 B CN102341899 B CN 102341899B CN 2010800105906 A CN2010800105906 A CN 2010800105906A CN 201080010590 A CN201080010590 A CN 201080010590A CN 102341899 B CN102341899 B CN 102341899B
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chip
tube core
lead
frame ribbon
join domain
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CN102341899A (zh
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J.麦米兰
S.P.佩伦
K.鲍威尔
A.冯
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UTAC Headquarters Pte Ltd
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Uti (hk) Ltd
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Abstract

一种无引线集成电路(IC)封装，包括安装至管芯连接区域的IC芯片和电连接IC芯片的多个电触点。IC芯片、电触点和管芯连接区域都覆盖焊接材料，其中部分电触点和管芯连接区域从焊接材料的底表面凸出。

Description

具有多种IC封装构造的无引线阵列塑料封装
相关申请的交叉引用
该申请要求2009年3月6日提交的美国临时申请No. 61/158,170的权益。通过引用的方式该申请并入下列专利文献：1998年6月10日提交的美国专利No. 6,229,200，题目为“Saw-Singulated Leadless Plastic Chip Carrier”；1999年4月9日提交的美国专利No. 6,498,099，题目为“Leadless Plastic Chip Carrier With Etch Back Pad Singulation”；以及2004年1月28日提交的美国专利No. 7,049,177，题目为“Leadless Plastic Chip Carrier With Standoff Contacts And Die连接垫”。
技术领域
本发明通常涉及集成电路(IC)封装技术，更特定但非通过限制性的方式涉及无引线IC封装及其相关制造方法。
背景技术
用于集成电路(IC)封装的系统、方法和技术在计算机化全球经济中是非常重要的。最终阶段中的一种方式包括：IC器件的制造是IC芯片的封装。在封装过程中，一个或多个IC芯片安装在封装基板上，连接电触点，然后涂覆焊接材料，所述焊接材料包含电绝缘体，例如环氧或硅酮焊接化合物。所得结构 – 通常称为“IC封装” – 然后连接至其他电气组件，例如印刷电路板(PCB)上的电气组件，以用于计算机中等。
在大部分IC封装中，IC芯片完全被焊接材料覆盖，而电触点至少部分暴露，使得它们可以连接其他电气组件。换言之，电触点被设计为在焊接材料内的IC芯片和焊接材料外的电气组件之间形成电连接。这些电触点的一种最通常的设计是这样的，其中它们形成延伸到焊接材料侧外方的“引线”。引线典型地向下弯曲以和PCB上的电气组件形成连接。
不幸地，外部引线的存在往往明显增加IC封装的尺寸。例如，由于引线的水平延伸，其往往增加穿过IC封装的长度和宽度。这是不利的，因为在其他原因中，尺寸增加在其中PCB间隔受到限制的系统中通常是存在问题的。另外，因为外部引线典型地沿着IC封装的侧面布置，因此IC封装的接脚数目受到IC封装周围线性距离的限制。另外，这些引线需要另外的检查线性同面性的步骤和另外要求的机械维度(并且如果它们不符合规范要修订或废弃)。最后，引线(从结合指开始向下至外部部分的尖端)增加总的电信号长度(焊线 + 引线)，这影响IC芯片的电学性能。
认识到和常规IC封装有关的这些和其他问题，研究者已经开发出IC封装，其中外部引线被电触点取代，所述电触点在顶部被焊接材料覆盖，但是在IC封装的底部上暴露，因此它们可以连接位于IC封装下方的电气组件。这些IC封装 – 称为“无引线”IC封装 – 和常规IC封装相比往往占据更少的空间，因为不存在外部引线。另外，这些IC封装消除了对于弯曲引线以形成连接的需要。
常规无引线IC封装的一些例子公开在相关和共同转让的美国专利No. 6,229,200、6,498,099和7,049,177，各公开的全部内容都以引用的方式并入本申请中。其中，这些专利描述和展示了无引线IC封装与制备和使用无引线IC封装的技术的多种设计变体形式。
发明概述
公开的实施方案包括具有多种不同构造的无引线IC封装。在不同的实施方案中，无引线封装可具有电触点、IC芯片、以及IC芯片和电触点之间的连接的变化的构造。变化的连接构造可包括例如不同的倒装芯片构造、丝焊连接构造和焊剂连接构造。所述实施方案还包括具有引线上芯片(引线上芯片)构造的IC封装。
在一个实施方案中，描述一种制造无引线集成电路(IC)封装的方法，该方法包括：提供具有顶表面和底表面的引线框架带；除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定一种或多个管芯连接区域的上部和多个电触点的上部；使第一IC芯片安装至所述部分限定的一个或多个管芯连接区域的第一管芯连接区域中的所述引线框架带；使第二IC芯片安装在所述部分限定的一个或多个管芯连接区域的第二管芯连接区域中；在所述多个部分限定的电触点和所述第一IC芯片之间形成电连接；使用焊接层覆盖所述第一IC芯片、所述第二IC芯片、所述部分限定的一个或多个管芯连接区域、所述部分限定的电触点和所述电连接，所述焊接层填充所述凹陷；对应于所述部分限定的一个或多个管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部和所述一个或多个管芯连接区域的下部。
在另一实施方案中，描述一种制造无引线集成电路(IC)封装的方法，该方法包括：提供具有顶表面和底表面的引线框架带；除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定多个电触点的上部；使IC芯片以倒装芯片构造安装至所述多个部分限定的电触点，在所述多个部分限定的电触点和所述IC芯片之间形成电连接；使用焊接层覆盖所述IC芯片和所述多个部分限定的电触点，所述焊接层填充所述凹陷；对应于所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部。
在另一实施方案中，描述一种制造无引线集成电路(IC)封装的方法，该方法包括：提供具有顶表面和底表面的引线框架带；除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定管芯连接区域的上部和多个电触点的上部；围绕所述引线框架带的周围形成侧壁；使用焊接层填充所述凹陷；使IC芯片安装至所述部分限定的管芯连接区域中的引线框架带；在所述多个部分限定的电触点和所述IC芯片之间形成电连接；提供被构造以附接所述侧壁的盖子；使所述盖子附接所述侧壁，所述盖子、所述侧壁、所述引线框架带和所述焊接层在其中限定密封的气腔；对应于所述部分限定的管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而限定所述多个电触点和所述管芯连接区域作为单独组件。
在另一实施方案中，描述一种制造无引线集成电路(IC)封装的方法，该方法包括：提供具有顶表面和底表面的引线框架带；除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定管芯连接区域的上部和多个电触点的上部；使IC芯片安装至所述部分图案化的管芯连接区域中的引线框架带；使无源电子组件安装至所述多个部分图案化的电触点；在所述多个部分限定的电触点和所述IC芯片之间形成电连接；使用焊接层覆盖所述IC芯片、所述无源电子组件、所述部分限定的至少一个管芯连接区域、所述部分限定的电触点和所述电连接，所述焊接层填充所述凹陷；对应于所述部分限定的至少一个管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部和所述至少一个管芯连接区域的下部。
本发明的上述概述不旨在展示本发明的各种实施方案或每一方面。
附图简述
当结合附图来参考下列详述时，可获得本发明的多种实施方案的更全面的理解，其中：
图1A-1B是具有围绕管芯-连接垫周围的两行电触点的无引线IC封装的实施方案的侧视图和仰视图；
图2A-2B是具有安装至管芯连接垫的堆叠的IC芯片的无引线IC封装的实施方案的侧视图和俯视图；
图3A-3B是具有多芯片模块布置的无引线IC封装的实施方案的侧视图和俯视图，该布置具有两个管芯连接垫，所述管芯连接垫均具有安装于其上的IC芯片；
图3C是具有多芯片模块模块布置的无引线IC封装的实施方案的俯视图，该布置具有四个管芯连接垫，所述管芯连接垫均具有安装于其上的IC芯片；
图4A-4B是具有系统级封装(system-in-package)构造的无引线IC封装的实施方案的侧视图和俯视图；
图4C-4E是图4A的细节A的侧视图和俯视图，示出无引线IC封装方面的多种实施方案；
图5是具有系统级封装构造的无引线IC封装的实施方案的俯视图；
图6A-6B是具有倒装芯片构造的无引线IC封装的实施方案的侧视图和仰视图；
图7A-7B是具有安装于其中的两个IC芯片的无引线IC封装的实施方案的侧视图和仰视图，其中IC芯片中的一个为倒装芯片构造；
图8A-8B是具有以叠堆布置安装于其上的倒装芯片构造和两个IC芯片的无引线IC封装的实施方案的侧视图和俯视图；
图9是无引线IC封装的实施方案的侧视图，其中一部分管芯连接垫已经被蚀刻掉；
图10A-10G是在IC封装制造过程的各种阶段无引线IC封装的实施方案的侧视图；以及
图11A-11B示出无引线IC封装的实施方案，所述无引线IC封装中具有气腔和与其一起使用的盖子。
发明详述
现在参照附图描述了选择的实施方案。提供这些实施方案作为教导性例子，并且不应该理解为限制权利要求书的范围。为了便于解释，该描述包括多个取向专用术语，例如“顶部”、“底部”、“上面”、“上方”等。这些术语不应该理解为限制所述制品的取向，而是仅仅旨在反映各种组件或其部分的相对位置。例如，“底表面”可解释为表示相对“顶表面”的表面，而不论具有底表面和顶表面的制品的取向如何。
通常，多种实施方案涉及以多种构造布置的无引线IC封装。这些不同构造可用于实现多种不同目的中的任一种，例如避免管芯-连接垫(DAP)和封装下方的PCB上的电路迹线之间的电学和/或物理干扰、改善DAP的传热特性、促进表面安装至PCB、提供DAP和/或电触点内特殊的电连接以及寻址基于空间的IC封装限制例如接脚数目，等等。在下面的描述中，展示特定构造的多个实施方案。然而，公开的构造旨在仅仅用于描述而非任何限制性目的。例如，多于一个IC芯片可以并列构造附接DAP，称为多芯片模块(MCM)。在具有多个芯片的IC封装中，DAP本身可以是单片或分段，例如其不可以共有相同的底板。或者，IC芯片可以以叠堆-管芯构造彼此堆叠于其上。另外，在一些情况下，IC封装可根本没有DAP。例如，IC芯片可使用电绝缘粘合剂直接和部分附接在电触点的顶部(称为引线上芯片)。IC芯片还可使用倒装芯片技术附接至包括多个电触点的管芯连接区域，其中焊盘具有焊接凸点，所述焊接凸点可回流至电触点的上表面。
还使用特定组件来描述一些实施方案，例如某些类型的IC芯片，包括半导体处理器管芯。然而，这些和其他组件可以被其他部件代替，或用另外的组件改进或补充。例如，无源组件例如芯片电阻器和电容器可以沿着IC芯片附接至电触点(系统级封装)。另外，所述实施方案中的特定材料例如某些类型的金属可以被类似的材料所代替。
现在参照附图，图1A-1B示出无引线IC封装100的实施方案的侧视图和仰视图。特别地参照图1A，示出IC封装100，其具有IC芯片105、DAP 110、电触点125、丝焊130和焊接层120。在所示实施方案中，IC芯片105通过粘合剂层115安装在DAP 110上。在各种实施方案中，粘合剂层115可以是糊或膜，并且可以例如是聚合物材料，例如环氧树脂、硅酮、聚酰亚胺、热塑性材料和/或软焊剂材料如金-锡或者锡和/或铅合金的各种组合。其中，IC芯片105可包括单晶体管、处理器管芯、或来自半导体晶片的存储器芯片切片。
再次参照图1A，IC芯片105包括焊盘140，所述焊盘140起到输入、输出(I/O)端子的作用，并且通过丝焊130连接至电触点125。DAP 110和电触点125都可具有施加和/或镀覆在其顶表面和底表面中的一者或两者上的可焊金属层135。可焊金属层135可包含下列金属的叠堆：例如镍(Ni)、钯(Pd)、金(Au)、银(Ag)、或两者或多种金属的组合如NiPdAu、电解或浸渍锡(Sn)、锡/铅(Sn/Pb)、锡合金或其他焊剂成品，或具有有机可焊防腐剂(OSP)涂层的热浸或裸铜(Cu)。DAP 110和电触点125的顶表面和底表面可镀覆相同材料，或者可镀覆不同材料。层135可以起到下列数种功能中的任一种，例如包括增强顶层的丝焊性、保护镀覆表面避免氧化、改善可焊性和改善导电性。
再次参照图1A，焊接层120可以这样的方式施加，该方式为覆盖IC芯片105、丝焊130、DAP 110和电触点125，但是使部分DAP 110和电触点125暴露在其底表面上。在其中暴露部分的DAP 110和电触点125从焊接层120凸出的实施方案中，凸出的部分可分别形成“支座(standoff)” DAP 和“支座”触点，从而通过可测量的距离从焊接层120的底表面凸出，例如小于或等于0.012 mm至大于或等于0.5 mm。
现在参照图1B，示出IC封装100的仰视图，其中DAP 110和电触点125的底表面可见到通过夹置在它们之间的焊接化合物120而彼此分离。在具有暴露部分的DAP 110和电触点125的实施方案中，可以使用暴露部分来(例如)提供可焊表面以使IC封装100焊接至PCB或另外的基板，从而提供热耗散表面或吸热装置，和/或提供IC封装100与外部电气组件之间的电连接。
现在大体上参照图2A-2B，示出无引线IC封装200的实施方案的侧视图和俯视图，所述无引线IC封装200具有安装于其中的IC封装配件，包括以堆叠关系安装至IC芯片205的IC芯片206。类似于图1A所示的实施方案，IC封装200具有DAP 210、电触点225、丝焊230和焊接层220。在所示IC封装200的实施方案中，IC芯片205使用设置在它们之间的粘合剂层215安装至DAP 210。另外，IC芯片206使用设置在它们之间的粘合剂层216安装至IC芯片205。在所示实施方案中，金属镀覆施加至DAP 210的周围以在其上形成接地环245。在各种实施方案中，IC芯片205和IC芯片206可通过丝焊231彼此电偶联，所述丝焊231电偶联至设置于其上的焊盘240。另外，丝焊230可使IC芯片205和/或IC芯片206电偶联至DAP 210、接地环/电源环245和电触点225中的一个或多个。在所示实施方案中，通过堆叠IC芯片206在IC芯片205的顶部上，可以相对仅具有设置于其中的一个IC芯片的IC封装而增加IC封装200的功能，并且不会增加其封装体尺寸或“足迹”。
现在参照图2B，为了描述目的，示出在施加焊接层之前的IC封装200的俯视图。从该视图可见，包括安装在IC芯片205的顶部上的IC芯片206的IC芯片配件安装到DAP 210上。可见多个焊盘240设置在IC芯片205和206周围的周围。另外，可见多个丝焊230使焊盘240偶联至其他焊盘240、电触点225和接地环/电源环245中的一个或多个。尽管示出接地环/电源环245为DAP 210的上表面上的环并且围绕其圆周，但是在多个实施方案中，接地环245可以是镀覆在DAP 210上的多个分立盘而不是连续环，或者不可包括任何镀覆。尽管示出IC芯片205和206以及DAP 210设置靠近IC封装200的中心区域，但是在多个实施方案中，DAP 210以及IC芯片205和206可以设置在IC封装200的任何区域中。
现在共同地参照图3A-3B，示出为多芯片模块布置的无引线IC封装300的实施方案的侧视图和俯视图，该布置具有邻近第二IC芯片306安装的第一IC芯片305，通常并列取向。为了描述目的，示出在施加焊接层之前图3B中的IC封装300的俯视图。在所示实施方案中，IC芯片305安装至DAP 310并且IC芯片安装至DAP 311，其中DAP 310不同于DAP 311。然而，在多个实施方案中，IC芯片305和306可安装至共同DAP。在所示实施方案中，可见丝焊330使IC芯片305和306电偶联至电触点325。
现在参照图3C，示出为多芯片模块布置的无引线IC封装301的实施方案的俯视图，该布置具有以通常并列布置安装的四个IC芯片305-308。为了描述目的，示出在施加焊接层之前IC封装301的俯视图。在所示实施方案中，可见丝焊330使IC芯片305-308电偶联至电触点325。在所示实施方案中，IC芯片305-308可通过丝焊330直接彼此偶联，如IC芯片305通过丝焊331偶联至IC芯片306所示。在多种实施方案中，丝焊330可通过一个或多个电触点325间接偶联IC芯片305-308，如提供IC芯片305和IC芯片306的间接偶联的共同电触点326所示。
现在共同地参照图4A-4B，示出具有系统级封装构造的无引线IC封装400的实施方案的侧视图和俯视图。为了描述目的，示出在施加焊接层之前图4B中的IC封装400的俯视图。在所示实施方案中，IC封装400含有安装于其中的IC芯片405和一个或多个无源组件450，例如芯片电阻器和/或芯片电容器，它们也安装于其中。无源组件450可以使用任何导电附接介质而附接至一个或多个电触点425。例如填充银的环氧树脂或焊糊。
现在参照图4C-4E，示出图4A的细节A的侧视图和俯视图用于IC封装400的多种实施方案。现在参照图4C，示出的无源组件450安装在电触点425和426之间。当IC封装400安装至PCB时，电触点425和426可以在无源组件450和PCB之间提供电连接。在所示实施方案中，电触点426通常是U-状的，使得无源组件450可偶联至电触点426的第一部分，并且丝焊(未示出)可偶联至电触点426的第二部分。电触点426的中间部分中的“沟槽”可帮助防止焊糊从其第一部分蔓延至其第二部分。类似于图4C，在图4D-4E中所示的实施方案中，无源组件450安装在电触点425和426之间。然而，在图4D-4E中示出的各种实施方案中的电触点426依照多种不同设计标准来不同地构造。例如，沿着电触点426长度的局部蚀刻可提供更大侧表面以用于粘附至焊接化合物。
现在参照图5，示出在增加囊封层之前的具有系统级封装构造的无引线IC封装500的实施方案的俯视图。类似于图4B中所示的实施方案，IC封装500具有安装于其中的IC芯片505和一个或多个无源组件550，并且多个丝焊530使IC芯片505偶联一个或多个电触点525。然而，在所示实施方案中，IC封装500还含有由多个丝焊530偶联的多个电触点525形成的电感器555，以形成“菊链”结构，其被构造以提供电感至IC芯片505，其丝焊至电感器555的菊链结构的第一和最后电触点325。
现在参照图6A-6B，示出具有倒装芯片构造的无引线IC封装600的实施方案的侧视图和仰视图。在制造过程中，进行引线框架带的局部蚀刻以限定电触点625的上部。电触点625的上部形成管芯连接区域以支撑设置于其上的IC芯片605并通过多个倒装芯片连接660使其偶联。支撑倒装芯片构造的IC芯片605的电触点625可互换地称为电触点或倒装芯片端子。倒装芯片连接660可以例如是焊接凸点，如低共熔、无Pb和/或高Pb的，或可以是铜柱，所述铜柱用例如锡或焊剂在其尖端封端。在使用例如多种回流技术使IC芯片605安装至电触点625后，IC芯片605然后可以使用模具底部填充技术用焊接化合物620囊封，其中焊接化合物620围绕IC芯片605一提供增加的机械保护来避免外部环境，和改善IC封装605 和电触点625之间的倒装芯片连接660的机械完整性。在各种实施方案中，模具底部填充方法可以是真空辅助的，这取决于各种设计标准，例如倒装芯片内部连接660的密度。按照模具底部填充方法，引线框架带的底表面可图案化以限定电触点625的下部，从而使它们彼此分离。在各种实施方案中，两个或多个IC芯片可以以倒装芯片构造安装在IC封装600内。
现在参照图7A-7B，示出具有安装于其中的第一和第二IC芯片705和706的无引线IC封装700的实施方案的侧视图和仰视图。在所示实施方案中，IC封装700包括第一IC芯片705，其安装至DAP 710并且丝焊至电触点725。IC封装700还包括以倒装芯片构造安装至电触点(还称为倒装芯片端子)725的第二IC芯片706。在图7B中，其中IC芯片705和706安装在IC封装700内的区域称为管芯连接区域，其以虚线示出。可以看到，DAP 710包括IC芯片705的管芯连接区域712，而管芯连接区域711包括多个倒装芯片端子725。
现在参照图8A-8B，示出无引线IC封装800的实施方案的侧视图和俯视图，所述无引线IC封装800具有安装于其中的IC芯片配件，包括安装至第一IC芯片805的第二IC芯片806。为了描述目的，示出施加焊接层之前图8B中的IC封装800的俯视图。在所示实施方案中，第一IC芯片805安装至设置在中间的电触点或倒装芯片构造的倒装芯片端子825，第二IC芯片806安装至第一IC芯片805，并且丝焊至设置在圆周的电触点825。在一些实施方案中，第一IC芯片805可通过共同端子826电偶联至第二IC芯片806，其中第一IC芯片805通过倒装芯片连接860偶联至共同端子826，并且第二IC芯片806通过丝焊830偶联至共同端子826。
现在参照图9，示出无引线IC封装900的“柱上芯片(chip-on-pillar)”或“引线上芯片”的实施方案的侧视图，其中一部分DAP被蚀刻掉。在所示实施方案中，IC封装900包括安装于其中的IC芯片905，具有设置在其底表面上的非导电性粘合剂层940，例如低流失B-阶段粘合剂、管芯-附接膜(DAF)或晶片背面涂层(WBC)，其可使用筛网印刷、模板印刷、旋转印刷或类似的方法来施加。在IC芯片905安装至DAP后，DAP的中间部分被蚀刻掉，使得只有DAP的圆周部分保留。DAP的圆周部分926提供用于IC芯片905的支撑，并且因此可提供接地焊。可期望应用不具有IC芯片905下方的DAP的IC封装900，其中PCB上的路线要求在IC芯片905下。
现在共同地参照图10A-10G，示出在IC封装制造过程的各个阶段具有形成于其中的气腔的无引线IC封装 1000(示于图10G)的实施方案的侧视图。为了简便，相对于单IC封装来描述IC制造过程。然而，该方法可用于同时制造具有单引线框架带的多个无引线IC封装。尽管相对于具有气腔的IC封装来描述图10A-10G的IC封装制造过程，但是下述多个原理通常可应用于本文所述多种其他IC封装实施方案。现在参照图10A，IC封装制造过程开始于未蚀刻的引线框架1001，其由铜或另外导电材料形成，例如各种金属或金属合金中的一种。
现在参照图10B，引线框架1001局部蚀刻在其顶表面上以在其中形成凹陷或图案，从而部分限定DAP 1010和电触点1025。图案可以使用数种常规蚀刻技术中的任一种来形成，例如多种形式的化学或机械蚀刻。尽管未示出，但是图案可以通过下列方式初始限定：在引线框架1001上形成蚀刻掩模，并且基于蚀刻掩模进行蚀刻。现在参照图10C，一旦形成DAP 1010和电触点1025的区域，这些区域的顶表面和/或底表面可以使用双面选择性镀覆方法来镀覆有镀覆层1035。在DAP 1010的上表面的周围附近设置的部分镀覆层1035还可以在其上形成接地环1045。镀覆层1035和1045可包括金属，例如镍(Ni)、钯(Pd)和金(Au)的叠堆，镍(Ni)和金(Au)或银(Ag)的叠堆。底表面上的镀覆层1035可以镀覆相同材料作为顶表面，或者镀覆其他金属成品例如银(Ag)、金(Au)、镍(Ni)和金(Au)或锡/铅(Sn/Pb)焊剂镀层。
现在参照图10D，可以看到从引线框架1001的外缘向上延伸的IC封装1000的侧壁1065。在各种实施方案中，侧壁1065可以通过使用囊封材料1020填充预成型的模具来形成。囊封材料1020还可以填充电触点1025之间的空间以形成囊封底表面1070。囊封材料1020可以是聚合物材料，例如环氧树脂、硅酮、热塑性和/或液晶聚合物(LCP)。现在参照图10E，IC芯片1005附接至部分限定的DAP 1010的上表面。此后，形成丝焊1030以使IC芯片1005电偶联至电触点1025和/或接地环1045。丝焊1030可以使用常规丝焊技术来形成，例如金、铜或铝丝焊。
现在参照图10F，盖子1075穿过侧壁1065的顶部附接以囊封IC封装1000的内部。盖子1075可以使用粘合剂、超声密封或其他固定方法来附接。盖子1075可以是不透明的，或在一些实施方案中可包括玻璃窗以用于光学应用。在各种实施方案中，盖子1075、侧壁1065、和底部囊封表面1070可以由环氧树脂、硅酮、热塑性(例如液晶聚合物)和/或其他合适的聚合物材料制成。
现在参照图10G，然后引线框架带1001的底表面回蚀刻(back-etch)以从其上除去金属部分1001’，从而限定电触点1025和DAP 1010的下部。在所得结构中，焊接层1020的底表面通过引线框架1001的除去的部分1001’而暴露。在各种实施方案中，在应用中可以期望在IC封装1000内设置气腔，例如用于高速/高频应用，具有GaAs芯片的封装(使用非无源的气桥)，MEMS，光电应用例如生物测定学，和/或不接受复杂叠堆的管芯，其中丝线从常规制模中清除。
现在参照图11A-11B，示出无引线IC封装1100的实施方案，所述无引线IC封装1100中具有气腔和与其一起使用的盖子1175。类似于图10G的IC封装1000，IC封装1100具有盖子1175，所述盖子1175被构造以密封其中的气腔。然而，在所示实施方案中，盖子1175具有半透明部分1180以允许光线通过。例如，在一些实施方案中，半透明部分1180可以是光学透镜或其他半透明玻璃。
考虑到上述内容，应该意识到，无引线IC封装可以使用具有多种不同构造中的任一种的电触点和管芯连接垫来形成，以实现多种不同的结果。不同构造可以使用制造技术来实现，例如上面所讨论或者本领域技术人员可得的一些变化和/或替换技术中的任一种。

Claims (32)

1.一种制造无引线集成电路(IC)封装的方法，包括：
提供具有顶表面和底表面的引线框架带；
除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定一个或多个管芯连接区域的上部和多个电触点的上部；
使第一IC芯片安装至所述部分限定的一个或多个管芯连接区域的第一管芯连接区域中的所述引线框架带；
使第二IC芯片安装在所述部分限定的一个或多个管芯连接区域的第二管芯连接区域中；
在所述多个部分限定的电触点和所述第一IC芯片之间形成电连接；
使用焊接层覆盖所述第一IC芯片、所述第二IC芯片、所述部分限定的一个或多个管芯连接区域、所述部分限定的电触点和所述电连接，所述焊接层填充所述凹陷；
对应于所述部分限定的一个或多个管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及
使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部和所述一个或多个管芯连接区域的下部。
2.权利要求1所述的方法，其中所述第二IC芯片以堆叠构造安装至所述第一IC芯片。
3.权利要求1所述的方法，其中所述第二IC芯片以相对于所述第一IC芯片通常并列构造安装至所述引线框架带。
4.权利要求3所述的方法，其中所述第一管芯连接区域毗邻所述第二管芯连接区域。
5.权利要求2所述的方法，其中所述第一管芯连接区域包括多个倒装芯片端子，并且所述第一IC芯片以倒装芯片构造安装至其上。
6.权利要求3所述的方法，其中所述第一管芯连接区域包括多个倒装芯片端子，并且所第一IC芯片以倒装芯片构造安装至其上。
7.权利要求1所述的方法，还包括：
使电子组件安装至所述引线框架带。
8.权利要求7所述的方法，其中所述电子组件选自：电阻器、电容器和电感器。
9.权利要求1所述的方法，还包括：
使所述第一IC芯片丝焊至所述多个电触点的第一和第二电触点；以及
使所述第一和第二触点以菊链构造和所述多个电触点的一个或多个电触点丝焊，以提供所述第一IC芯片电感。
10.权利要求2所述的方法，其中所述第一IC芯片和所述第二IC芯片通过在它们之间设置的非导电性间隔物材料而分离。
11.权利要求2所述的方法，还包括：
通过多个丝焊使所述第二IC芯片和所述第一IC芯片电偶联。
12.权利要求2所述的方法，还包括：
使所述第二IC芯片丝焊至所述多个电触点的至少一个电触点。
13.权利要求2所述的方法，其中所述电连接是丝焊。
14.权利要求5所述的方法，还包括：
使所述第二IC芯片丝焊至所述多个电触点的至少一个电触点。
15.权利要求5所述的方法，还包括：
通过所述第二IC芯片和所述多个倒装芯片端子的一个或多个倒装芯片端子之间的一个或多个丝焊，使所述第二IC芯片和所述第一IC芯片电偶联。
16.权利要求3所述的方法，还包括：
通过丝焊使所述第一IC芯片和所述第二IC芯片电偶联至所述多个电触点。
17.权利要求16所述的方法，还包括：
通过丝焊使所述第一IC芯片和所述第二IC芯片电偶联。
18.权利要求3所述的方法，还包括：
使存储器芯片以堆叠构造安装至所述第一IC芯片。
19.一种制造无引线集成电路(IC)封装的方法，包括：
提供具有顶表面和底表面的引线框架带；
除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定管芯连接区域的上部和多个电触点的上部；
使IC芯片配件安装至所述部分限定的管芯连接区域中的引线框架带，所述IC芯片配件包括以堆叠构造安装在其顶表面上的第一管芯和第二管芯；
在所述多个部分限定的电触点和所述IC芯片配件之间形成电连接；
使用焊接层覆盖所述IC芯片配件、所述部分限定的管芯连接区域、所述部分限定的电触点和所述电连接，所述焊接层填充所述凹陷；
对应于所述部分限定的管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及
使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部和所述管芯连接区域的下部。
20.权利要求19所述的方法，其中所述管芯连接区域包括管芯-连接垫。
21.权利要求19所述的方法，其中所述管芯连接区域包括多个倒装芯片端子，并且所述第一管芯以倒装芯片构造安装在其上。
22.一种制造无引线集成电路(IC)封装的方法，包括：
提供具有顶表面和底表面的引线框架带；
除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定第一和第二管芯连接区域的上部和多个电触点的上部；
使第一IC芯片安装至所述第一部分限定的管芯连接区域中的所述引线框架带；
使第二IC芯片安装至所述第二部分限定的管芯连接区域中的所述引线框架带；
在所述电触点与所述第一和第二IC芯片之间形成电连接；
使用焊接层覆盖所述第一和第二IC芯片、所述第一和第二部分限定的管芯连接区域、所述多个部分限定的电触点和所述电连接，所述焊接层填充所述凹陷；
对应于所述第一和第二部分限定的管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及
使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部和所述第一和第二管芯连接区域的下部。
23.权利要求22所述的方法，其中所述第一管芯连接区域是管芯-连接垫。
24.权利要求22所述的方法，其中所述第二管芯连接区域是管芯-连接垫。
25.权利要求22所述的方法，其中所述第一管芯连接区域包括多个倒装芯片端子，并且所述第一IC芯片以倒装芯片构造安装于其上。
26.权利要求22所述的方法，其中所述第二管芯连接区域包括多个倒装芯片端子，并且所述第二IC芯片以倒装芯片构造安装于其上。
27.一种制造无引线集成电路(IC)封装的方法，包括：
提供具有顶表面和底表面的引线框架带；
除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定多个电触点的上部；
使IC芯片以倒装芯片构造安装至所述多个部分限定的电触点，
在所述多个部分限定的电触点和所述IC芯片之间形成电连接；
使用焊接层覆盖所述IC芯片和所述多个部分限定的电触点，所述焊接层填充所述凹陷；
对应于所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及
使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部。
28.一种制造无引线集成电路(IC)封装的方法，包括：
提供具有顶表面和底表面的引线框架带；
除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定管芯连接区域的上部和多个电触点的上部；
围绕所述引线框架带的周围形成侧壁；
使用焊接层填充所述凹陷；
使IC芯片安装至所述部分限定的管芯连接区域中的引线框架带；
在所述多个部分限定的电触点和所述IC芯片之间形成电连接；
提供被构造以附接所述侧壁的盖子；
使所述盖子附接所述侧壁，所述盖子、所述侧壁、所述引线框架带和所述焊接层在其中限定密封的气腔；
对应于所述部分限定的管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及
使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而限定所述多个电触点和所述管芯连接区域作为单独组件。
29.权利要求28所述的方法，其中所述盖子是不透明的。
30.权利要求28所述的方法，其中所述盖子包括光学质量玻璃透镜。
31.一种制造无引线集成电路(IC)封装的方法，包括：
提供具有顶表面和底表面的引线框架带；
除去部分所述引线框架带的顶表面以在其中形成凹陷，从而部分限定管芯连接区域的上部和多个电触点的上部；
使IC芯片安装至所述部分图案化的管芯连接区域中的引线框架带；
使无源电子组件安装至所述多个部分图案化的电触点；
在所述多个部分限定的电触点和所述IC芯片之间形成电连接；
使用焊接层覆盖所述IC芯片、所述无源电子组件、所述部分限定的至少一个管芯连接区域、所述部分限定的电触点和所述电连接，所述焊接层填充所述凹陷；
对应于所述部分限定的至少一个管芯连接区域和所述多个部分限定的电触点，在所述引线框架带的底表面上形成抗蚀层；以及
使用所述抗蚀层作为抗蚀掩模来选择性蚀刻所述引线框架带的底表面，从而通过部分所述引线框架带蚀刻以限定所述多个电触点的下部和所述至少一个管芯连接区域的下部。
32.权利要求31所述的方法，其中所述无源电子组件选自：电阻器、电容器和电感器。
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