CN205282448U - 表面安装类型半导体器件 - Google Patents
表面安装类型半导体器件 Download PDFInfo
- Publication number
- CN205282448U CN205282448U CN201520973708.5U CN201520973708U CN205282448U CN 205282448 U CN205282448 U CN 205282448U CN 201520973708 U CN201520973708 U CN 201520973708U CN 205282448 U CN205282448 U CN 205282448U
- Authority
- CN
- China
- Prior art keywords
- lead frame
- region
- package
- contact
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims description 54
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 34
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 abstract 2
- 238000003466 welding Methods 0.000 description 24
- 239000011324 bead Substances 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 19
- 239000010949 copper Substances 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- 239000010410 layer Substances 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 14
- 238000005245 sintering Methods 0.000 description 14
- 238000005520 cutting process Methods 0.000 description 11
- 238000005476 soldering Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 230000005499 meniscus Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000006071 cream Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000004049 embossing Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000003801 milling Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000007669 thermal treatment Methods 0.000 description 3
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910001152 Bi alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910008433 SnCU Inorganic materials 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- CCXYPVYRAOXCHB-UHFFFAOYSA-N bismuth silver Chemical compound [Ag].[Bi] CCXYPVYRAOXCHB-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005098 hot rolling Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000011859 microparticle Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000002957 persistent organic pollutant Substances 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 239000013047 polymeric layer Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/6027—Mounting on semiconductor conductive members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8134—Bonding interfaces of the bump connector
- H01L2224/81345—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本实用新型的各个实施例涉及一种表面安装类型半导体器件的方法。一种表面安装半导体器件,尤其是四方扁平无引线多行(QFN_mr)类型的表面安装半导体器件,包括:半导体材料(20、20’)的主体;以及引线框架元件(11),所述引线框架元件(11)包括电连接至所述半导体主体(20)的多个接触端子(50),所述引线框架元件(11)包括:容纳所述半导体主体(20)的焊盘(12a)、以及接线键合接触区域(12)的一行或者多行(R1、R2),所述接触端子(50)电连接至所述接线键合接触区域(12)。
Description
技术领域
此处描述了一种表面安装类型的半导体器件,尤其是四方扁平无引线多行(QFN_mr)类型的半导体器件。
背景技术
各个实施例可以应用于在消费者、汽车和工业行业中的功率控制、射频传输、物理/电气输入的数字转换的应用的QFN_mr器件。
已知的是,半导体器件,诸如,例如,集成电路和MEMS器件,都包封在对应的封装体内,该封装体执行保护不受外界影响并且作为与外界的分界面的功能。例如,所谓的“表面安装”封装体是已知的,其使得能够在印刷电路板(PCB)上进行表面安装。
更加详细地,表面安装封装体包括,例如,所谓的“无引线四方扁平”(QFN)类型的封装体,也称为“微引线框架”(MLF)封装体或者“小外廓无引线”(SON)封装体。
一般而言,参照例如QFN类型的封装体,其包括树脂区域,其中吞封(englobe)有该树脂区域中的是引线框架,该引线框架又形成分布在封装体的底表面上的至少一个端子阵列。在文件第US2005/0116321号中描述了用于产生包括引线框架的封装体的方法的示例。
如与标准QFN器件相比,QFN_mr器件从0.4mm的间距开始,并且,在相同的面积下,具有更大数量的输入/输出,这些输入/输出有可能布置在QFN_mr器件的底表面上,从由器件的散耗器占用的中央区域开始,一直到其边缘,而在标准QFN器件中,输入/输出可能仅仅沿着边缘布置。
在标准QFN器件中,外接触的表面到达器件的边缘,因为,就接触由引线框架的结构支撑而言,在器件的单片化期间不存在接触自身的分开的问题。在QFN_mr器件中,在执行单片化操作之前,接触完全绝缘并且仅仅由封装树脂和由接线支撑;结果,它们无法承受由切割刀片传输的应力而不分层。为此,QFN_mr器件的引线框架设计为,在接触与封装体的边缘之间留出空间,通常为0.1mm。
在一些情况下,例如在汽车行业中,为了保证在PCB上的QFN_mr器件的焊接操作的质量等级,要求外接触(即,考虑到与所焊器件的与器件自身的中央对应的中性点的距离,从热机械观点来看,受到最大应力的外接触)可目测检查,以便核实焊珠的尺寸和形状遵循最低要求。
关于标准QFN器件,该要求通过引入在接触的暴露侧上的锡的沉积或电镀处理以获得相对于在PCB上的焊接焊盘成90°设置的表面来满足,该表面是使得能够获得更结实的并且更容易经由自动检查来检查的焊接弯月面的表面。
关于QFN_mr器件,因为接触不会到达封装体的边缘,所以这是不可能的。
实用新型内容
此处描述的各个实施例具有改进根据已知领域的器件的潜力的目的,如之前所论述的。
各个实施例基于具有在随附的权利要求书中描述的特性的器件而实现上述目的。
各个实施例可以设想:
—在分隔区域中沉积传导焊接材料,以便将与相邻焊盘向对应的接线键合接触区域接合在一起;
—将器件固定至相应的焊盘;以及
—在引线框架上执行热处理,该热处理设计为将传导焊接材料烧结或者回流。
各个实施例还可以设想:
—执行接线键合,该接线键合包括:在由传导焊接材料接合的接线键合区域与相应的焊盘之间,关联接线;
—在引线框架上执行封装体的模塑;以及
—通过沿着前述分隔区域实现切口以便切割焊传导焊接材料,来执行器件的单片化,从而使传导焊接材料的珠的表面暴露在器件的外部。
各个实施例可以设想前述传导焊接材料是TLPS(瞬时液相焊料)。
各个实施例可以设想提供金属的引线框架,尤其是铜的引线框架,包括多个之前电镀的焊盘和接线键合接触区域。
各个实施例可以设想最外行的区域被被部分地电镀,从而使面朝分隔区域的这部分区域暴露出来。
各个实施例可以设想提供引线框架,该引线框架具有宽度至少为600μm的分隔区域。
各个实施例可以设想,在前述单片化操作之后,经由将焊膏珠铺设在PCB上的步骤、以及将由切割焊珠的侧表面和底表面形成的边缘放置在焊膏珠上的步骤,将单片化的器件安装在PCB上,以导致焊膏珠的侧向弯月面的形成。
各个实施例可以指表面安装类型的半导体器件,尤其是四方扁平无引线多行(QFN_mr)类型的半导体器件,包括半导体材料的主体;引线框架元件,该引线框架元件包括电连接至半导体主体的多个接触端子。前述引线框架元件包括容纳半导体主体的焊盘、以及接线键合接触区域的一行或者多行,接触端子电连接至接线键合接触区域。
各个实施例可以设想接触端子被烧结。
各个实施例可以设想器件包括封装体,该封装体包括涂覆器件区域的介电层,该封装体包括前述半导体主体、前述焊盘、和前述接线键合接触区域的一行或者多行,该封装体通过前述引线框架元件在下面定界,前述接触端子分布在封装体的底表面上以及在封装体的侧表面上。
附图说明
将仅以示例的方式参照所附附图对各个实施例进行描述,其中:
图1A、图1B、图1C和图1D是表示此处描述的器件的制造方法的步骤的截面图;
图2A、图2B、图2C和图2D是表示此处描述的器件的制造方法的变型实施例的截面图;
图3A、图3B和图3C是表示此处描述的器件的制造方法的另外一些步骤的截面图;
图4示出了此处描述的器件的制造方法的又一步骤的截面图;
图5是此处描述的器件的制造方法的又一步骤的示意图;
图6示出了在图5的步骤中获得的器件模块;
图7示出了表示此处描述的最后一个步骤的截面图;
图8A和图8B示出了在此处描述的器件的制造方法的第一步骤中的多个器件的透视图和放大透视图;
图9示出了在此处描述的器件的制造方法的第一步骤中的多个器件的又一视图;
图10A和图10B示出了在此处描述的器件的制造方法的第二步骤中的多个器件的透视图和放大透视图;
图12示出了在此处描述的器件的制造方法的第三步骤中的多个器件的透视图;
图14示出了在此处描述的器件的制造方法的第四步骤中的多个器件的透视图;
图16A和图16B示出了在此处描述的器件的制造方法的第二步骤中的多个器件的又一透视图和放大透视图;
图18示出了在此处描述的制器件的造方法的第五步骤中的多个器件的又一视图;
图20示出了在此处描述的器件的制造方法的第六步骤中的器件的视图;
图21示出了在此处描述的器件的制造方法的第七步骤中的器件的视图;
图11、图13、图15、图17和图19示出了在器件的制造方法的不同步骤中的器件的细节。
具体实施方式
在以下说明中,提供了许多具体细节,旨在能够最大程度地理解以示例的方式提供的各个实施例。实施例可以用或者不用具体细节来实施,或者可以用其他方法、部件、材料等来实施。在其他情况下,公知的结构、材料、或者操作不再详细图示或者描述,从而使得不会模糊各个实施例的各个方面。在本说明中,提及“一个实施例”是为了表明结合该实施例描述的具体特征、结构、或者特性被包括在至少一个实施例中。因此,可以出现在本说明的各处的短语诸如“在一个实施例中”等,并非一定是指一个或者相同的实施例。此外,具体特征、结构或者性可以按照任何方便的方式组合在一个或者多个实施例中。
此处仅仅出于方便读者起见提供了附图标记,并且这些附图标记不限定各个实施例的范围或者意义。
图1A,其表示此处描述的方法的第一步骤110,示出了标准引线框架的侧向截面图。上面的步骤110设想从标准金属引线框架11开始,尤其是铜引线框架,尤其是PPE(预电镀框架)类型的。引线框架11基本上是铜板,在该铜板上,尤其是通过蚀刻,获得相对于顶表面11u的基准面的浮雕图案。这些浮雕图案包括焊盘12a,该焊盘12a具有宽的表面,该表面设计为容纳半导体器件20的主体,所谓的裸片。存在多个焊盘12a,该多个焊盘12a一般成行和成列地布置在引线框架11上(对此,参见图8A的透视图),并且通过更小的接触区域12的一行或者多行(在这种情况下为两行R1、R2)与相邻焊盘分隔开,其中要应用键合接线13。最外行(在这种情况下是与焊盘12a对应的区域12的行R2)、以及与相邻焊盘对应的最外行一起,确定分隔区域23。焊盘放置在相对于更小区域12的中央位置中,在其处待应用键合接线13,以及用于将器件20粘合在其顶表面11u上。
焊盘12a和区域12通过使用材料,诸如NiPd或者NiPdAu或者Ag,而电镀有接触14,以便限定出待应用键合接线13的区域。根据已知的PPF技术(采用电化学工艺对引线框架进行预电镀),优选地在提供引线框架11之前,对接触层14电镀。
如已经提及的,每个焊盘12a通过四个区域12彼此分隔开。如可以从图8更加清楚地注意到,这与每个焊盘12a由区域12的第一行R1围绕并且由区域12的第二行R2围绕的事实相对应,如在图8中更加清楚可见的,第一行R1和第二行R2根据围绕焊盘12a的矩形周长布置。在与相邻焊盘对应的第二行R2之间,确定了分隔区域23,在此处描述的方法中,该分隔区域23具有至少为600±50μm的宽度S。
在引线框架11的底表面11d上,在与区域12对应的位置中,再次通过电镀而获得可焊接的底部接触16,以及在与顶部焊盘12a对应的位置中,提供了底部焊盘16a,底部接触16和底部焊盘16a直接电镀在引线框架11的底部铜表面11d上,该底部铜表面11d基本上是平面的并且不具有任何浮雕图案。
在图8A中图示的是在步骤100中的QFN_mr类型的引线框架11的对应透视图,在该引线框架11的顶表面11u上可见具有基本上矩形形状的焊盘12a。如可以从示出了焊盘12a的放大视图的图8B更加清楚地了解的,这些焊盘12a由区域12的第一行R1沿着围绕焊盘12a的矩形周长围绕,这些区域12待进行接线键合。布置在该周长外侧上的是区域12的第二行R2,并且然后是接触区域23。如可以从图8B注意到的,区域12的第二行R2被部分地电镀,使区域12的面朝分隔区域23的部分暴露出来。
基本上,可以确定出器件区域AD,该器件区域AD的范围是:从分隔区域23的长度S的一半、其内部包括行R2和R1、到焊盘12a。如图8A所示,器件的前述面积AD也基本上是矩形的,并且其周长沿着被分隔区域23确定出的沟槽的纵轴延伸。然后,如随后的图所示的,沿着该周长,制作用于器件的单片化操作的切口。
图9是再次基本在与步骤100对应的处理步骤中的底表面11d的透视图,在该图中可见对应接触16和底部焊盘16a的布置,该布置与在顶表面11d上的区域12和焊盘12a的布置对应,并且因此包括底部焊盘16a,该底部焊盘16a由沿着矩形周长布置的底部接触16的两行围绕。
返回到在图1中图示的过程,为了在步骤120中提供接触端子50(例如,在图7中可见),如在图1B中图示的,在上述区域23中应用了传导焊接材料15,尤其是传导焊接材料珠15。此处术语“珠”理解为如下含义:应用填充材料的焊接材料珠,即,一旦经由热处理烧结或者回流便会通过形成中间金属层而在由铜制成的表面23与12之间提供机械和电学接触的一定量的传导材料。传导焊接材料珠15优选地由可在低温(220℃)下烧结并且不可逆的TLPS(瞬时液相焊料)类型的材料组成,尤其是铜锡复合物,例如由ORMET生产的材料DAP689。TLPS材料基本上是具有可在低温(低于250℃)下烧结的以铜和锡为基础的材料,这种材料一旦烧结便是稳定的,并且在烧结之后形成耐受对铜引线框架的蚀刻处理的中间金属。
在变型实施例中,传导焊接材料15可以是具有高于260℃的回流焊接温度的传导合金,并且因此比用于将器件焊接在PBC上的SAC(锡-银-铜)合金的回流焊接温度高,该SAC合金也耐受对铜引线框架的蚀刻处理。例如,此处使用银-铋合金,例如,由铟产生的材料BiAgX,或者回流焊接温度高于260℃的焊膏。
在步骤120中,使用从一个接触移动至另一个以形成珠的分配针、或者通过热轧加上施加压力、或者通过丝印印刷技术进行转送,来执行传导焊接材料15的应用。可以通过针分配或者通过丝印印刷技术来应用TLPS材料,然而优选地可以仅通过丝印印刷技术来应用具有传导合金的膏。
按照也将在接线键合区域12上的邻接表面覆盖接近50%方式,来应用传导焊接材料15,即,基本上保留不小于100±50μm的长度的表面不具有镀层14。由此,产生了椭圆形形状的传导材料珠15,该珠在结合与两个相邻焊盘对应的两个区域12的方向上的总长度S大于800±50μm,宽度为250±50μm,并且厚度大于200±50μm。
对区域12的用于容纳键合接线13的部分电镀,以产生相对于区域12自身的应用了传导材料15的相连表面的不连续,相反,该表面暴露出来,并且因此是铜表面。这样,传导材料15超过边界的程度是受控的,由此防止材料将区域12的设置有镀层14的部分污染,在该部分处待有效地应用键合接线13。
在需要使用未加工的铜作为区域12的被设计用于接线键合的部分的表面剖光结构的情况下,相连表面再一次由铜制成,但是具有标准粗糙度。
图10A和图10B是在执行步骤120之后的引线框架11的透视图,与视图8A和视图8B相似,其中可以注意到的是由传导材料15制成的珠,每个珠在第二行R2的两个区域12之间延伸,由此将这两个区域接合在一起。在图10B中还可见角部接触15c,该角部接触15c通过将材料15沉积在未经电镀的区域12上而形成。
相反,图11是图1B的关于由传导材料制成的接触15的截面图的放大部分。
然后,步骤130是安装半导体器件的主体20(所谓的裸片)的步骤。在要安装具有金属化底表面的主体20的情况下(如在步骤130中),可以将传导材料15沉积成层15g,也沉积在焊盘12a上以便能够粘合器件20,并且这样,可以与侧向接触的应用同时地应用。
如果传导材料15是可烧结材料,那么然后在步骤140中烧结传导材料15,或者可替代地,经由通过隧道炉或者在静态炉中进行回流来烧结传导材料15。对于烧结,最大温度是220℃,然而,对于具有高回流烧结温度的膏的回流,使用在270℃与300℃之间的温度。
必须监测炉中的氧含量,以便保证完全烧结或者回流。通过使炉在氮气气氛下工作来获得这种条件。在低温可烧结材料(TLPS)的情况下,可以进一步通过使炉在还原性气氛下工作来改进烧结。这种条件通过使炉在氮气N2和氢气H2的混合气体(H2的百分比小于5%)下工作来获得。如图1D所图示的,传导焊接材料珠15进行烧结或者回流(在具有高回流焊接温度的膏的情况下),从而成为焊珠15s,通过焊接连接至相应的接线键合区域12。
图12表示承载着焊珠15s和粘合在焊盘12a上的芯片20的引线框架11(在步骤130之后)的透视图。
图2A至图2D图示了与图1的处理步骤相同的处理步骤,但是考虑了有必要安装具有由氧化硅制成的底表面的器件20’的情况。在这种情况下,在提供引线框架11的步骤110之后,执行沉积传导材料15的步骤120’,其中在焊盘12a上不沉积层15g,而是在步骤125’中,在焊盘12a上应用粘附材料18,粘附材料18是用于具有由氧化硅制成的底表面的器件20’的标准类型的,即,在应用传导焊接材料15之后,例如使用C-DAF(传导裸片-附接膜)或者胶。在步骤130’中,将具有由氧化硅制成的底表面的器件20’应用在焊盘16a上。在烧结或者回流传导焊接材料15的步骤140’期间,执行使一层粘附材料18聚合成聚合层18s。
图3A至图3C图示了在热处理步骤尤其是烧结步骤140或者140’之后的步骤。第一个下一步骤是等离子清洁的步骤150,该步骤的目的是从要执行接线键合的区域12去除任何有机污染物。要考虑到,如果将含有锡的材料用作用于提供接触的传导材料15,那么该材料与可能在等离子清洁中使用的氮气(即,形成气体)反应,形成会导致其自身的污染的不稳定化合物。由此,优选的是,将与氩气结合的氮气用作反应气体70,来执行等离子清洁150的步骤,这保证了适当的机械清洁。
然后,执行接线键合的步骤160,该接线键合通过在区域12和焊盘12a的电镀表面14上(或者在未加工的铜表面上)使用金、铜、或者银的接线13来进行。将接线13连接在行R1和R2中的每个区域12与这些区域2在它们的周长中围起的焊盘12a之间。
图13表示在接线键合160之后的焊珠15s的细节,其中接线13设置为与电镀表面14接触。
下一个步骤170(如在图3C中图示的)是在引线框架11上模塑介电材料(尤其是塑料树脂)层40的步骤,以获得由保护了接线13和器件20或者20’的树脂制成的封装体41。图14是涂覆有介电层40的引线框架11的示意图,而图15示出了在涂覆有介电层40之后的焊珠15s的细节。更加详细地,模塑步骤170设想经由注入其中分布有硅微粒子的热固性环氧树脂来形成介电层40。将介电层40形成在半导体器件的主体20的裸片上,并且涂覆器件的整个区域AD,并且因此还涂覆了焊珠15s。当然,介电层40,即树脂层,还覆盖了在引线框架11上的器件的其他区域。
可以在模塑步骤170之后,例如在175℃的固化温度下,进行热处理,该处理称为模塑后固化(PMC)。
图4再次在侧向截面图中图示了在此处描述的方法的又一步骤180中的引线框架11。
在该在化学回蚀刻步骤中,执行对引线框架11的底表面11d的化学蚀刻,以去除不受镀层14(即,在底表面11d的接触16上和接触焊盘16a上的镀层14)保护的铜层。具体而言,回蚀刻步骤180去除引线框架11的铜,但是不去除通过烧结TPLS而获得的并且制成烧结焊珠15s的SnCu中间金属复合物。结果,在步骤180之后,焊珠15s分布成其本身的底表面15d在引线框架11的底表面11d上、并且设置在电镀接触16之间的其处已经去除了铜的未掩蔽部分中。因此,化学蚀刻180也使焊珠15s的底表面15d暴露了700μm的长度E和250μm的宽度。图16A和图16B是在沉积步骤120之后的引线框架11的透视图,与图10A和图10B的视图相似,在这些图中,在回蚀刻步骤180之后从底表面11d的一侧可以注意到引线框架11,并且因此可以注意到焊珠15s的底表面15d。再次在相同的上下文中,图17示出了在回蚀刻步骤180之后的接触15的细节。
该过程的下一个步骤,步骤190,在图5中图示,并且由各个器件模块30的单片化组成,该单片化优选地通过使用金刚石刀片切割来执行,这产生接近200±50μm的宽度t的切口19。使基本上被包括在分隔区域23之间的器件区域AD与其他对应的器件区域分隔开,由此能够使器件20的裸片与其他器件的其他芯片分隔开。由此切割的介电层40,与引线框架11的与器件区域AD对应的部分集成在一起,并且代表器件模块30的封装体41。
图18是引线框架11的透视图,在单片化步骤190之后,通过切口19将引线框架11分为多个器件模块30。
图6仅仅图示了在封装体41中的单独的模块30,并且可以注意到,在给定封装体41的底表面与引线框架11的底表面11d基本对应的情况下,切口19如何确定模块30的焊珠15s的侧表面15a,该侧表面15a被暴露出,即,未被介电层40或者通过任何镀层覆盖。从图6还可以了解到,在切割之后,底表面15d保持暴露,达200±50μm的距离d。
总而言之,在切割操作190之后,介电区域40形成覆盖裸片20的封装体41,该封装体41通过器件20的区域的这部分引线框架11,在下面定界。切割操作190使得每个焊珠15s,在每个焊珠15s已经基本上被切割掉一半从而形成切割的焊珠15m之后,确定出烧结材料的端子50,该端子包括底表面15d,该底表面15d分布在封装体41的底表面11d上;以及侧表面15a,而该侧表面15a向外暴露并且因此是可焊接的。该侧表面15a与封装体P的侧表面共面,封装体P具有基本上平行立面体的形状,其顶表面和底表面与器件区域AD的顶表面和底表面相对应。沿着由封装体41的侧表面411和由底表面11d形成的边缘延伸的,是接触端子50的至少一部分。因此,切割操作(步骤190)使得形成具有四方扁平无引线(QFN)类型的封装体的器件。
因此,如刚才已经论述的,基本上,在单片化步骤190之后,焊珠15s使侧表面15a和底表面15d暴露出来。这使得可以在PCB60上焊接的步骤200期间(如在图7中图示的),通过形成侧向焊接弯月面25,来执行焊接。如可以在图7中注意到的,焊膏珠24铺设在PCB60上,在这种情况下,优选地是铺设在给定端子50待经由焊接而连接至PCB60的位置处,并且由侧表面15a以及底表面15d(其与封装体P的底部边缘对准)形成的边界被放置在前述焊膏珠24上,从而导致形成侧向弯月面25。
在图19中图示的是切割的焊珠15m的细节,即,焊珠15s由切口19分为两部分,并且也在这种情况下,可以注意到切口19如何使得表面15a暴露出来。切割的珠15m焊接至区域12并且由此与器件的主体20电接触,并且因此形成,可以在其上(尤其是在侧表面15a上)焊接另外的接触的接触端子50。结果,获得器件,该器件包括半导体材料20、20’的主体和引线框架元件11,该引线框架元件11包括电连接至半导体主体20的多个接触端子50,该引线框架元件11包括焊盘12a、和接线键合接触区域12的一行或者多行R1、R2,该接触端子50电连接至接线键合接触区域12。
图20是模块30的示意性透视图,该图突出了:涂覆有环氧树脂的介电层40的顶表面;以及在周长上从环氧树脂的介电层40显露出来的端子50的侧表面15a,由此提供了可以执行焊接200的点,如图7所示。
图21是器件模块30的示意性透视图,该图突出了器件模块30的底表面,并且结果,沿着周长连接至第二行R2的接触16的侧表面15a、和连接至第一行R1的接触16的侧表面15a、以及底部焊盘16a可见。还可见的是切割的珠15m的底表面15d,该底表面15d与底部接触16和珠15m的侧表面电连续。
因此,所公开的解决方案的优点通过前述说明清楚地显露出来。
有利地,对于QFN_mr封装体而言,所描述的方法能够获得侧向弯月面,该侧向弯月面在对外行的PCB检查中可见,这是用于部件的自动定位的系统中所要求的特性。
而且,有利地,该方法可以使用蚀刻引线框架和导体丝网印刷的简单混合技术。而不一定进行电镀导线。
所描述的方法有利地提供:将可烧结材料直接应用在铜引线框架上,而不要求可去除的绝缘装置,或者更加一般地不要求临时衬底。为此,可以用高温(高达300℃)焊膏替代烧结材料,只要该方法通过使用金属引线框架能够实施回流温度(超过250℃)。
经由该方法获得的器件有利地不具有连接至裸片(即,连接至半导体主体)的烧结材料,而是将烧结材料应用在引线框架的接触上,而引线框架又接线键合至裸片。
该方法与ASE、STATS和UTAC技术有利地兼容。
当然,在不背离保护范围的情况下,在不损害所描述的解决方案的原理的情况下,细节和实施例可以相对于此处仅仅以示例的方式已经描述的细节和实施例有所不同,甚至明显地不同。保护范围由所附权利要求书所限定。
Claims (3)
1.一种表面安装半导体器件,尤其是四方扁平无引线多行类型的表面安装半导体器件,其特征在于,包括:
半导体材料(20、20’)的主体;以及
引线框架元件(11),所述引线框架元件(11)包括电连接至所述半导体主体(20)的多个接触端子(50),所述引线框架元件(11)包括:容纳所述半导体主体(20)的焊盘(12a)、以及接线键合接触区域(12)的一行或者多行(R1、R2),
所述接触端子(50)电连接至所述接线键合接触区域(12)。
2.根据权利要求1所述的器件,其特征在于,所述接触端子(50)被烧结。
3.根据权利要求1或2所述的器件,其特征在于,所述器件包括封装体(41),所述封装体(41)包括涂覆器件区域(AD)的介电层(40),所述封装体(41)包括所述半导体主体(20)、所述焊盘(12a)、以及所述接线键合接触区域(12)的一行或者多行(R1、R2),所述封装体(41)通过所述引线框架元件(11)在下面定界,所述接触端子(50)分布在所述封装体(41)的底表面(11d)上以及在所述封装体(41)的侧表面上。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT102015000018951 | 2015-05-28 | ||
ITUB20151360 | 2015-05-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN205282448U true CN205282448U (zh) | 2016-06-01 |
Family
ID=54064501
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201520973708.5U Active CN205282448U (zh) | 2015-05-28 | 2015-11-30 | 表面安装类型半导体器件 |
CN201510855210.3A Active CN106206326B (zh) | 2015-05-28 | 2015-11-30 | 用于制造表面安装类型半导体器件的方法以及对应的半导体器件 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510855210.3A Active CN106206326B (zh) | 2015-05-28 | 2015-11-30 | 用于制造表面安装类型半导体器件的方法以及对应的半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (2) | US9824956B2 (zh) |
EP (1) | EP3098841B1 (zh) |
CN (2) | CN205282448U (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106206326A (zh) * | 2015-05-28 | 2016-12-07 | 意法半导体股份有限公司 | 用于制造表面安装类型半导体器件的方法以及对应的半导体器件 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109494209B (zh) * | 2018-10-08 | 2020-03-06 | 江苏长电科技股份有限公司 | 一种侧壁可浸润超薄封装结构及其制造方法 |
TWI749465B (zh) * | 2020-02-14 | 2021-12-11 | 聚積科技股份有限公司 | 積體電路的轉移封裝方法 |
IT202100005759A1 (it) * | 2021-03-11 | 2022-09-11 | St Microelectronics Srl | Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
US6872599B1 (en) | 2002-12-10 | 2005-03-29 | National Semiconductor Corporation | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
US7122406B1 (en) * | 2004-01-02 | 2006-10-17 | Gem Services, Inc. | Semiconductor device package diepad having features formed by electroplating |
US7608916B2 (en) | 2006-02-02 | 2009-10-27 | Texas Instruments Incorporated | Aluminum leadframes for semiconductor QFN/SON devices |
US20100015329A1 (en) | 2008-07-16 | 2010-01-21 | National Semiconductor Corporation | Methods and systems for packaging integrated circuits with thin metal contacts |
KR101622805B1 (ko) * | 2009-03-06 | 2016-05-20 | 유탁 홍콩 리미티드 | 다양한 ic 패키징 구성들을 가진 리드리스 어레이 플라스틱 패키지 |
US8124447B2 (en) * | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US8803300B2 (en) * | 2009-10-01 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit packaging system with protective coating and method of manufacture thereof |
US8501539B2 (en) * | 2009-11-12 | 2013-08-06 | Freescale Semiconductor, Inc. | Semiconductor device package |
US8969136B2 (en) | 2011-03-25 | 2015-03-03 | Stats Chippac Ltd. | Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof |
US20120306065A1 (en) * | 2011-06-02 | 2012-12-06 | Texas Instruments Incorporated | Semiconductor package with pre-soldered grooves in leads |
JP5959386B2 (ja) * | 2012-09-24 | 2016-08-02 | エスアイアイ・セミコンダクタ株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP6030970B2 (ja) * | 2013-02-12 | 2016-11-24 | エスアイアイ・セミコンダクタ株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP6423369B2 (ja) * | 2013-02-15 | 2018-11-14 | オーメット サーキッツ インク | 多層電子基体z軸内部接続構造物 |
ITMI20130473A1 (it) * | 2013-03-28 | 2014-09-29 | St Microelectronics Srl | Metodo per fabbricare dispositivi elettronici |
US9059185B2 (en) | 2013-07-11 | 2015-06-16 | Texas Instruments Incorporated | Copper leadframe finish for copper wire bonding |
JP6244147B2 (ja) * | 2013-09-18 | 2017-12-06 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置の製造方法 |
CN205282448U (zh) * | 2015-05-28 | 2016-06-01 | 意法半导体股份有限公司 | 表面安装类型半导体器件 |
-
2015
- 2015-11-30 CN CN201520973708.5U patent/CN205282448U/zh active Active
- 2015-11-30 CN CN201510855210.3A patent/CN106206326B/zh active Active
- 2015-12-16 US US14/971,750 patent/US9824956B2/en active Active
- 2015-12-18 EP EP15201108.6A patent/EP3098841B1/en active Active
-
2017
- 2017-10-30 US US15/797,464 patent/US10211129B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106206326A (zh) * | 2015-05-28 | 2016-12-07 | 意法半导体股份有限公司 | 用于制造表面安装类型半导体器件的方法以及对应的半导体器件 |
CN106206326B (zh) * | 2015-05-28 | 2022-05-13 | 意法半导体股份有限公司 | 用于制造表面安装类型半导体器件的方法以及对应的半导体器件 |
Also Published As
Publication number | Publication date |
---|---|
EP3098841B1 (en) | 2021-04-21 |
US20160351476A1 (en) | 2016-12-01 |
US20180053710A1 (en) | 2018-02-22 |
US9824956B2 (en) | 2017-11-21 |
CN106206326A (zh) | 2016-12-07 |
EP3098841A1 (en) | 2016-11-30 |
US10211129B2 (en) | 2019-02-19 |
CN106206326B (zh) | 2022-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN207781575U (zh) | 经封装的电子装置 | |
CN102884623B (zh) | 在介电体上具有端子的微电子封装 | |
CN101252096B (zh) | 芯片封装结构以及其制作方法 | |
KR100324333B1 (ko) | 적층형 패키지 및 그 제조 방법 | |
US20110201159A1 (en) | Semiconductor package and manufacturing method thereof | |
CN102456648B (zh) | 封装基板的制法 | |
CN205282448U (zh) | 表面安装类型半导体器件 | |
KR20050016130A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2011205013A (ja) | 半導体記憶装置 | |
US20070155247A1 (en) | Rounded contact fingers on substrate/PCB for crack prevention | |
US9640506B2 (en) | Method for manufacturing electronic devices | |
JP2017191895A (ja) | 半導体装置および半導体装置の製造方法 | |
CN105489565A (zh) | 嵌埋元件的封装结构及其制法 | |
JP2009194079A (ja) | 半導体装置用配線基板とその製造方法及びそれを用いた半導体装置 | |
CN109390237A (zh) | 侧面可焊接无引线封装 | |
CN102315135B (zh) | 芯片封装及其制作工艺 | |
US8637972B2 (en) | Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel | |
US7768104B2 (en) | Apparatus and method for series connection of two die or chips in single electronics package | |
CN101090077A (zh) | 半导体封装件及其制法 | |
US9318354B2 (en) | Semiconductor package and fabrication method thereof | |
CN103107145A (zh) | 半导体封装件、预制导线架及其制法 | |
US20070205493A1 (en) | Semiconductor package structure and method for manufacturing the same | |
US7611927B2 (en) | Method of minimizing kerf width on a semiconductor substrate panel | |
CN103247578A (zh) | 半导体承载件暨封装件及其制法 | |
JP2013012567A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |