TWI571977B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI571977B
TWI571977B TW103106214A TW103106214A TWI571977B TW I571977 B TWI571977 B TW I571977B TW 103106214 A TW103106214 A TW 103106214A TW 103106214 A TW103106214 A TW 103106214A TW I571977 B TWI571977 B TW I571977B
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Taiwan
Prior art keywords
semiconductor wafer
semiconductor
adhesive film
package
semiconductor package
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TW103106214A
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English (en)
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TW201533858A (zh
Inventor
石啓良
鍾興隆
朱德芳
楊勝明
陳宏成
陳嘉揚
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103106214A priority Critical patent/TWI571977B/zh
Priority to CN201410081790.0A priority patent/CN104867894A/zh
Priority to US14/256,496 priority patent/US9343401B2/en
Publication of TW201533858A publication Critical patent/TW201533858A/zh
Application granted granted Critical
Publication of TWI571977B publication Critical patent/TWI571977B/zh

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Description

半導體封裝件及其製法
本發明係有關於一種半導體封裝件及其製法，尤指一種具有被動元件的半導體封裝件及其製法。
電子產品能否達到輕、薄、短、小、快之理想境界，主要係取決於積體電路(IC)元件在高記憶容量、寬頻及低電壓化需求之發展，然而，積體電路元件能否持續提高記憶容量與操作頻率並降低電壓需求，端視積體電路元件上的電子電路與電子元件積體化的程度以及作為提供電子電路訊號與電源傳遞媒介所用之輸入/輸出連接件(I/O connector)的密度而定。
目前，為了符合業界之需求，讓球柵陣列(BGA)封裝型式之半導體裝置能容納較多例如電容器、電阻器、電感器或振盪器等之被動元件(passive device)已蔚為球柵陣列封裝型式之半導體裝置的主流。
某些例如通訊或高頻半導體裝置的半導體應用裝置常需要將許多電阻器、電感器、電容器及振盪器等被動元件電性連接至所封裝之半導體晶片，俾使該半導體晶片具 有特定之電流特性或發出特定之電訊號。
第1圖所示者，係為習知之球柵陣列封裝型式之半導體裝置的立體圖。如圖所示，複數被動元件11雖安置於基板10表面，但是為了避免該等被動元件11阻礙半導體晶片12與複數銲指墊(bonding fingers)(未圖示)間之電性連接以及半導體晶片12與複數銲指墊的配置，傳統上多將該等被動元件11安置於基板10的角端位置或半導體晶片12接置區域以外的基板10之額外佈局面積上。
惟，限制被動元件11的設置位置將會減少基板10的線路佈局(routability)之靈活性，且限制銲指墊的位置亦導致該等被動元件11的佈設數量受到侷限，而不利半導體裝置的高度集積化之發展趨勢；甚者，被動元件11的佈設數量隨著半導體封裝件的高性能之要求而相對地遽增，倘若採取前述習知方法，該基板10的表面必須同時容納許多半導體晶片12及許多被動元件11，造成基板10的面積加大，進而迫使封裝件的體積增大，亦不符合半導體封裝件輕薄短小之發展潮流。
基於上述問題，遂有人構想將複數被動元件整合至半導體晶片與銲指墊區域間之基板區域上，如第2圖所示之另一種習知之球柵陣列封裝型式之半導體裝置的剖視圖；然而，隨著半導體裝置內之單位面積的輸出/輸入連接件的數量增加，銲線21的數量亦隨之提昇；此外，一般被動元件22的高度(例如0.8毫米)係高於半導體晶片23的高度(例如0.55毫米)，所以如欲避免銲線21觸及被動 元件22而造成短路，則需要拉高銲線21並使之橫越該被動元件22之正上方，導致銲接的困難度提昇並增加製程複雜性，亦使得銲線21的線弧(wire loop)長度增加，且由於銲線21本身多是由金或鋁等材質製成，故增長銲線21的線弧長度將明顯提升銲線21的成本；況且，銲線21本身具有重量，拉高之銲線21若缺乏支撐，容易因本身重力崩塌(sag)而觸及被動元件22並產生短路。
因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：封裝基板，係具有相對之第一表面與第二表面，該第一表面具有複數銲墊；複數被動元件，係設於該第一表面上；黏著膜，係黏設於該複數被動元件上；半導體晶片，係黏設於該黏著膜上而使該黏著膜位於該半導體晶片與被動元件之間；複數銲線，係電性連接該半導體晶片與銲墊；以及封裝膠體，係形成於該封裝基板之第一表面上，以包覆該半導體晶片、被動元件與銲線。
於前述之半導體封裝件中，該第一表面具有一半導體晶片設置區，供該複數被動元件設於該半導體晶片設置區中，且令該複數銲墊圍設於該半導體晶片設置區外。
於前述之半導體封裝件中，復包括複數設於該封裝基板之第二表面上之導電元件。
於本發明之半導體封裝件中，該導電元件係為銲球， 且該被動元件係為電容器、電阻器、電感器或振盪器。
本發明復提供一種半導體封裝件之製法，係包括：提供一封裝基板，其具有相對之第一表面與第二表面，且該第一表面具有複數銲墊；於該第一表面上設置複數被動元件；於該等被動元件上設置一黏著膜與一半導體晶片，以使該黏著膜位於該半導體晶片與被動元件之間；藉由複數銲線電性連接該半導體晶片與銲墊；以及於該封裝基板之第一表面上形成封裝膠體，以包覆該半導體晶片、被動元件與銲線。
於前述之半導體封裝件之製法中，該黏著膜係先設於該半導體晶片上，且其製備之步驟係包括：於一具有複數該半導體晶片的半導體晶圓的一表面上接置該黏著膜；以及進行切單步驟。
依上所述之半導體封裝件之製法，該第一表面具有一半導體晶片設置區，供該複數被動元件設於該半導體晶片設置區中，且令該複數銲墊圍設於該半導體晶片設置區外，於形成該封裝膠體之後，復包括於該封裝基板之第二表面上設置複數導電元件，該導電元件係為銲球，且該被動元件係為電容器、電阻器、電感器或振盪器。
由上可知，本發明之被動元件係不會額外佔用封裝基板的面積，而能維持線路佈局之靈活性；再者，該被動元件並不會有銲線接觸被動元件而短路的問題存在，進而能提高產品良率與提升產品信賴度。
10‧‧‧基板
11、22、31‧‧‧被動元件
12、23、401‧‧‧半導體晶片
21、32‧‧‧銲線
30‧‧‧封裝基板
30a‧‧‧第一表面
30b‧‧‧第二表面
301‧‧‧銲墊
33‧‧‧封裝膠體
34‧‧‧導電元件
40‧‧‧半導體晶圓
41‧‧‧黏著膜
A‧‧‧半導體晶片設置區
第1圖所示者係為習知之球柵陣列封裝型式之半導體裝置的立體圖；第2圖所示者係為另一種習知之球柵陣列封裝型式之半導體裝置的剖視圖；以及第3A至3F圖所示者係本發明之半導體封裝件之製法的剖視圖，其中，第3F’圖係第3F圖之另一實施態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之用語亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第3A至3F圖所示者，係本發明之半導體封裝件之製法的剖視圖，其中，第3F’圖係第3F圖之另一實施態樣。
首先，如第3A圖所示，提供一封裝基板30，其具有相對之第一表面30a與第二表面30b，且該第一表面30a 具有一半導體晶片設置區A與圍設於該半導體晶片設置區A外的複數銲墊301。
如第3B圖所示，於該第一表面30a之半導體晶片設置區A上設置複數被動元件31，該被動元件31係為電容器、電阻器、電感器或振盪器。
如第3C圖所示，於一具有複數半導體晶片401的半導體晶圓40的一表面上接置黏著膜41，並進行切單步驟。
如第3D圖所示，藉由該黏著膜41將該半導體晶片401設置於該等被動元件31上。
如第3E圖所示，藉由複數銲線32電性連接該半導體晶片401與銲墊301。
如第3F圖所示，於該封裝基板30之第一表面30a上形成封裝膠體33，以包覆該半導體晶片401、被動元件31與銲線32，並於該封裝基板30之第二表面30b上設置複數導電元件34，該導電元件34係例如為銲球。
要補充說明的是，本發明之被動元件31並不限於完全在該半導體晶片401對該封裝基板30的投影範圍內，而亦可部分超出該半導體晶片401對該封裝基板30的投影範圍，如第3F’圖所示。
本發明復提供一種半導體封裝件，係包括：一封裝基板30，係具有相對之第一表面30a與第二表面30b，該第一表面30a具有一半導體晶片設置區A與圍繞該半導體晶片設置區A的複數銲墊301；複數被動元件31，係設於該第一表面30a之半導體晶片設置區A上；黏著膜41，係黏 設於該複數被動元件31上；一半導體晶片401，係黏設於該黏著膜41上而使該黏著膜41位於該半導體晶片401與被動元件31之間；複數銲線32，係電性連接該半導體晶片401與銲墊301；以及封裝膠體33，係形成於該封裝基板30之第一表面30a上，以包覆該半導體晶片401、被動元件31與銲線32。
前述之半導體封裝件中，該第一表面30a具有一半導體晶片設置區A，供該複數被動元件31設於該半導體晶片設置區A中，且令該複數銲墊301圍設於該半導體晶片設置區A外，且復包括複數設於該封裝基板30之第二表面30b上之導電元件34。
依前所述之半導體封裝件，該導電元件34係為銲球，且該被動元件31係為電容器、電阻器、電感器或振盪器。
綜上所述，相較於習知技術，由於本發明之被動元件係設置於半導體晶片設置區中，所以不會額外佔用封裝基板的面積，並能維持線路佈局之靈活性；再者，該被動元件並不干涉銲線的設置且並非位於銲線的線弧下方，因而不會有銲線接觸被動元件而短路的問題存在，進而能提高產品良率與提升產品信賴度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
30‧‧‧封裝基板
30a‧‧‧第一表面
30b‧‧‧第二表面
301‧‧‧銲墊
31‧‧‧被動元件
32‧‧‧銲線
33‧‧‧封裝膠體
34‧‧‧導電元件
401‧‧‧半導體晶片
41‧‧‧黏著膜

Claims (19)

  1. 一種半導體封裝件，係包括：封裝基板，係具有相對之第一表面與第二表面，該第一表面具有複數銲墊；複數被動元件，係設於該第一表面上；黏著膜，係接觸黏設於該複數被動元件上，且該黏著膜未接觸該封裝基板之該第一表面；半導體晶片，係黏設於該黏著膜上而使該黏著膜位於該半導體晶片與被動元件之間；複數銲線，係電性連接該半導體晶片與銲墊；以及封裝膠體，係形成於該封裝基板之第一表面上，並接觸該複數被動元件，以包覆該半導體晶片、被動元件與銲線。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一表面具有一半導體晶片設置區，供該複數被動元件設於該半導體晶片設置區中，且令該複數銲墊圍設於該半導體晶片設置區外。
  3. 如申請專利範圍第2項所述之半導體封裝件，其中，該複數銲墊所設置之位置與該半導體晶片設置區係為共平面。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該被動元件係為電容器、電阻器、電感器或振盪器。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該黏著膜係設於該半導體晶片與該複數被動元件之頂 表面之間。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該封裝膠體係為單一層。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該黏著膜係接觸於該半導體晶片之底表面。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該黏著膜係接觸於該複數被動元件之頂表面，且該封裝膠體係接觸於該複數被動元件之側壁。
  9. 如申請專利範圍第1項所述之半導體封裝件，其中，該封裝膠體係直接接觸該封裝基板之該第一表面。
  10. 一種半導體封裝件之製法，係包括：提供一封裝基板，其具有相對之第一表面與第二表面，且該第一表面具有複數銲墊；於該第一表面上設置複數被動元件；於該等被動元件上接觸設置一黏著膜與一半導體晶片，以使該黏著膜位於該半導體晶片與被動元件之間，且該黏著膜未接觸該封裝基板之該第一表面；藉由複數銲線電性連接該半導體晶片與銲墊；以及於該封裝基板之第一表面上形成封裝膠體，以包覆該半導體晶片、被動元件與銲線，其中，該封裝膠體接觸該複數被動元件。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該第一表面具有一半導體晶片設置區，供該複數被動元件設於該半導體晶片設置區中，且令該複數 銲墊圍設於該半導體晶片設置區外。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該複數銲墊所設置之位置與該半導體晶片設置區係為共平面。
  13. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該黏著膜係先設於該半導體晶片上，且其製備之步驟係包括：於一具有複數該半導體晶片的半導體晶圓的一表面上接置該黏著膜；以及進行切單步驟。
  14. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該被動元件係為電容器、電阻器、電感器或振盪器。
  15. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該黏著膜係設於該半導體晶片與該複數被動元件之頂表面之間。
  16. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該封裝膠體係為單一層。
  17. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該封裝膠體係接觸於該半導體晶片。
  18. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該黏著膜係接觸於該複數被動元件之頂表面，且該封裝膠體係接觸於該複數被動元件之側壁。
  19. 如申請專利範圍第10項所述之半導體封裝件之製法， 其中，該封裝膠體係直接接觸該封裝基板之該第一表面。
TW103106214A 2014-02-25 2014-02-25 半導體封裝件及其製法 TWI571977B (zh)

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