TWI468088B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI468088B
TWI468088B TW102118734A TW102118734A TWI468088B TW I468088 B TWI468088 B TW I468088B TW 102118734 A TW102118734 A TW 102118734A TW 102118734 A TW102118734 A TW 102118734A TW I468088 B TWI468088 B TW I468088B
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Taiwan
Prior art keywords
carrier
circuit board
chip
semiconductor package
bonding wire
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TW102118734A
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English (en)
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TW201446089A (zh
Inventor
邱志賢
蔡宗賢
楊超雅
陳嘉揚
鄭志銘
朱育德
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102118734A priority Critical patent/TWI468088B/zh
Priority to CN201310213682.XA priority patent/CN104183555B/zh
Priority to US13/971,189 priority patent/US9502377B2/en
Publication of TW201446089A publication Critical patent/TW201446089A/zh
Application granted granted Critical
Publication of TWI468088B publication Critical patent/TWI468088B/zh

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    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件之製法，尤指一種能提升產品可靠度之半導體封裝件之製法。
由於電子產業的蓬勃發展，大部分的電子產品均不斷朝小型化、輕量化和高速化的目標邁進，其中更有不少電子產品必須使用射頻晶片，例如將射頻晶片與數位IC、射頻晶片與數位訊號處理器(Digital Signal Processor,DSP)、或射頻晶片與基頻晶片(Base Band,BB)等整合在一起，藉以達到小型化或高速化的目標。
習知多晶片封裝構造已有許多型態，為達到較小表面接合面積，一般以堆疊方式將複數個晶片相互堆疊於一基板上，當採用打線接合之方式電性連接該些晶片與該基板時，係將該些晶片之主動面朝上堆疊，以利複數個銲線之連接，例如，將一虛晶片(dummy die)設於兩相鄰晶片之間，或者，以一膠狀黏著劑(paste adhesive)或膠膜間隔兩相鄰之晶片，以提供該些銲線足夠之線弧高度。
第1圖係為習知半導體封裝件1之剖面示意圖。如第 1圖所示，該半導體封裝件1係包含一線路板10、設於該線路板10上之一射頻晶片12、設於該射頻晶片12上之一虛晶片11、設於該虛晶片11上之一半導體晶片14、電性連接該半導體晶片14與該線路板10之複數第一銲線140、電性連接該射頻晶片12與該線路板10之複數第二銲線13及包覆該虛晶片11、半導體晶片14、第一銲線140、射頻晶片12及第二銲線13之封裝膠體16，其中，該虛晶片11係可提供一間距，以使該第二銲線13具有足夠之線弧高度。
然而，該射頻晶片12之射頻電路為敏感區域(尤其當該射頻晶片12為高頻率晶片或無線射頻晶片時)，故會有干擾(interference)、熱量(thermal)等因素影響效能，因而限制佈線之靈活度與元件之擺放空間，致使無法實現高整合之無線(wireless)系統級(System in Package,SiP)封裝模組。
再者，該射頻晶片12與該半導體晶片14之堆疊係會使兩者間訊號互相干擾而產生雜訊，尤其當該射頻晶片12為高頻率晶片或無線射頻晶片時，對於該半導體晶片14的干擾程度更為嚴重。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：一線路板；承載件，係設於該線路 板上；射頻晶片，係設於該承載件上，該射頻晶片具有相對之主動面與非主動面，該主動面上具有複數電極墊，且該非主動面係結合至該承載件上；複數高位銲線，係電性連接該電極墊與該線路板；以及絕緣層，係設於該線路板上，以包覆該承載件、高位銲線與射頻晶片。
本發明復提供一種半導體封裝件之製法，係包括：提供一線路板，該線路板上具有承載件；設置射頻晶片於該承載件上，該射頻晶片具有相對之主動面與非主動面，該主動面上具有複數電極墊，且該非主動面係結合至該承載件上；形成複數高位銲線於該電極墊上，以令該些高位銲線電性連接該電極墊與該線路板；以及形成絕緣層於該線路板上，以包覆該承載件、高位銲線與射頻晶片。
前述之半導體封裝件及其製法中，該承載件係為功能性晶片、虛晶片、散熱片或絕緣體。
前述之半導體封裝件及其製法中，該射頻晶片之寬度係大於該承載件之寬度，以於該射頻晶片與該線路板之間形成容置空間。復包括至少一半導體元件，係設於該線路板上，例如，位於該容置空間中或位於該承載件之周圍。
前述之半導體封裝件及其製法中，該射頻晶片藉由結合層固定於該承載件上。
另外，前述之半導體封裝件及其製法中，復包括形成複數低位銲線於該承載件上，以令該低位銲線連接該承載件與該線路板，且該射頻晶片藉由結合層固定於該承載件上，且該結合層包覆該低位銲線之部分線段。例如，該低 位銲線電性連接該承載件與該線路板；或者，接地層形成於該射頻晶片之非主動面上，且該低位銲線接觸該接地層，使該承載件接地至該線路板。
由上可知，本發明之半導體封裝件及其製法，係藉由將該射頻晶片間隔設於該線路板上，以利於在該線路板與該射頻晶片之間產生空間，以供置放元件或高頻佈線，而達到高度整合無線系統級封裝模組之目的。
1,2,2’,2”‧‧‧半導體封裝件
10,20‧‧‧線路板
11‧‧‧虛晶片
12,22‧‧‧射頻晶片
13‧‧‧第二銲線
14‧‧‧半導體晶片
140‧‧‧第一銲線
16‧‧‧封裝膠體
200‧‧‧黏著層
201,201’‧‧‧第一銲墊
202‧‧‧第二銲墊
21‧‧‧承載件
210,210’‧‧‧低位銲線
23‧‧‧高位銲線
22a‧‧‧主動面
22b‧‧‧非主動面
220‧‧‧電極墊
24‧‧‧半導體元件
25‧‧‧結合層
26‧‧‧絕緣層
27‧‧‧接地層
S‧‧‧容置空間
W,d‧‧‧寬度
第1圖係為習知半導體封裝件之剖視示意圖；以及第2A至2D圖係為本發明之半導體封裝件之製法的剖視示意圖；其中，第2C’圖係為第2C圖之其中一種實施例，第2D’及2D”圖係為第2D圖之其它實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、“高位”、“低位”及“一”等之用語， 亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之半導體封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一線路板20，該線路板20上具有一承載件21，且設置複數半導體元件24於該線路板20上。
於本實施例中，該線路板20具有第一銲墊201與第二銲墊202，且藉由黏著層200固定該承載件21。
再者，該承載件21係為功能性晶片、虛晶片(dummy die)、散熱片或絕緣體。
又，該些半導體元件24係為電阻、電容或電感等，其位於該承載件21之周圍。
如第2B圖所示，形成複數低位銲線210於該承載件21上，以令該低位銲線210電性連接該承載件21與該線路板20之第一銲墊201。
如第2C圖所示，設置一射頻晶片22於該承載件21上，該射頻晶片22具有相對之主動面22a與非主動面22b，該主動面22a上具有複數電極墊220，且該非主動面22b係結合至該承載件21上。
接著，形成複數高位銲線23於該電極墊220上，以令該些高位銲線23電性連接該電極墊220與該線路板20之第二銲墊202。
於本實施例中，該射頻晶片22係為高頻率晶片或無線射頻晶片，且該射頻晶片22之寬度W係大於該承載件21之寬度d，以於該射頻晶片22與該線路板20之間形成一容置空間S，且該半導體元件24係位於該容置空間S中且不接觸該射頻晶片22，即該半導體元件24之高度小於該承載件21之高度，該容置空間S之高度至少0.2mm。
再者，該射頻晶片22藉由一結合層25固定於該承載件21上，該結合層25不接觸該半導體元件24，且利用膠膜包線(Film over Wire,FOW)技術，使該結合層25包覆該低位銲線210之部分線段，以達輕薄短小之目的，且可避免該低位銲線210跨越及觸碰至該射頻晶片22而發生短路之問題，且可降低打線作業之困難度。
又，如第2C’圖所示，本實施例係先形成該結合層25於該射頻晶片22之非主動面22b上，再將該射頻晶片22以該結合層25結合至該承載件21上；於其它實施例中，亦可先形成該結合層25於該承載件21上，再將該射頻晶片22以其非主動面22b結合至該結合層25上。
如第2D圖所示，形成一絕緣層26於該線路板20上，以包覆該承載件21、射頻晶片22、低位銲線210及高位銲線23。
於本實施例中，該絕緣層26係為模壓製程用之封裝膠體，但於其它實施例中，該絕緣層26亦可為例如壓合製程用之薄膜或印刷製程用之膠材等，故該絕緣層26之材質或形成方式並無特別限制。
本發明將該射頻晶片22架高至一適當高度，以形成一 容置空間S，供置放元件(如半導體元件24)及高頻佈線(如線路板20上之線路)，故能提升佈線之靈活度與元件之擺放空間，而達到高度整合無線(wireless)系統級(System in Package,SiP)封裝模組之目的。
再者，利用架高該射頻晶片22，能避免該射頻晶片22與半導體元件24(或線路板20之線路)發生干擾。
又，如第2D’圖所示，亦可於該射頻晶片22之非主動面22b上形成一接地層27，且該低位銲線210’接觸該接地層27，使該承載件21藉由該低位銲線210’僅接地至該線路板20之第一銲墊201’，故該承載件21無電性功能。
另外，如第2D”圖所示，該承載件21亦可藉由部分該低位銲線210’接地至該線路板20之第一銲墊201’，且藉由部分該低位銲線210電性連接該線路板20之第一銲墊201，故該承載件21具電性功能。
本發明提供一種半導體封裝件2,2’,2”，係包括：一線路板20、設於該線路板20上之一承載件21、設於該承載件21上之一射頻晶片22、電性連接該電極墊220與該線路板20之複數高位銲線23、以及設於該線路板20上之一絕緣層26。
所述之承載件21係為功能性晶片、虛晶片、散熱片或絕緣體。
所述之射頻晶片22具有相對之主動面22a與非主動面22b，該主動面22a上具有複數電極墊220，且該非主動面22b係結合至該承載件21上。
所述之絕緣層26係包覆該承載件21、高位銲線23與射頻晶片22。
於一實施例中，該射頻晶片22之寬度W係大於該承載件21之寬度d，以於該射頻晶片22與該線路板20之間形成一容置空間S。復包括設於該線路板20上之至少一半導體元件24，其位於該承載件21之周圍或位於該容置空間S中。
於一實施例中，該射頻晶片22係藉由一結合層25固定於該承載件21上，且藉由複數低位銲線210電性連接該承載件21與該線路板20，令該結合層25包覆該低位銲線210之部分線段。
於一實施例中，該射頻晶片22之非主動面22b上具有一接地層27，且複數低位銲線210’接觸該接地層27，使該承載件21僅接地至該線路板20。或者，該承載件21藉由部分該低位銲線210’接地至該線路板20，且藉由部分該低位銲線210電性連接該線路板20。
綜上所述，本發明之半導體封裝件及其製法中，藉由架高該射頻晶片，以利於在該線路板上置放元件及高頻佈線，而達到高度整合無線系統級封裝模組之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧線路板
21‧‧‧承載件
210‧‧‧低位銲線
22‧‧‧射頻晶片
22a‧‧‧主動面
22b‧‧‧非主動面
220‧‧‧電極墊
23‧‧‧高位銲線
24‧‧‧半導體元件
25‧‧‧結合層
26‧‧‧絕緣層

Claims (16)

  1. 一種半導體封裝件，係包括：至少一半導體元件；一線路板；承載件，係設於該線路板上；射頻晶片，係設於該承載件上，該射頻晶片具有相對之主動面與非主動面，該主動面上具有複數電極墊，且該非主動面係結合至該承載件上；複數高位銲線，係電性連接該電極墊與該線路板；以及絕緣層，係形成於該線路板上，以包覆該承載件、高位銲線與射頻晶片；其中，該射頻晶片之寬度係大於該承載件之寬度，以於該射頻晶片與該線路板之間形成容置空間，該半導體元件設於該線路板上並位於該容置空間中且不接觸該射頻晶片。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該承載件係為功能性晶片、虛晶片、散熱片或絕緣體。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該射頻晶片藉由結合層固定於該承載件上。
  4. 如申請專利範圍第1項所述之半導體封裝件，復包括複數低位銲線，係連接該承載件與該線路板，且該射頻晶片藉由結合層固定於該承載件上。
  5. 如申請專利範圍第4項所述之半導體封裝件，其中， 該低位銲線係電性連接該承載件與該線路板。
  6. 如申請專利範圍第5項所述之半導體封裝件，其中，該結合層包覆該低位銲線之部分線段。
  7. 如申請專利範圍第4或6項所述之半導體封裝件，其中，該射頻晶片之非主動面上具有接地層，且該低位銲線接觸該接地層，使該承載件接地至該線路板。
  8. 如申請專利範圍第7項所述之半導體封裝件，其中，該承載件藉由部分該低位銲線接地至該線路板，且藉由部分該低位銲線電性連接該線路板。
  9. 一種半導體封裝件之製法，係包括：提供一線路板，該線路板上具有承載件及至少一半導體元件；設置射頻晶片於該承載件上，其中，該射頻晶片具有相對之主動面與非主動面，該主動面上具有複數電極墊，且該非主動面係結合至該承載件上，其中，該射頻晶片之寬度係大於該承載件之寬度，以於該射頻晶片與該線路板之間形成容置空間，且令該半導體元件位於該容置空間中且不接觸該射頻晶片；形成複數高位銲線於該電極墊上，以令該些高位銲線電性連接該電極墊與該線路板；以及形成絕緣層於該線路板上，以包覆該承載件、高位銲線與射頻晶片。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該承載件係為功能性晶片、虛晶片、散熱片或 絕緣體。
  11. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該射頻晶片藉由結合層固定於該承載件上。
  12. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成複數低位銲線於該承載件上，以令該低位銲線連接該承載件與該線路板，且該射頻晶片藉由結合層固定於該承載件上。
  13. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該低位銲線係電性連接該承載件與該線路板。
  14. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該結合層係包覆該低位銲線之部分線段。
  15. 如申請專利範圍第12項所述之半導體封裝件之製法，其中，該射頻晶片之非主動面上形成有接地層，供該低位銲線接觸該接地層，以使該承載件接地至該線路板。
  16. 如申請專利範圍第15項所述之半導體封裝件之製法，其中，該承載件藉由部分該低位銲線接地至該線路板，且藉由部分該低位銲線電性連接該線路板。
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