TWI585923B - 封裝基板、封裝結構及其製法 - Google Patents

封裝基板、封裝結構及其製法 Download PDF

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TWI585923B
TWI585923B TW103134528A TW103134528A TWI585923B TW I585923 B TWI585923 B TW I585923B TW 103134528 A TW103134528 A TW 103134528A TW 103134528 A TW103134528 A TW 103134528A TW I585923 B TWI585923 B TW I585923B
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electrical contact
contact pads
conductive
conductive trace
traces
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TW103134528A
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TW201614786A (en
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林長甫
姚進財
陳嘉成
楊志仁
黃富堂
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矽品精密工業股份有限公司
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Priority to TW103134528A priority Critical patent/TWI585923B/zh
Priority to CN201410558182.4A priority patent/CN105590917A/zh
Priority to US14/709,510 priority patent/US20160099204A1/en
Publication of TW201614786A publication Critical patent/TW201614786A/zh
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Description

封裝基板、封裝結構及其製法
本發明係有關一種封裝結構，尤指一種提高良率之封裝基板及其製法。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)、微型化(Miniaturization)以及高電路效能等需求，遂而發展出覆晶(Flip chip)接合封裝技術。
如第1及1’圖所示，習知覆晶式封裝結構1係包括一具有複數導電跡線11與複數電性接觸墊13之基板10、藉由複數導電凸塊15設於該電性接觸墊13上之晶片16、及包覆該晶片16之封裝膠體17，且該電性接觸墊13之高度d等於該導電跡線11之高度d。
由於電子產品朝輕薄短小的趨勢發展，故封裝件的尺寸越來越小，使得各接點間之距離也越來越小。例如，該電性接觸墊13之寬度小於75um，且該導電跡線11之線寬與線距為15um。
惟，習知封裝結構1中，由於該電性接觸墊13之高度d等於該導電跡線11之高度d，亦即該電性接觸墊13之頂面與該導電跡線11之頂面間的直線距離呈水平路徑L(其長度約15um)，故容易導致該導電凸塊15接觸該電性接觸墊13旁的導電跡線11，因而發生短路之問題，進而降低產品良率。
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種封裝結構，係包括：板體，係具有複數導電跡線；複數電性接觸墊，係形成於該板體上，使該電性接觸墊之高度大於該導電跡線之高度，且至少一該電性接觸墊旁係佈設有至少一該導線跡線；以及電子元件，係藉由複數導電元件設於各該電性接觸墊上並電性連接各該電性接觸墊。
本發明復提供一種封裝結構之製法，係包括：於一具有複數導電跡線之板體上形成複數電性接觸墊，使該電性接觸墊之高度大於該導電跡線之高度，且至少一該電性接觸墊旁係佈設有至少一該導線跡線；以及藉由複數導電元件將電子元件設於各該電性接觸墊上並電性連接各該電性接觸墊。
前述之封裝結構及其製法中，該導電跡線之表面係齊平或低於該板體之表面。
前述之封裝結構及其製法中，該導電跡線之表面係外 露於該板體之表面。
前述之封裝結構及其製法中，該電性接觸墊係形成於該導電跡線上。例如，單一該導電跡線上形成有複數該電性接觸墊。
前述之封裝結構及其製法中，復包括形成絕緣保護層於該板體上，且令該些電性接觸墊外露於該絕緣保護層。
前述之封裝結構及其製法中，復包括形成封裝層於該板體上，以令該封裝層包覆該電子元件。
由上可知，本發明之封裝結構及其製法中，主要藉由該電性接觸墊之高度大於該導電跡線之高度，以於該電子元件設於該些電性接觸墊上時，該些導電元件不會接觸該導電跡線，故能避免發生短路之問題。
1,3‧‧‧封裝結構
10‧‧‧基板
11‧‧‧導電跡線
13,23,23’‧‧‧電性接觸墊
15‧‧‧導電凸塊
16‧‧‧晶片
17‧‧‧封裝膠體
2,2’,2”‧‧‧封裝基板
20‧‧‧板體
20a,21a,21a’,23a’‧‧‧表面
21,21’‧‧‧第一導電跡線
22,22’,52‧‧‧第二導電跡線
220‧‧‧接點區
24‧‧‧絕緣保護層
25‧‧‧導電元件
26‧‧‧電子元件
27‧‧‧封裝層
d,h,t‧‧‧高度
L‧‧‧水平路徑
S‧‧‧斜線路徑
第1圖係為習知封裝結構之剖視示意圖；第1’圖係為第1圖之局部放大圖；第2A至2C圖係為本發明封裝基板之製法之剖視示意圖；其中，第2B’、2C’與2C”圖係為第2B及2C圖之另一實施例；第3圖係為本發明封裝結構之剖面示意圖；第3’圖之A-A剖面線係為第3圖；第3”圖係為第3圖之局部放大圖；第4A圖係為本發明封裝基板之另一實施例之上視示意圖；第4B圖係為第4A圖之B-B剖面線之示意圖； 第4C圖係為第4A圖之C-C剖面線之示意圖；第5A圖係為本發明封裝基板之另一實施例之上視示意圖；以及第5B圖係為第5A圖之D-D剖面線之示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之封裝基板2,2’之製法之剖視示意圖。
如第2A圖所示，提供一具有複數第一導電跡線21與第二導電跡線22之板體20，且該第二導電跡線22係定義有複數接點區220。
於本實施例中，該接點區220係為該第二導電跡線22之端部。
如第2B圖所示，形成複數電性接觸墊23於各該接點區220上，使該電性接觸墊23之高度h大於該第一導電跡線21之高度t。
於本實施例中，係以沉積或電鍍製程製作該些電性接觸墊23。
再者，該第一導線跡線21係形成於各該電性接觸墊23之間。
又，該第一導電跡線21之表面21a與該第二導電跡線22之表面係齊平該板體20之表面20a；或者，如第2B’圖所示，藉由蝕刻製程，使該第一導電跡線21’之表面21a’與該第二導電跡線22之表面低於該板體20之表面20a，例如低於該板體20之表面20a約0至10um。
如第2C至2C”圖所示，形成一如防銲層之絕緣保護層24於該板體20上，且令該些電性接觸墊23與部分第一及第二導電跡線21,22外露於該絕緣保護層24(如第2C圖所示)、或令該些電性接觸墊23與部分第二導電跡線22外露於該絕緣保護層24(如第2C”圖所示，藉該絕緣保護層24覆蓋第一導電跡線21以提供較佳隔絕效果)。
於後續製程中，如第3圖所示，藉由複數如銲錫凸塊之導電元件25將一電子元件26以覆晶方式設於各該電性接觸墊23上，使該電子元件26藉由該些導電元件25電性連接各該電性接觸墊23。接著，形成封裝層27於該封裝 基板2之板體20上，以令該封裝層27包覆該電子元件26與該些導電元件25。
於本實施例中，該電子元件26係為係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
再者，於其它實施例中，如第3’圖所示，亦可增高該第二導電跡線22’，使該第二導電跡線22’之高度大於該第一導電跡線21之高度，且該第二導電跡線22’之部分區域係作為該些電性接觸墊23。
本發明之製法中，藉由該電性接觸墊23之高度h大於該第一導電跡線21之高度t，使該電性接觸墊23之表面23a(即頂面)與該第一導電跡線21之表面21a(即頂面)間的直線距離呈斜線路徑S，如第3”圖所示，故相較於習知技術之水平路徑L，本發明之斜線路徑S之長度(約31.5um)大於習知技術之水平路徑L之長度(約15um)。因此，當該電子元件26設於該些電性接觸墊23上時，該些導電元件25不會接觸該第一導電跡線21，故能避免該電性接觸墊23與該第一導電跡線21發生橋接而短路之問題。
又，如第4A至4C圖所示，若該封裝基板2具有多排接點時，外露於該絕緣保護層24之各該電性接觸墊23與各該第一導電跡線21係可交錯排列。
另外，如第5A至5B圖所示，該第二導電跡線52係為電源線或接地線，可於單一該第二導電跡線52上形成複 數電性接觸墊23。
本發明復提供一種封裝結構3，係包括：一封裝基板2,2’,2”、設於該封裝基板2,2’,2”上之一電子元件26以及一包覆該電子元件26之封裝層27。
所述之封裝基板2,2’,2”係包括：一板體20、形成於該板體20上之複數第一導電跡線21,21’及複數電性接觸墊23，使該電性接觸墊23之高度h大於該第一導電跡線21,21’之高度t，且至少一該電性接觸墊23旁係佈設有至少一該導線跡線21,21’。
所述之第一導電跡線21,21’之表面21a,21a’係齊平或低於該板體20之表面20a，且該第一導電跡線21,21’之表面21a,21a’係外露於該板體20之表面20a。
所述之電子元件26係藉由複數導電元件25設於各該電性接觸墊23上並電性連接各該電性接觸墊23。
於一實施例中，該電性接觸墊23係形成於該第二導電跡線22之接點區220上。例如，單一該第二導電跡線52上形成有複數該電性接觸墊23。
於一實施例中，所述之封裝基板2,2’,2”復包括形成於該板體20上之一絕緣保護層24，且令該些電性接觸墊23外露於該絕緣保護層24。
綜上所述，本發明之封裝結構及其製法，藉由將封裝基板上之電性接觸墊增高或降低該電性接觸墊周圍之第一導電跡線之高度，以於該電子元件設於該些電性接觸墊上時，該些導電元件不會接觸該第一導電跡線，故能避免因 發生橋接而短路之問題。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝基板
20‧‧‧板體
21‧‧‧第一導電跡線
21a‧‧‧表面
23‧‧‧電性接觸墊
24‧‧‧絕緣保護層

Claims (18)

  1. 一種封裝基板，係包括：板體，於其一表面具有複數第一導電跡線與第二導電跡線，其中，該些第一與第二導電跡線之高度均相同；複數電性接觸墊，係形成於該第二導電跡線上而未形成於該第一導電跡線上，使該電性接觸墊之高度大於該第一導電跡線之高度，且至少一該電性接觸墊旁係佈設有至少一該第一導線跡線；以及絕緣保護層，係形成於該板體上，且令該些電性接觸墊、該些第一導電跡線與第二導電跡線外露於該絕緣保護層。
  2. 如申請專利範圍第1項所述之封裝基板，其中，該第一導電跡線之表面係齊平或低於該板體之表面。
  3. 如申請專利範圍第1項所述之封裝基板，其中，該第一導電跡線之表面係外露於該板體之表面。
  4. 如申請專利範圍第1項所述之封裝基板，其中，單一該第二導電跡線上形成有複數該電性接觸墊。
  5. 一種封裝基板之製法，係包括：提供一表面具有複數第一導電跡線與第二導電跡線之板體，其中，該些第一與第二導電跡線之高度均相同；形成複數電性接觸墊於該第二導電跡線上，且該些電性接觸墊未形成於該第一導電跡線上，使該電性 接觸墊之高度大於該第一導電跡線之高度，且至少一該電性接觸墊旁係佈設有至少一該第一導線跡線；以及形成絕緣保護層於該板體上，且令該些電性接觸墊、該些第一導電跡線與第二導電跡線外露於該絕緣保護層。
  6. 如申請專利範圍第5項所述之封裝基板之製法，其中，該第一導電跡線之表面係齊平或低於該板體之表面。
  7. 如申請專利範圍第5項所述之封裝基板之製法，其中，該第一導電跡線之表面係外露於該板體之表面。
  8. 如申請專利範圍第5項所述之封裝基板之製法，其中，單一該第二導電跡線上形成有複數該電性接觸墊。
  9. 一種封裝結構，係包括：板體，於其一表面具有複數第一導電跡線與第二導電跡線，其中，該些第一與第二導電跡線之高度均相同；複數電性接觸墊，係形成於該第二導電跡線上而未形成於該第一導電跡線上，使該電性接觸墊之高度大於該第一導電跡線之高度，且至少一該電性接觸墊旁係佈設有至少一該第一導線跡線；絕緣保護層，係形成於該板體上，且令該些電性接觸墊、該些第一導電跡線與第二導電跡線外露於該絕緣保護層；以及電子元件，係藉由複數導電元件設於各該電性接 觸墊上並電性連接各該電性接觸墊。
  10. 如申請專利範圍第9項所述之封裝結構，其中，該第一導電跡線之表面係齊平或低於該板體之表面。
  11. 如申請專利範圍第9項所述之封裝結構，其中，該第一導電跡線之表面係外露於該板體之表面。
  12. 如申請專利範圍第9項所述之封裝結構，其中，單一該第二導電跡線上形成有複數該電性接觸墊。
  13. 如申請專利範圍第9項所述之封裝結構，復包括封裝層，係包覆該電子元件。
  14. 一種封裝結構之製法，係包括：於一表面具有複數第一導電跡線與第二導電跡線之板體之第二導電跡線上形成複數電性接觸墊，且該些電性接觸墊未形成於該第一導電跡線上，使該電性接觸墊之高度大於該第一導電跡線之高度，且至少一該電性接觸墊旁係佈設有至少一該第一導線跡線，其中，該些第一與第二導電跡線之高度均相同；形成絕緣保護層於該板體上，且令該些電性接觸墊、該些第一導電跡線與第二導電跡線外露於該絕緣保護層；以及藉由複數導電元件將電子元件設於各該電性接觸墊上並電性連接各該電性接觸墊。
  15. 如申請專利範圍第14項所述之封裝結構之製法，其中，該第一導電跡線之表面係齊平或低於該板體之表面。
  16. 如申請專利範圍第14項所述之封裝結構之製法，其中，該第一導電跡線之表面係外露於該板體之表面。
  17. 如申請專利範圍第14項所述之封裝結構之製法，其中，單一該第二導電跡線上形成有複數該電性接觸墊。
  18. 如申請專利範圍第14項所述之封裝結構之製法，復包括形成封裝層於該板體上，以令該封裝層包覆該電子元件。
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