TWI635595B - 電路板及晶片封裝體 - Google Patents

電路板及晶片封裝體 Download PDF

Info

Publication number
TWI635595B
TWI635595B TW106129157A TW106129157A TWI635595B TW I635595 B TWI635595 B TW I635595B TW 106129157 A TW106129157 A TW 106129157A TW 106129157 A TW106129157 A TW 106129157A TW I635595 B TWI635595 B TW I635595B
Authority
TW
Taiwan
Prior art keywords
ground
circuit board
chip package
conductive
disposed
Prior art date
Application number
TW106129157A
Other languages
English (en)
Other versions
TW201913947A (zh
Inventor
林宥緯
Original Assignee
晨星半導體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 晨星半導體股份有限公司 filed Critical 晨星半導體股份有限公司
Priority to TW106129157A priority Critical patent/TWI635595B/zh
Priority to US15/850,460 priority patent/US20190067208A1/en
Application granted granted Critical
Publication of TWI635595B publication Critical patent/TWI635595B/zh
Publication of TW201913947A publication Critical patent/TW201913947A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15157—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本發明提供一種晶片封裝體，包括電路板、封裝膠體、複數個導電結構以及電磁干擾防護層。電路板包括複數個接地導電墊，設置於其下表面上。封裝膠體設置於電路板的上表面上。導電結構設置於封裝膠體中，並電連接接地導電墊，其中各導電結構的端點從封裝膠體的側壁露出。電磁干擾防護層設置於封裝膠體上，並透過導電結構的端點與接地導電墊電連接。

Description

電路板及晶片封裝體
本發明關於一種電路板及晶片封裝體，尤指一種電路板及晶片封裝體，其側邊露出的接地導線用以與電磁干擾防護層電連接。
半導體封裝（semiconductor package）是一種用以將一個或多個晶粒密封為一體的技術，以提供晶粒一定的衝擊或摩擦的保護。隨著科技的演進，晶片的尺寸越來越小，其中的線路越來越密集，晶片封裝體的電磁干擾問題亦越來越嚴重，因此，晶片封裝體中會包含一電磁干擾防護層，其與接地導線電連接，以提供電磁干擾防護。然而，晶片封裝體在測試時會重複進出測試插槽，造成電磁干擾防護層與接地導線間因電磁干擾防護層之磨損而形成斷路，使電磁干擾防護層產生天線效應。
本發明之目的之一在於提供一種晶片封裝體及電路板，透過於封裝膠體的側壁露出導電結構，或於電路板的側壁露出多條接地導線的端點，使電磁干擾防護層與接地導線間不易因測試產生斷路。
本發明的一實施例提供一種晶片封裝體，其包括一電路板、一封裝膠體、複數個導電結構以及一電磁干擾防護層。電路板具有彼此相對的上表面以及下表面，其中電路板包括複數個接地導電墊，設置於下表面上。封裝膠體設置於電路板的上表面上。導電結構設置於封裝膠體中，導電結構分別電連接接地導電墊，其中各導電結構的端點從封裝膠體的側壁露出。電磁干擾防護層設置於封裝膠體上，並透過導電結構的端點與接地導電墊電連接。
本發明的另一實施例提供一種電路板，其包括一絕緣層以及複數條接地走線。接地走線設置於絕緣層中，且各接地走線包括複數條接地導線，其中各接地導線的端點從電路板的側壁露出，且接地導線露出的端點在電路板的俯視方向上重疊。
為使熟習本發明所屬技術領域之一般技藝者能更進一步瞭解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成的功效。為了方便表示而能夠輕易了解，圖式並未以成品之實際尺寸或比例繪示，因此圖式中元件之尺寸或比例僅用以示意而並非欲以限制本發明的範圍。
第1圖繪示本發明第一實施例的晶片封裝體的側視圖，第2圖繪示本發明第一實施例的晶片封裝體沿著第1圖的剖線A-A’的剖視圖。如第1圖與第2圖所示，晶片封裝體10包括一電路板CB、一電子元件CH、一封裝膠體EN以及一電磁干擾防護層EL。電路板CB具有彼此相對的上表面CBa以及下表面CBb，電路板CB包括一絕緣層IN、複數個接墊BP、複數個導電墊CP以及複數條晶片走線CTR，絕緣層IN設置於上表面CBa與下表面CBb之間，接墊BP設置於上表面CBa上，導電墊CP設置於下表面CBb上，且晶片走線CTR設置於絕緣層IN中。電子元件CH(例如晶片)設置於電路板CB的上表面CBa上，並可例如透過導電線CL電連接至接墊BP，以透過接墊BP與晶片走線CTR連接至對應的導電墊CP。接墊BP可包括晶片接墊CBP1、CBP2，其中晶片接墊CBP1用以電連接至電子元件CH的接地端，晶片接墊CBP2用以電連接至電子元件CH的非接地訊號端。導電墊CP可包括接地導電墊GCP以及非接地導電墊NGCP，其中接地導電墊GCP用以電連接至外部的接地端，非接地導電墊NGCP用以電連接至外部的非接地端。本領域熟悉該項技藝者應知晶片走線CTR可依據設計需求而有不同的結構。舉例而言，晶片走線CTR可由多層導線層WL以及複數個導通孔所形成，且絕緣層IN可包括複數層絕緣層，其中各導線層WL設置於任兩相鄰的絕緣層之間，使得相鄰導線層WL可透過位於其間的絕緣層分隔開，且各導通孔可貫穿對應的一層或多層絕緣層。因此，於同一晶片走線CTR中，導線可用以達到水平方向H的電連接，而導通孔可用以達到垂直方向V的電連接。
封裝膠體EN設置於電路板CB的上表面CBa上，用以密封電子元件CH。電磁干擾防護層EL設置並覆蓋於封裝膠體EN上，且電磁干擾防護層EL可包括至少兩彼此分隔開的連接部ELP，從封裝膠體EN的上表面延伸至電路板CB的側壁上。值得說明的是，晶片走線CTR中之一者可為用以將晶片接墊CBP1電連接至接地導電墊GCP的接地走線，其包括複數條分別由不同導電層WL所形成的接地導線GW，且接地導線GW中至少兩者的端點可分別從電路板CB不同部分側壁露出，以分別與不同的連接部ELP相接觸。藉此，延伸至電路板CB側壁的各連接部ELP可與對應的一接地導線GW的端點電連接，以進一步電連接至接地導電墊GCP，因此電磁干擾防護層EL可具有電磁干擾防護的功能。
然而，由於晶片封裝體10在測試時會重複進出測試插槽，且電路板CB側壁在測試時會完全接觸測試插槽，因此電磁干擾防護層EL位於電路板CB側壁上的連接部ELP容易受到測試插槽的摩擦而脫落，導致電磁干擾防護層EL與接地導線GW間形成斷路，使得電磁干擾防護層EL產生天線效應。
第3圖繪示本發明第二實施例的晶片封裝體的側視圖，第4圖繪示本發明第二實施例的晶片封裝體沿著第3圖的剖線A-A’的剖視圖。第3、4圖所示之晶片封裝體100與第1、2圖所示之晶片封裝體10的差異在於，晶片封裝體100還包括複數個導電結構GS，設置於封裝膠體EN中，且導電結構GS電連接接地導電墊GCP。導電結構GS可例如為金屬線，但不限於此。在實施例中，電路板CB’的接墊BP可另包括複數個接地接墊GBP，鄰近電路板CB’的側壁設置並電連接接地導電墊GCP。並且，各導電結構GS可連接接地接墊GBP，並從電路板CB’上表面CBa延伸至封裝膠體EN的側壁，使得各導電結構GS的一端點可從封裝膠體EN的側壁露出。由於電磁干擾防護層EL的連接部ELP會延伸至封裝膠體EN的側壁上，因此電磁干擾防護層EL可透過與導電結構GS的接觸電連接至接地接墊GBP，以更進一步電連接至接地導電墊GCP，並可達到電磁干擾防護的功用。為避免延伸至封裝膠體EN側壁的導電結構GS與接地接墊GBP影響電子元件CH與導電線CL的配置，導電結構GS與接地接墊GBP例如可位於晶片接墊CBP1、CBP2與電路板CB’的側壁之間。
於一實施例中，晶片封裝體100之電路板CB’於絕緣層IN中的走線可類似第2圖所示之晶片封裝體10之電路板CB’於絕緣層IN中的走線，且電路板CB’之接地接墊GBP可透過導通孔電連接至如第2圖所示之接地導線GW。
如此一來，由於各導電結構GS的端點可從封裝膠體EN的側壁露出，因此電磁干擾防護層EL與導電結構GS的電連接位置可遠離測試插槽，藉此保持電磁干擾防護層EL與接地導電墊GCP的電連接，以避免產生天線效應。
本發明的電路板並不限於上述實施例的設計。第5圖繪示本發明第三實施例的晶片封裝體200的剖視圖，第6圖繪示本發明晶片封裝體200的電路板從第5圖的箭頭C觀看的側面圖。晶片封裝體200與第3、4圖所示之晶片封裝體100的差異在於，晶片封裝體200之電路板CB”可另包括複數條接地走線GTR，設置於絕緣層IN中，且接地接墊GBP可透過接地走線GTR電連接接地導電墊GCP。具體而言，各接地走線GTR可包括複數條接地導線GW，分別由不同的導電層WL所形成，且可透過接地導通孔GV彼此電連接，進而將位於電路板CB”上表面CBa的接地接墊GBP電連接至位於電路板CB”下表面CBb的接地導電墊GCP。本實施例不同接地走線GTR的接地導線GW可彼此連接，以使接地走線GTR彼此電連接，但不限於此。於另一實施例中，不同接地走線GTR的接地導線GW亦可彼此分隔開，使不同接地走線GTR彼此電性絕緣。
於本實施例中，各接地走線GTR的接地導線GW中之至少兩者可延伸至電路板CB”的側壁，使各接地走線GTR有至少兩接地導線GW的端點可從電路板CB”的側壁露出，以助於與電磁干擾防護層EL的連接部ELP電連接，也就是說，電路板CB”可為電鍍線(plating line, PL)類型電路板。舉例來說，電路板CB”的側壁可具有複數個連接區CR，分別從上表面CBa延伸至下表面CBb，用以設置電磁干擾防護層EL的連接部ELP，且對應同一接地走線GTR的接地導線GW的端點可從同一連接區CR的側壁露出，以與同一連接部ELP連接。因此，連接部ELP的數量可與接地走線GTR的數量相同。舉例而言，連接部ELP的數量可為偶數，例如兩個、四個或以上。
值得說明的是，由於各接地走線GTR有至少兩接地導線GW的端點可從電路板CB”的側壁露出，以增加各連接部ELP與對應接地走線GTR的連接點的數量，因此可降低各連接部ELP與對應接地走線GTR的電連接受到磨損而斷線的機率，以避免晶片封裝體200產生天線效應。為使同一接地走線GTR的接地導線GW方便延伸至電路板CB”的側壁，對應接地接墊GBP的接地走線GTR較佳位於晶片走線CTR與電路板CB”的側壁之間。
值得說明的是，對應同一接地走線GTR的接地導線GW所露出的兩相鄰端點在電路板CB”的俯視方向V上係彼此重疊，而此特徵係違反傳統端點間隔的設計原則，亦即，接地導線GW所露出之兩相鄰端點在水平方向H上之間隔(pitch)NP小於80微米。具體而言，由於含有電路板CB”的晶片封裝體200在進行測試時，會重複進出測試插槽，電路板CB”的端點容易因被測試插槽擠壓，造成金屬絲朝向上表面CBa延伸。在傳統電路板中，上下相鄰導電層WL在水平方向H上的製程對位誤差例如約為50微米，導線端點的寬度例如為約20微米，並且從電路板側壁露出端點並非均電連接至同一晶片走線，因此為避免因端點的金屬展延而造成短路，在設計露出端點的配置關係時，設計原則會設定在分別位於上下兩相鄰導電層WL中的兩相鄰端點在水平方向H上的間隔需大於或等於約80微米。然而，本實施例同一接地走線GTR的接地導線GW均為電連接，因此即使兩者間形成短路也不會產生問題。
請參考第7圖，其繪示本發明第四實施例的晶片封裝體300的剖視圖。相較於第5圖所示之晶片封裝體200，晶片封裝體300的導電結構GS’可為金屬片。
請參考第8圖，其繪示本發明第五實施例的晶片封裝體400的剖視圖。相較於第5圖所示之晶片封裝體200，晶片封裝體400的電路板CB’’’的接地導線GW’可不延伸至電路板CB’’’的側壁，使得電路板CB’’’的側壁並不暴露出接地導線GW’的端點。也就是說，電路板CB’’’也可為非電鍍線(non-plating line, NPL)類型電路板。於本實施例中，電磁干擾防護層EL仍可透過導電結構GS電連接至接地導電墊GCP。 以上所述僅為本發明之實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10、100、200、300、400‧‧‧晶片封裝體
CB、CB’、CB”、CB’’’‧‧‧電路板
CBa‧‧‧上表面
CBb‧‧‧下表面
IN‧‧‧絕緣層
BP‧‧‧接墊
CP‧‧‧導電墊
GBP‧‧‧接地接墊
CBP1、CBP2‧‧‧晶片接墊
GCP‧‧‧接地導電墊
NGCP‧‧‧非接地導電墊
GTR‧‧‧接地走線
CTR‧‧‧晶片走線
V‧‧‧俯視方向
CL‧‧‧導電線
WL‧‧‧導線層
GW、GW’‧‧‧接地導線
GV‧‧‧接地導通孔
CR‧‧‧連接區
H‧‧‧水平方向
NP‧‧‧間隔
DR‧‧‧元件區
GS、GS’‧‧‧導電結構
CH‧‧‧電子元件
SB‧‧‧錫球
EN‧‧‧封裝膠體
ELP‧‧‧連接部
EL‧‧‧電磁干擾防護層
第1圖繪示本發明第一實施例的晶片封裝體的側視圖。 第2圖繪示本發明第一實施例的晶片封裝體沿著第1圖的剖線A-A’的剖視圖。 第3圖繪示本發明第二實施例的晶片封裝體的側視圖。 第4圖繪示本發明第二實施例的晶片封裝體沿著第3圖的剖線A-A’的剖視圖。 第5圖繪示本發明第三實施例的晶片封裝體的剖視圖。 第6圖繪示本發明第三實施例的電路板從第5圖的箭頭C觀看的側面圖。 第7圖繪示本發明第四實施例的晶片封裝體的剖視圖。 第8圖繪示本發明第五實施例的晶片封裝體的剖視圖。

Claims (10)

  1. 一種晶片封裝體，包括： 一電路板，具有彼此相對的一上表面以及一下表面，其中該電路板包括複數個接地導電墊，設置於該下表面上； 一封裝膠體，設置於該電路板的該上表面上； 複數個導電結構，設置於該封裝膠體中，該等導電結構分別電連接該等接地導電墊，其中各該導電結構的一端點從該封裝膠體的側壁露出；以及 一電磁干擾防護層，設置於該封裝膠體上，並透過該等導電結構的該等端點與該等接地導電墊電連接。
  2. 如請求項1所述的晶片封裝體，其中該電路板另包括複數個接地接墊，設置於該上表面上，且該等導電結構透過該等接地接墊電連接該等接地導電墊。
  3. 如請求項2所述的晶片封裝體，其中該電路板另包括一絕緣層以及複數條設置於該絕緣層中的接地走線，且該等接地接墊透過該等接地走線電連接該等接地導電墊。
  4. 如請求項3所述的晶片封裝體，其中各該接地走線包括複數條彼此電連接的接地導線，該等接地導線中之至少兩者的端點從該電路板的側壁露出，且該電磁干擾防護層與該等接地導線中之該至少兩者露出的端點相接觸。
  5. 如請求項4所述的晶片封裝體，其中該等接地導線中之該至少兩者露出的端點在該電路板的俯視方向上重疊。
  6. 如請求項4所述的晶片封裝體，其中該等接地導線中之該至少兩者露出的端點在水平方向上的間隔小於80微米。
  7. 如請求項1所述的晶片封裝體，其中各該導電結構包括金屬線或金屬片。
  8. 一種電路板，包括： 一絕緣層；以及 複數條接地走線，設置於該絕緣層中，且各該接地走線包括複數條接地導線，其中各該接地導線的一端點從該電路板的側壁露出，且該等接地導線露出的該等端點在該電路板的俯視方向上重疊。
  9. 如請求項8所述的電路板，另包括複數個設置於該上表面上之接地接墊以及複數個設置於該下表面上之接地導電墊，且該等接地接墊透過該等接地走線電連接該等接地導電墊。
  10. 如請求項8所述的電路板，其中兩相鄰的該等端點在水平方向上的間隔小於80微米。
TW106129157A 2017-08-28 2017-08-28 電路板及晶片封裝體 TWI635595B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW106129157A TWI635595B (zh) 2017-08-28 2017-08-28 電路板及晶片封裝體
US15/850,460 US20190067208A1 (en) 2017-08-28 2017-12-21 Circuit board and chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106129157A TWI635595B (zh) 2017-08-28 2017-08-28 電路板及晶片封裝體

Publications (2)

Publication Number Publication Date
TWI635595B true TWI635595B (zh) 2018-09-11
TW201913947A TW201913947A (zh) 2019-04-01

Family

ID=64453127

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106129157A TWI635595B (zh) 2017-08-28 2017-08-28 電路板及晶片封裝體

Country Status (2)

Country Link
US (1) US20190067208A1 (zh)
TW (1) TWI635595B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102659093B1 (ko) * 2018-03-08 2024-04-22 삼성전자주식회사 배선을 전기적으로 연결하는 도전성 구조물을 포함하는 회로 기판 및 이를 포함하는 전자 장치
CN215299222U (zh) * 2018-11-30 2021-12-24 株式会社村田制作所 模块
CN111422818B (zh) * 2020-03-30 2024-01-23 歌尔微电子股份有限公司 传感器封装结构及封装方法
WO2023053763A1 (ja) * 2021-09-30 2023-04-06 株式会社村田製作所 モジュール

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201526194A (zh) * 2013-12-23 2015-07-01 Sk Hynix Inc 具有電磁干擾屏蔽層的半導體封裝、製造其之方法、包含其之電子系統及包含其之記憶卡
TWM517418U (zh) * 2015-08-13 2016-02-11 力成科技股份有限公司 隔室遮蔽之多晶片封裝構造

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201526194A (zh) * 2013-12-23 2015-07-01 Sk Hynix Inc 具有電磁干擾屏蔽層的半導體封裝、製造其之方法、包含其之電子系統及包含其之記憶卡
TWM517418U (zh) * 2015-08-13 2016-02-11 力成科技股份有限公司 隔室遮蔽之多晶片封裝構造

Also Published As

Publication number Publication date
US20190067208A1 (en) 2019-02-28
TW201913947A (zh) 2019-04-01

Similar Documents

Publication Publication Date Title
TWI635595B (zh) 電路板及晶片封裝體
US20170278830A1 (en) Semiconductor packages having reduced stress
US20130026657A1 (en) Semiconductor package and method of fabricating the same
KR100368025B1 (ko) 중심 지향성 솔더 볼 랜드 타입을 갖는 회로 기판 및 이를이용한 ｂｇａ 패키지
TWI614861B (zh) 電子封裝結構及其製法
TWI566352B (zh) 封裝基板及封裝件
JP5627097B2 (ja) 配線基板
KR20110028939A (ko) 솔더 볼 및 반도체 패키지
US10021784B1 (en) Electronic device and electronic circuit board thereof
US10559513B2 (en) Circuit board and packaged chip
TWI582905B (zh) 晶片封裝結構及其製作方法
US20210035916A1 (en) Semiconductor package
TWM462949U (zh) 封裝基板
TWI483351B (zh) 半導體裝置及其製法
KR101332865B1 (ko) 팬-인 타입 반도체 장치
TWI495052B (zh) 基板結構與使用該基板結構之半導體封裝件
CN109509728B (zh) 电子封装件
TWI585923B (zh) 封裝基板、封裝結構及其製法
TWI520295B (zh) 具金屬柱組及導電孔組之基板及具金屬柱組及導電孔組之封裝結構
US20230170290A1 (en) Semiconductor package
TWI721648B (zh) 封裝載板以及封裝結構
US20240055365A1 (en) Electronic device
KR20160116838A (ko) 반도체 패키지
CN109509736A (zh) 电路板及芯片封装体
TWI605544B (zh) 基板結構及其製法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees
MM4A Annulment or lapse of patent due to non-payment of fees