CN105590917A - 封装基板、封装结构及其制法 - Google Patents

封装基板、封装结构及其制法 Download PDF

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CN105590917A
CN105590917A CN201410558182.4A CN201410558182A CN105590917A CN 105590917 A CN105590917 A CN 105590917A CN 201410558182 A CN201410558182 A CN 201410558182A CN 105590917 A CN105590917 A CN 105590917A
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Prior art keywords
electric contact
plate body
conductive
making
packaging
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林长甫
姚进财
陈嘉成
杨志仁
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

一种封装基板、封装结构及其制法，该封装结构包括：具有多个导电迹线与电性接触垫的封装基板、以及藉由多个导电元件设于各该电性接触垫上并电性连接各该电性接触垫的电子元件，其中，至少一该电性接触垫旁布设有至少一该导线迹线，所以藉由该电性接触垫的高度大于该导电迹线的高度，使该些导电元件不会接触该导电迹线，所以能避免该电性接触垫与该第一导电迹线发生桥接而短路的问题。

Description

封装基板、封装结构及其制法
技术领域
本发明有关一种封装结构，尤指一种提高良率的封装基板及其制法。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术亦随之开发出不同的封装型态。为满足半导体装置的高积集度(Integration)、微型化(Miniaturization)以及高电路效能等需求，遂而发展出覆晶(Flipchip)接合封装技术。
如图1及图1’所示，现有覆晶式封装结构1包括一具有多个导电迹线11与多个电性接触垫13的基板10、藉由多个导电凸块15设于该电性接触垫13上的晶片16、及包覆该晶片16的封装胶体17，且该电性接触垫13的高度d等于该导电迹线11的高度d。
由于电子产品朝轻薄短小的趋势发展，所以封装件的尺寸越来越小，使得各接点间的距离也越来越小。例如，该电性接触垫13的宽度小于75um，且该导电迹线11的线宽与线距为15um。
然而，现有封装结构1中，由于该电性接触垫13的高度d等于该导电迹线11的高度d，也就是该电性接触垫13的顶面与该导电迹线11的顶面间的直线距离呈水平路径L(其长度约15um)，所以容易导致该导电凸块15接触该电性接触垫13旁的导电迹线11，因而发生短路的问题，进而降低产品良率。
因此，如何克服上述现有技术的问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种封装基板、封装结构及其制法，能避免该电性接触垫与该第一导电迹线发生桥接而短路的问题。
本发明的一种封装基板，包括：板体，其具有多个导电迹线；以及多个电性接触垫，其形成于该板体上，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线。
本发明还提供一种封装基板的制法，包括：提供一具有多个导电迹线的板体；以及形成多个电性接触垫于该板体上，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线。
本发明的封装结构，包括：板体，其具有多个导电迹线；多个电性接触垫，其形成于该板体上，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线；以及电子元件，其藉由多个导电元件设于各该电性接触垫上并电性连接各该电性接触垫。
本发明还提供一种封装结构的制法，其包括：于一具有多个导电迹线的板体上形成多个电性接触垫，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线；以及藉由多个导电元件将电子元件设于各该电性接触垫上并电性连接各该电性接触垫。
前述的封装结构及其制法中，该导电迹线的表面齐平或低于该板体的表面。
前述的封装结构及其制法中，该导电迹线的表面外露于该板体的表面。
前述的封装结构及其制法中，该电性接触垫形成于该导电迹线上。例如，单一该导电迹线上形成有多个该电性接触垫。
前述的封装结构及其制法中，复包括形成绝缘保护层于该板体上，且令该些电性接触垫外露于该绝缘保护层。
前述的封装结构及其制法中，复包括形成封装层于该板体上，以令该封装层包覆该电子元件。
由上可知，本发明的封装结构及其制法中，主要藉由该电性接触垫的高度大于该导电迹线的高度，以于该电子元件设于该些电性接触垫上时，该些导电元件不会接触该导电迹线，所以能避免发生短路的问题。
附图说明
图1为现有封装结构的剖视示意图；
图1’为图1的局部放大图；
图2A至图2C为本发明封装基板的制法的剖视示意图；其中，图2B’、图2C’与图2C”为图2B及图2C的另一实施例；
图3为本发明封装结构的剖面示意图；
图3’的A-A剖面线为图3；
图3”为图3的局部放大图；
图4A为本发明封装基板的另一实施例的上视示意图；
图4B为图4A的B-B剖面线的示意图；
图4C为图4A的C-C剖面线的示意图；
图5A为本发明封装基板的另一实施例的上视示意图；以及
图5B为图5A的D-D剖面线的示意图。
符号说明
1,3封装结构
10基板
11导电迹线
13,23,23’电性接触垫
15导电凸块
16晶片
17封装胶体
2,2’,2”封装基板
20板体
20a,21a,21a’,23a’表面
21,21’第一导电迹线
22,22’,52第二导电迹线
220接点区
24绝缘保护层
25导电元件
26电子元件
27封装层
d,h,t高度
L水平路径
S斜线路径。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的封装基板2,2’的制法的剖视示意图。
如图2A所示，提供一具有多个第一导电迹线21与第二导电迹线22的板体20，且该第二导电迹线22定义有多个接点区220。
于本实施例中，该接点区220为该第二导电迹线22的端部。
如图2B所示，形成多个电性接触垫23于各该接点区220上，使该电性接触垫23的高度h大于该第一导电迹线21的高度t。
于本实施例中，以沉积或电镀制程制作该些电性接触垫23。
此外，该第一导线迹线21形成于各该电性接触垫23之间。
又，该第一导电迹线21的表面21a与该第二导电迹线22的表面齐平该板体20的表面20a；或者，如图2B’所示，藉由蚀刻制程，使该第一导电迹线21’的表面21a’与该第二导电迹线22的表面低于该板体20的表面20a，例如低于该板体20的表面20a约0至10um。
如图2C至图2C”所示，形成一如防焊层的绝缘保护层24于该板体20上，且令该些电性接触垫23与部分第一及第二导电迹线21,22外露于该绝缘保护层24(如图2C所示)、或令该些电性接触垫23与部分第二导电迹线22外露于该绝缘保护层24(如图2C”所示，藉该绝缘保护层24覆盖第一导电迹线21以提供较佳隔绝效果)。
于后续制程中，如图3所示，藉由多个如焊锡凸块的导电元件25将一电子元件26以覆晶方式设于各该电性接触垫23上，使该电子元件26藉由该些导电元件25电性连接各该电性接触垫23。接着，形成封装层27于该封装基板2的板体20上，以令该封装层27包覆该电子元件26与该些导电元件25。
于本实施例中，该电子元件26为为主动元件、被动元件或其组合者，且该主动元件例如半导体晶片，而该被动元件例如电阻、电容及电感。
此外，于其它实施例中，如图3’所示，也可增高该第二导电迹线22’，使该第二导电迹线22’的高度大于该第一导电迹线21的高度，且该第二导电迹线22’的部分区域作为该些电性接触垫23。
本发明的制法中，藉由该电性接触垫23的高度h大于该第一导电迹线21的高度t，使该电性接触垫23的表面23a(即顶面)与该第一导电迹线21的表面21a(即顶面)间的直线距离呈斜线路径S，如图3”所示，所以相较于现有技术的水平路径L，本发明的斜线路径S的长度(约31.5um)大于现有技术的水平路径L的长度(约15um)。因此，当该电子元件26设于该些电性接触垫23上时，该些导电元件25不会接触该第一导电迹线21，所以能避免该电性接触垫23与该第一导电迹线21发生桥接而短路的问题。
又，如图4A至图4C所示，若该封装基板2具有多排接点时，外露于该绝缘保护层24的各该电性接触垫23与各该第一导电迹线21可交错排列。
另外，如图5A至图5B所示，该第二导电迹线52为电源线或接地线，可于单一该第二导电迹线52上形成多个电性接触垫23。
本发明还提供一种封装结构3，包括：一封装基板2,2’,2”、设于该封装基板2,2’,2”上的一电子元件26以及一包覆该电子元件26的封装层27。
所述的封装基板2,2’,2”包括：一板体20、形成于该板体20上的多个第一导电迹线21,21’及多个电性接触垫23，使该电性接触垫23的高度h大于该第一导电迹线21,21’的高度t，且至少一该电性接触垫23旁布设有至少一该导线迹线21,21’。
所述的第一导电迹线21,21’的表面21a,21a’齐平或低于该板体20的表面20a，且该第一导电迹线21,21’的表面21a,21a’外露于该板体20的表面20a。
所述的电子元件26藉由多个导电元件25设于各该电性接触垫23上并电性连接各该电性接触垫23。
于一实施例中，该电性接触垫23形成于该第二导电迹线22的接点区220上。例如，单一该第二导电迹线52上形成有多个该电性接触垫23。
于一实施例中，所述的封装基板2,2’,2”复包括形成于该板体20上的一绝缘保护层24，且令该些电性接触垫23外露于该绝缘保护层24。
综上所述，本发明的封装结构及其制法，藉由将封装基板上的电性接触垫增高或降低该电性接触垫周围的第一导电迹线的高度，以于该电子元件设于该些电性接触垫上时，该些导电元件不会接触该第一导电迹线，所以能避免因发生桥接而短路的问题。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (26)

1.一种封装基板，包括：
板体，其具有多个导电迹线；以及
多个电性接触垫，其形成于该板体上，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线。
2.如权利要求1所述的封装基板，其特征为，该导电迹线的表面齐平或低于该板体的表面。
3.如权利要求1所述的封装基板，其特征为，该导电迹线的表面外露于该板体的表面。
4.如权利要求1所述的封装基板，其特征为，该电性接触垫形成于该导电迹线上。
5.如权利要求4所述的封装基板，其特征为，单一该导电迹线上形成有多个该电性接触垫。
6.如权利要求1所述的封装基板，其特征为，该封装基板还包括形成于该板体上的绝缘保护层，且令该些电性接触垫外露于该绝缘保护层。
7.一种封装基板的制法，包括：
提供一具有多个导电迹线的板体；以及
形成多个电性接触垫于该板体上，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线。
8.如权利要求7所述的封装基板的制法，其特征为，该导电迹线的表面齐平或低于该板体的表面。
9.如权利要求7所述的封装基板的制法，其特征为，该导电迹线的表面外露于该板体的表面。
10.如权利要求7所述的封装基板的制法，其特征为，该电性接触垫形成于该导电迹线上。
11.如权利要求10所述的封装基板的制法，其特征为，单一该导电迹线上形成有多个该电性接触垫。
12.如权利要求7所述的封装基板的制法，其特征为，该制法还包括形成绝缘保护层于该板体上，且令该些电性接触垫外露于该绝缘保护层。
13.一种封装结构，包括：
板体，其具有多个导电迹线；
多个电性接触垫，其形成于该板体上，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线；以及
电子元件，其藉由多个导电元件设于各该电性接触垫上并电性连接各该电性接触垫。
14.如权利要求13所述的封装结构，其特征为，该导电迹线的表面齐平或低于该板体的表面。
15.如权利要求13所述的封装结构，其特征为，该导电迹线的表面外露于该板体的表面。
16.如权利要求13所述的封装结构，其特征为，该电性接触垫形成于该导电迹线上。
17.如权利要求16所述的封装结构，其特征为，单一该导电迹线上形成有多个该电性接触垫。
18.如权利要求13所述的封装结构，其特征为，该结构还包括形成于该板体上的绝缘保护层，且令该些电性接触垫外露于该绝缘保护层。
19.如权利要求13所述的封装结构，其特征为，该结构还包括封装层，其包覆该电子元件。
20.一种封装结构的制法，其包括：
于一具有多个导电迹线的板体上形成多个电性接触垫，使该电性接触垫的高度大于该导电迹线的高度，且至少一该电性接触垫旁布设有至少一该导线迹线；以及
藉由多个导电元件将电子元件设于各该电性接触垫上并电性连接各该电性接触垫。
21.如权利要求20所述的封装结构的制法，其特征为，该导电迹线的表面齐平或低于该板体的表面。
22.如权利要求20所述的封装结构的制法，其特征为，该导电迹线的表面外露于该板体的表面。
23.如权利要求20所述的封装结构的制法，其特征为，该电性接触垫形成于该导电迹线上。
24.如权利要求23所述的封装结构的制法，其特征为，单一该导电迹线上形成有多个该电性接触垫。
25.如权利要求20所述的封装结构的制法，其特征为，该制法还包括形成绝缘保护层于该板体上，且令该些电性接触垫外露于该绝缘保护层。
26.如权利要求20所述的封装结构的制法，其特征为，该制法还包括形成封装层于该板体上，以令该封装层包覆该电子元件。
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