CN103258818B - 用于细小间距pop结构的系统和方法 - Google Patents

用于细小间距pop结构的系统和方法 Download PDF

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CN103258818B
CN103258818B CN201210258799.5A CN201210258799A CN103258818B CN 103258818 B CN103258818 B CN 103258818B CN 201210258799 A CN201210258799 A CN 201210258799A CN 103258818 B CN103258818 B CN 103258818B
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reflow soldering
soldering process
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CN103258818A (zh
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林正忠
林修任
陈正庭
林俊成
郑明达
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种细小间距的层叠封装件POP以及其形成方法。POP通过将连接件如焊球放置在具有半导体管芯连接到其上的第一衬底上来形成。实施第一回流焊工艺以使焊球伸长。之后,具有另一半导体管芯连接到其上的第二衬底与焊球连接。实现第二回流焊工艺以形成沙漏形连接件。本发明还公开了用于细小间距POP结构的系统和方法。

Description

用于细小间距POP结构的系统和方法
技术领域
本发明涉及半导体技术领域,具体地,涉及用于细小间距POP结构的系统和方法。
背景技术
自从发明集成电路(IC)以来,半导体工业便由于各种电子元件(即:晶体管、二极管、电阻器、电容器等)集成密度的不断提高而得到了快速发展。在很大程度上,集成密度的提高得益于最小部件尺寸不断的减小,使得更多的元件可以集成在给定区域内。
集成技术的这些进步本质上是二维(2D)的,因为集成元件占据的基本是半导体晶圆表面上的空间。虽然由于光刻技术的迅猛发展致使2DIC形成有了相当大的进步,但能在二维层面上实现的密度仍受到物理上的限制。其中一种限制就是制造这些元件所需的最小尺寸。而且,如果将更多器件放入同一芯片中,则需要更为复杂的设计。
在尝试进一步提高电路密度的过程中,人们对三维(3D)IC进行了研究。在典型的3DIC形成工艺中,两个管芯接合在一起,每个管芯与衬底上的接触焊盘之间形成电连接。例如,一种尝试涉及将两个管芯在相互的顶部接合。然后,将堆叠后的管芯接合到承载衬底,并且导线将每个管芯上的电连接接触焊盘接合到承载衬底上的接触焊盘。
另一种3D封装方法采用层叠封装(packaging-on-packaging,PoP)技术或中介层(interposer)技术来堆叠管芯以减小形成因数。PoP包括与硅中介层电连接的第一管芯,以及放置在第一管芯上方并且与硅中介层电连接的另一封装管芯。然后硅中介层电连接到另一衬底,如印刷电路板。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种半导体器件,包括:
第一衬底,所述第一衬底具有连接到其的第一半导体管芯;
第二衬底,所述第二衬底具有连接到其的第二半导体管芯;以及
将所述第一衬底电连接到所述第二衬底的多个电连接件,所述多个电连接件中的每一个的高宽比都在约1到约4之间。
在可选实施例中,所述多个电连接件中的每一个在中部区域的宽度都小于与所述第一衬底和所述第二衬底相邻区域的宽度。
在可选实施例中,所述多个电连接件中的每一个都具有与外部部分不同的内芯。
在可选实施例中,所述内芯包括Cu芯。
在可选实施例中,所述内芯包括塑料芯。
在可选实施例中,所述半导体器件进一步包括位于所述第一衬底与所述第二衬底之间的模制底部填充物。
根据本发明的另一个方面,提供了一种半导体器件,包括:
第一衬底,所述第一衬底具有连接到其的第一半导体管芯;
第二衬底,所述第二衬底具有连接到其的第二半导体管芯;以及
将所述第一衬底电连接到所述第二衬底的多个电连接件,所述多个电连接件中的每一个都具有沙漏形状。
在可选实施例中,所述多个电连接件中的每一个的高宽比都在约1到约4之间。
在可选实施例中,所述多个电连接件中的每一个都具有与外部部分不同的内芯。
在可选实施例中,所述内芯包括Cu芯。
在可选实施例中,所述内芯包括塑料芯。
根据本发明的又一方面,提供了一种形成半导体器件的方法,所述方法包括:
提供第一衬底,所述第一衬底具有连接到其的第一半导体管芯;
提供第二衬底,所述第二衬底具有连接到其的第二半导体管芯;
将多个电连接件放置在所述第一衬底上;
实施第一回流焊工艺以使所述多个电连接件伸长;
使所述第二衬底与所述多个电连接件接触;
实施第二回流焊工艺,从而使所述多个电连接件中的每一个都形成以下形状:中部区域中具有宽度宽于与所述第一衬底和所述第二衬底接触区域的宽度的部分。
在可选实施例中,所述第一回流焊工艺包括感应回流焊工艺。
在可选实施例中,所述第二回流焊工艺包括感应回流焊工艺。
在可选实施例中,所述多个电连接件中的每一个都包括与外部材料不同的内芯区域。
在可选实施例中,所述第一回流焊工艺对所述外部材料进行回流焊,且不会对所述内芯再成形。
在可选实施例中,所述第二回流焊工艺对所述外部材料进行回流焊,且不会对所述内芯再成形。
在可选实施例中,所述内芯包括铜。
在可选实施例中,所述方法进一步包括在所述第一衬底的表面上形成模塑底部填充物。
在可选实施例中,实施所述第二回流焊工艺直到所述电连接件形成沙漏形状为止。
附图说明
为更完整的理解实施例及其优点,现将结合附图所进行的以下描述作为参考,其中:
图1-5示出了形成一个实施例的各个中间阶段。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
首先参考图1,示出了根据一个实施例的第一衬底108和第二衬底104的截面图。在一个实施例中,第一衬底108是封装件100的部件,封装件100可包括,例如,通过第一组导电连接件110安装在第一衬底108上的第一集成电路管芯106。第一组导电连接件110可包括,例如,无铅焊料、共晶铅、导电柱以及它们的组合等。
第一衬底108可以是例如封装衬底、印刷电路板、高密度互连板等。通孔(TV)(未示出)可用于提供第一集成电路管芯106与第一衬底108的背面上的第一组导电部件112之间的电连接。第一衬底108还可包括在第一衬底108的一个或两个表面内和/或上的再分布线(RDL)(未示出),以允许不同的引脚配置和更多的电连接。元件上方还可以形成密封材料或包胶模(overmold)114,以保护元件免受环境及外部污染物的污染。
根据一个实施例,第二衬底104还可以具有安装在其上的第二集成电路管芯102。封装件100将电连接第二衬底104,从而形成层叠封装件(PoP),这一点将在下文详细论述。
第二衬底104进一步包括第二组导电部件116,其与安装在第二衬底104上的第二集成电路管芯102位于第二衬底104的同一表面上;以及第三组导电部件118,沿第二衬底104的与第二集成电路管芯102相对的表面。在本实施例中,第二衬底104通过一组后续形成的导电连接件提供第一集成电路管芯106与第二集成电路管芯102之间的电连接,和/或第二衬底104的第三组导电部件118与第一集成电路管芯106和第二集成电路管芯102之一或二者之间的电连接(见图5)。第二衬底104中的TV(未示出)提供第二组导电部件116与第三组导电部件118之间的电连接。第二衬底104还可包括位于第二衬底104的一个或两个表面内和/或上的RDL(未示出),以允许不同的引脚配置和更多的电连接。在一个实施例中,第二衬底104可以是任何合适的衬底,如硅衬底、有机衬底、陶瓷衬底、介电衬底、层压衬底等。
如图1所示,第二集成电路管芯102通过第二组导电连接件120电连接到第二衬底104上的第二组导电部件116中的部分导电部件上。第二组导电连接件120可包括(例如)无铅焊料、共晶铅、导电柱以及它们的组合等。
第二集成电路管芯102和第一集成电路管芯106可以是用于特定应用的任何适合的集成电路管芯。例如,第二集成电路管芯102和第一集成电路管芯106之一可是存储芯片(如DRAM、SRAM、NVRAM和/或类似芯片),另一管芯则可是逻辑电路。
现在参考图2,根据一个实施例,焊剂230施加在第二衬底104的表面上,第三组导电连接件232被施加成与第二组导电部件116电接触。焊剂230可以(例如)浸渍操作方式施加,在该操作中第二衬底104的表面浸渍在焊剂中。焊剂有助于清洁第二组导电部件116的表面,从而有助于在第二组导电部件116与第三组导电连接件232之间形成电接触。
在一个实施例中,第三组导电连接件232包括一个具有较软外表面的内芯。例如,第三组导电连接件232可以是Cu芯或塑料芯的焊球。在该实施例中,焊球具有Cu芯或塑料芯,并且该芯包覆有焊料外表面(如共晶焊料、无铅焊料)或类似外表面。焊料外表面的熔融温度低于内芯,使得在后续的回流焊工艺期间,焊球的外部形状重新形成时,内芯的形状可以保持不变。
图3示出了根据某一实施例的在第一回流焊工艺后的第三组导电连接件232。如图2和图3所示,第一回流焊工艺致使第三组导电连接件232从图2中的相对球形变为图3中的子弹形。在一个实施例中,采用感应回流焊工艺来实施第一回流焊工艺。可实施感应回流焊工艺使得磁场(图3中用虚线336表示)与第二衬底104的主面垂直。以这种方式实施感应回流焊工艺有助于使第三组导电连接件232伸长(如连接器的焊料外表面)。可以对感应回流焊工艺期间使用的电流进行调整,以便得到特定应用所需的形状。然而,在其他实施例中,也可以使用其他回流焊工艺,如快速热处理(RTP)、红外线(IR)等。
图3进一步示出了根据一个实施例的施加在第二衬底104上的模塑料340的形成。在一个实施例中,模塑料340是模塑底部填充物(MUF),包括例如聚合物、环氧树脂或类似物。模塑料340可以和第二集成电路管芯102的顶面和边缘接触。可以采用例如压缩模塑或传递模塑将模塑料340模塑到第二集成电路管芯102和第二衬底104上。在图3所示的实施例中,模塑料340的顶面与第二集成电路管芯102的顶面共面。在其他实施例中,模塑料340的顶面可高于第二集成电路管芯102的顶面,使得第二集成电路管芯102可以完全封装在模塑料340内。还可以实施研磨工艺或抛光工艺以去除模塑料340在第二集成电路管芯102的顶面上方的部分,从而暴露出第二集成电路管芯102。
图4示出了根据一个实施例的将第一衬底108的第一组导电部件112与第三组导电连接件232(例如焊球)接触的初始接合步骤后的封装件100。还可以使用焊剂(图4中未示出)清洁第一衬底108的第一组导电部件112和/或第三组导电连接件232的表面,这有助于电连接的形成。
图5示出了根据一实施例的实施第二回流焊工艺后的第三组导电连接件232的形状。如图5所示,第二回流焊工艺使得第三组导电连接件232具有沙漏形状。在一个实施例中,采用感应回流焊工艺来实施第二回流焊工艺时,使得磁场(图5中用虚线542表示)与第二衬底104的主面垂直。以这种方式实施感应回流焊工艺有助于使第三组导电连接件232伸长(如连接器的焊料外表面)。使第三组导电连接件232的外部部分伸长部分有助于形成图5所示的沙漏形状。可以对感应回流焊工艺期间使用的电流进行调整,以便得到特定应用所需的形状。然而,在其他实施例中,也可以使用其他回流焊工艺,如RTP、IR等。
在一个实施例中,第三组导电连接件232中的各个具有沿中部宽度W,和高度H,如图5所示。在一个实施例中,H与W之比(H/W)在大约1.0到大约4.0之间。已经发现,形成连接,诸如利用前面所述的回流焊工艺来得到子弹形和然后沙漏形的连接,可以使连接器的密度更高。例如,通过利用相对长且窄的连接件,连接件可以是足够高以适应如图5所示的PoP的配置,不过仍具有高密度来适应工业中半导体器件尺寸减小的趋势。沙漏形的使用还可以降低相邻连接器共同短路的可能性。
应当理解,以上描述为实施例的一般性描述,实施例可以包含许多其他部件。例如,实施例可以包括凸块下金属化层、钝化层、模塑料、另外的管芯和/或衬底等。此外,第一集成电路管芯106和第二集成电路管芯102的结构、放置与布置仅是示例,因而,其他实施例可以使用不同的结构、放置和布置。
还应当理解,上述讨论的各个步骤的顺序仅是示例,同样,其他实施例可以采用不同的顺序。不同顺序的步骤将包含在实施例的范围内。
在一个实施例中,第一衬底108上的第一组导电部件112和第二衬底104上的第二组导电部件116和第三组导电部件118可以以球栅阵列(BGA)排列方式布置。
其后,可以使用其他常规工艺来完成封装件100。例如,第二衬底104可以连接到另一衬底,如印刷电路板(PCB)、高密度互连板、硅衬底、有机衬底、陶瓷衬底、介电衬底、层压衬底、另一半导体封装件等。
在一个实施例中,提供了半导体器件。该半导体器件包括第一衬底,具有连接到其的第一半导体管芯;第二衬底,具有连接到其的第二半导体管芯,以及将第一衬底电连接到第二衬底的多个电连接件。所述多个电连接件中的每一个的高宽比都在约1到约4之间。
在另一实施例中,提供了半导体器件。该半导体器件包括第一衬底,具有连接到其的第一半导体管芯;第二衬底,具有连接到其的第二半导体管芯,以及将第一衬底电连接到第二衬底的多个电连接件。这些电连接件中的每一个都具有沙漏形状。
在另一实施例中,提供了一种形成半导体器件的方法。该方法包括提供第一衬底,该第一衬底具有连接到其的第一半导体管芯;提供第二衬底,该第二衬底具有连接到其的第二半导体管芯;将多个电连接件放置在第一衬底上;实施第一回流焊工艺以使所述多个电连接件伸长;使第二衬底与所述多个电连接件接触;实施第二回流焊工艺,从而使所述多个电连接件中的每一个都形成如下形状:中部区域的宽度比与第一衬底和第二衬底接触区域的宽度宽。
尽管已经详细地描述了本发明及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,做各种不同的改变,替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员通过本发明应理解,现有的或今后开发的执行与本发明所采用的相应实施例基本相同的功能或实现基本相同结果的工艺、机器、制造,材料组分、装置、方法或步骤根据本发明可以被使用。因此,所附权利要求旨在将这样的工艺、机器、制造、材料组分、装置、方法或步骤包括在范围内。

Claims (9)

1.一种形成半导体器件的方法,所述方法包括:
提供第一衬底,所述第一衬底具有连接到其的第一半导体管芯;
提供第二衬底,所述第二衬底具有连接到其的第二半导体管芯;
将多个电连接件放置在所述第一衬底上;
实施第一回流焊工艺以使所述多个电连接件伸长;
在实施所述第一回流焊工艺之后,使所述第二衬底与所述多个电连接件接触;
在所述接触之后,实施第二回流焊工艺,从而使所述多个电连接件中的每一个都形成以下形状:中部区域中具有宽度窄于与所述第一衬底和所述第二衬底接触区域的宽度的部分。
2.根据权利要求1所述的方法,其中所述第一回流焊工艺包括感应回流焊工艺。
3.根据权利要求1所述的方法,其中所述第二回流焊工艺包括感应回流焊工艺。
4.根据权利要求1所述的方法,其中所述多个电连接件中的每一个都包括与外部材料不同的内芯区域。
5.根据权利要求4所述的方法,其中所述第一回流焊工艺对所述外部材料进行回流焊,且不会对所述内芯再成形。
6.根据权利要求4所述的方法,其中所述第二回流焊工艺对所述外部材料进行回流焊,且不会对所述内芯再成形。
7.根据权利要求4所述的方法,其中所述内芯包括铜。
8.根据权利要求1所述的方法,进一步包括在所述第一衬底的表面上形成模塑底部填充物。
9.根据权利要求1所述的方法,其中实施所述第二回流焊工艺直到所述电连接件形成沙漏形状为止。
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