TW201401446A - 基板結構與使用該基板結構之半導體封裝件 - Google Patents

基板結構與使用該基板結構之半導體封裝件 Download PDF

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TW201401446A
TW201401446A TW101122596A TW101122596A TW201401446A TW 201401446 A TW201401446 A TW 201401446A TW 101122596 A TW101122596 A TW 101122596A TW 101122596 A TW101122596 A TW 101122596A TW 201401446 A TW201401446 A TW 201401446A
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semiconductor package
substrate
width
electrical contact
line
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TWI495052B (zh
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林長甫
蔡和易
姚進財
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矽品精密工業股份有限公司
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Priority to CN201210238506.7A priority patent/CN103515329B/zh
Priority to US13/654,713 priority patent/US9368467B2/en
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Abstract

一種基板結構與半導體封裝件，該基板結構係包括基板本體以及形成於該基板本體上的複數線路，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該線路係於電性接點處縮減其寬度。本發明係有效達到細線寬/細線距與微型化之目的，並可增進產品可靠度，且降低製造成本。

Description

基板結構與使用該基板結構之半導體封裝件
本發明係有關於一種基板結構與半導體封裝件，尤指一種用於覆晶封裝之基板結構與半導體封裝件。
由於電子產品的設計愈來愈朝向輕薄短小、多功能及高頻工作效能的趨勢前進，因此電路板或封裝基板亦必須往細線寬/細線距(fine line/fine pitch)的方向發展，且因為覆晶式半導體封裝件的接腳數遠大於打線式半導體封裝件的接腳數，所以逐漸以覆晶式半導體封裝件取代打線式半導體封裝件。
第1圖所示者，係習知覆晶式封裝基板之俯視圖，該封裝基板1之用以接置半導體晶片的電性接點111須設置於線路11之一端，且該電性接點111的尺寸大於線路11的尺寸，因此線路11之佈線密度往往會受限於電性接點111的大小，而無法製作細線寬/細線距之產品，故於固定的封裝基板面積之情況下，其佈線密度無法提升，而導致半導體封裝件的效能受限。
為解決前述問題，業界遂開發出一種應用於覆晶式封裝基板的BOT(Ball on Trace)技術，如第2圖所示，亦即封裝基板2之線路於接置半導體晶片處無須設置電性接點，故線路21之佈線密度不受電性接點大小之限制，但是為了避免銲球22與線路21間的接觸面積過小，業界運用BOT技術時，往往會於線路21欲接至銲球22處稍微設計 寬一些，以增加覆晶之接著強度，使產品可靠度增加，但是這樣部分較寬的線路21還是會使封裝基板2之佈線密度受到一定的限制。
此外，由於封裝件產品之佈線密度提升，且半導體晶片之電極墊數目增加，故用以接置於線路21上之銲球22其體積亦相對縮小，而導致銲球22與線路21間之接著強度下降，進而產生可靠度問題。
因此，如何避免上述習知技術中之種種問題，實已成目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種基板結構，係包括：基板本體；以及複數線路，係形成於該基板本體上，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有縮減之寬度。
本發明復提供一種使用該基板結構之半導體封裝件，係包括：該基板結構；以及半導體晶片，係覆晶接置於該基板本體上，該半導體晶片具有複數電極墊，且該電極墊與基板本體間具有導電凸塊，並使該導電凸塊結合至該電性接點上，俾令該半導體晶片藉該導電凸塊電性連接該複數線路。
由上可知，由於本發明係在保持大部分的線路區域寬度不變的情況下，僅使少數線路區域變細而作為電性接點；相較於習知將電性接點處的寬度保持不變，而去縮小大部分線路區域寬度的基板(同一基板面積下，線與線之排 列密度係由每條線路最寬處決定)，本發明之線路的製造難度大為下降，使得封裝基板的製造良率上升，進而減低製造成本。再者，本發明亦能提供較強之半導體晶片接合強度，而可提升半導體封裝件的可靠度。而且，本發明可加大相鄰線路間之電性接點間的間距，以達成高密度線路與細線寬/細線距之目的。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「端」、「側」、「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第3A、3B與3C圖所示者，分別係本發明之基板結構與半導體封裝件之立體圖、俯視圖與剖視圖；其中，第3C圖係沿俯視圖第3B圖之剖面線AA之剖視圖，第3A與3B 圖係省略部分構件，且第3A圖係迴銲前之狀態，第3B與3C圖係迴銲後之狀態。
如第3A至3C圖所示，本發明係提供一可為封裝基板或電路板的基板本體30，於該基板本體30上形成有複數線路31，又，用以和外部元件電性連接之該複數線路31係具有電性接點311，其中，該線路31係於電性接點311處縮減其寬度。
於本實施例中，係將電性接點的寬度縮減至如同第2圖之較細線路的寬度，並將線路加寬至如同第2圖之較寬線路的寬度，且使得該線路31較佳係於電性接點311處縮減其寬度至原來的百分之七十至九十。
又本實施例係令該線路31從其寬度方向之相對兩側表面內縮，而具有縮減之寬度，但不以此為限。
此外，另提供一半導體晶片32，係覆晶接置於該基板本體30上，該半導體晶片32之一表面具有複數電極墊321，於該半導體晶片32具有該電極墊321之表面上形成有絕緣保護層33，且該絕緣保護層33具有複數對應外露各該電極墊321的絕緣保護層開孔330，於該電極墊321上可視情況地形成有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)34，並可於該凸塊底下金屬層34上形成有導電凸塊35，該導電凸塊35之端部係位於該電性接點311上，並電性連接該線路31，且於該半導體晶片32與基板本體30之間形成有底膠36。
於本實施例中，該導電凸塊35係包括金屬柱351與 位於其一端上的銲料352，且該銲料352係位於該電性接點311上；或者，於其他實施例中，該導電凸塊35可為銲料。
再參照第3B圖，可知該導電凸塊35之端部除了連接該電性接點311的頂面311a外，該導電凸塊35之端部亦連接該電性接點311的側表面311b與相接該側表面311b之線路斷面310，即該導電凸塊35與電性接點311之接觸面共有一頂面311a、二側表面311b與二線路斷面310，電性接點提供與導電凸塊35結合之接觸面積顯較習知技術為多，故可增進導電凸塊35與電性接點311間的接合強度。
此外，由第3B圖可知，因為該線路31係於電性接點311處縮減其寬度，而使得相鄰電性接點311之距離增加，且縮減寬度後所形成的空間可容納部分該銲料352，而不易有相鄰之電性接點彼此橋接的問題，所以電性接點間的間距可縮小，達成高密度線路與細線寬/細線距之目的。
綜上所述，相較於習知技術，由於本發明係在大部分的線路區域寬度不變的情況下，僅使少數線路區域變細而作為電性接點；相較於習知將電性接點處的寬度保持不變，而去縮小大部分線路區域寬度的基板(同一基板面積下，線與線之排列密度係由每條線路最寬處決定)，本發明之線路的製造難度大為下降，使得封裝基板的製造良率上升，進而減低製造成本。再者，本發明亦能提供較強之半導體晶片接合強度，而可提升半導體封裝件的可靠度。而且，本發明可加大相鄰線路間之電性接點間的間距，以達 成高密度線路與細線寬/細線距之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2‧‧‧封裝基板
11,21,31‧‧‧線路
111,311‧‧‧電性接點
22‧‧‧銲球
30‧‧‧基板本體
310‧‧‧線路斷面
311a‧‧‧頂面
311b‧‧‧側表面
32‧‧‧半導體晶片
321‧‧‧電極墊
33‧‧‧絕緣保護層
330‧‧‧絕緣保護層開孔
34‧‧‧凸塊底下金屬層
35‧‧‧導電凸塊
351‧‧‧金屬柱
352‧‧‧銲料
36‧‧‧底膠
第1圖係一種習知覆晶式封裝基板之俯視圖；第2圖係另一種習知覆晶式封裝基板之立體圖；以及第3A、3B與3C圖分別係本發明之基板結構與半導體封裝件之立體圖、俯視圖與剖視圖；其中，第3C圖係沿俯視圖第3B圖之剖面線AA之剖視圖。
30‧‧‧基板本體
31‧‧‧線路
311‧‧‧電性接點
35‧‧‧導電凸塊

Claims (13)

  1. 一種基板結構，係包括：基板本體；以及複數線路，係形成於該基板本體上，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有縮減之寬度。
  2. 如申請專利範圍第1項所述之基板結構，其中，該電性接點之寬度為該線路寬度的百分之七十至九十。
  3. 如申請專利範圍第1項所述之基板結構，其中，該線路係從其寬度方向之相對兩側表面內縮，而具有縮減之寬度。
  4. 一種半導體封裝件，係包括：基板結構，包括有：基板本體；以及複數線路，係形成於該基板本體上，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有縮減之寬度；以及半導體晶片，係覆晶接置於該基板本體上，該半導體晶片具有複數電極墊，且該電極墊與基板本體間具有導電凸塊，並使該導電凸塊結合至該電性接點上，俾令該半導體晶片藉該導電凸塊電性連接該複數線路。
  5. 如申請專利範圍第4項所述之半導體封裝件，其中，該電性接點之寬度為該線路寬度的百分之七十至九 十。
  6. 如申請專利範圍第4項所述之半導體封裝件，其中，該線路係從其寬度方向之相對兩側表面內縮，而具有縮減之寬度。
  7. 如申請專利範圍第4項所述之半導體封裝件，其中，該導電凸塊之端部係連接該電性接點的側表面與相接該側表面之線路斷面。
  8. 如申請專利範圍第4項所述之半導體封裝件，其中，該導電凸塊係包括金屬柱與位於其一端上的銲料，以供該銲料結合於該電性接點上。
  9. 如申請專利範圍第4項所述之半導體封裝件，其中，該導電凸塊係為銲料。
  10. 如申請專利範圍第4項所述之半導體封裝件，復包括底膠，係形成於該半導體晶片與基板本體之間。
  11. 如申請專利範圍第4項所述之半導體封裝件，其中，該半導體晶片具有該電極墊之表面上復形成有絕緣保護層，且該絕緣保護層具有複數對應外露各該電極墊的絕緣保護層開孔。
  12. 如申請專利範圍第4項所述之半導體封裝件，其中，該電極墊與導電凸塊之間復形成有凸塊底下金屬層。
  13. 如申請專利範圍第4項所述之半導體封裝件，其中，該基板本體係為封裝基板或電路板。
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