TW201401456A - 基板結構與封裝結構 - Google Patents

基板結構與封裝結構 Download PDF

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TW201401456A
TW201401456A TW101121874A TW101121874A TW201401456A TW 201401456 A TW201401456 A TW 201401456A TW 101121874 A TW101121874 A TW 101121874A TW 101121874 A TW101121874 A TW 101121874A TW 201401456 A TW201401456 A TW 201401456A
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substrate
package structure
substrate body
package
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TW101121874A
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林長甫
陳錦德
姚進財
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矽品精密工業股份有限公司
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Priority to TW101121874A priority Critical patent/TW201401456A/zh
Priority to CN201210238451.XA priority patent/CN103515345A/zh
Priority to US13/654,780 priority patent/US20130334684A1/en
Publication of TW201401456A publication Critical patent/TW201401456A/zh

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Abstract

一種基板結構與封裝結構，該基板結構係包括基板本體以及複數線路，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有線路凹槽。本發明係有效達到細線寬/細線距與微型化之目的，並可增進產品可靠度。

Description

基板結構與封裝結構
本發明係有關於一種基板結構與封裝結構，尤指一種覆晶封裝之基板結構與封裝結構。
由於電子產品的設計愈來愈朝向輕薄短小的趨勢前進，因此電路板或封裝基板亦必須往細線寬/細線距(fine line/fine pitch)的方向發展。
請參閱第1A與1B圖，分別係習知基板結構與封裝結構之示意圖，其中，第1A圖係沿俯視圖第1B圖之剖面線AA之剖視圖，且第1B圖係省略部分構件。
如圖所示，習知之覆晶製程係先提供一可為封裝基板或電路板的基板本體10，於該基板本體10之一表面上形成有複數線路11，該線路11之末端係具有面積較大的電性接點111，以供對外之電性連接。
再者，另提供一半導體晶片12，係覆晶接置於該基板本體10上，該半導體晶片12之一表面具有複數電極墊121，於該半導體晶片12具有該電極墊121之表面上形成有絕緣保護層13，且該絕緣保護層13具有複數對應外露各該電極墊121的絕緣保護層開孔130，於該電極墊121上形成有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)14，並於該凸塊底下金屬層14上形成有金屬柱15，該金屬柱15之端部上係形成有銲料16，該電極墊121係藉其上之銲料16對應電性連接該線路11之電性接點111。
惟，由於該等電性接點111的尺寸較該線路11為大，因此在電路板或封裝基板上的該等線路11須為細線寬/細線距的要求之下，該等電性接點111間的間距會相當狹窄，而在以銲料16連接半導體晶片12時，會容易因為半導體晶片12之對位偏移或金屬柱15上之銲料16因加熱接置於電性接點111時下壓，而發生銲料16橋接(solder bridge)問題，進而使產品發生電性異常之可靠度問題。
因此，如何避免上述習知技術中之種種問題，實已成目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種基板結構，係包括：基板本體；複數線路，係形成於該基板本體之一表面上，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有線路凹槽。
本發明復提供一種封裝結構，係包括：基板本體；複數線路，係形成於該基板本體之一表面上，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有線路凹槽；以及半導體晶片，係覆晶接置於該基板本體上，該半導體晶片之一表面具有複數電極墊，各該電極墊上形成有導電凸塊，該導電凸塊之端部係位於該線路凹槽處，並電性連接該線路。
由上可知，由於本發明之導電凸塊係可直接嵌入至線路斷開部所形成的下凹空間中，所以能提升對位精度，又該下凹空間中可容納導電凸塊的端部，並使整體封裝結構 的高度降低；又下凹空間可容納導電凸塊的端部，則不易有相鄰之電性接點彼此橋接的問題。基於前述優點，故可減少填充於晶片與基板本體間之底膠的用量，進而具有輕薄化與低成本的優點。再者，本發明之導電凸塊係進一步連接線路的斷面，故可增進導電凸塊與線路間的接合強度(由於線路具凹部，故導電凸塊與線路間之接觸表面增加)；而且，本發明之電性接點無須如習知般增大面積，且銲料被該線路斷開部所限制而不易溢流，所以電性接點間的間距及線路間的間距可縮小，達成高密度線路與細線寬/細線距之目的，使封裝件之效性功能增加。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「端」、「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可 實施之範疇。
請參閱第2A與2B圖，分別係本發明之基板結構與封裝結構之示意圖。
如第2A圖所示，本發明係提供一可為封裝基板或電路板的基板本體20，於該基板本體20之一表面上形成有複數線路21，又，用以和外部元件電性連接之該複數線路21係具有電性接點211，其中，該電性接點211具有線路斷開部212，以外露該基板本體20之表面，以供對外之電性連接。
此外，另提供一半導體晶片22，係覆晶接置於該基板本體20上，該半導體晶片22之一表面具有複數電極墊221，於該半導體晶片22具有該電極墊221之表面上形成有絕緣保護層23，且該絕緣保護層23具有複數對應外露各該電極墊221的絕緣保護層開孔230，於該電極墊221上可視情況地形成有凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)24，並可於該凸塊底下金屬層24上形成有導電凸塊25，該導電凸塊25之端部係對位於該線路斷開部212處，並電性連接該線路21，且於該半導體晶片22與基板本體20之間形成有底膠26。
於本實施例中，該導電凸塊25係包括金屬柱251與位於其一端上的銲料252，且該銲料252係位於該線路斷開部212處；或者，於其他實施例中，該導電凸塊25可為銲料。
請同時參照第2B圖，可知該導電凸塊25的端部係直 接嵌入在該線路斷開部212所形成的下凹空間中，且連接該線路21之斷面(側表面)；其中，第2A圖係沿俯視圖第2B圖之剖面線BB之剖視圖，且第2B圖係省略部分構件。
另外，該線路之線路斷開部可於製作線路時利用如微影等圖案化製程所形成，且該線路斷開部可如第2A圖所示為完全截斷線路的情況，亦可為不截斷線路而僅形成開孔的態樣，亦或製作成具有一缺口之情況，如U字型。
要補充說明的是，該線路斷開部亦可改用未斷開之線路凹槽取代，且該線路凹槽之深度約為線路厚度的三分之二，惟此係本發明所屬技術領域中具有通常知識者依據本說明書而能瞭解者，故不在此加以贅述與圖示。
綜上所述，相較於習知技術，由於本發明之導電凸塊係可直接嵌入至線路斷開部所形成的下凹空間中，所以能提升對位精度，又該下凹空間中可容納導電凸塊的端部，並使整體封裝結構的高度降低；又下凹空間可容納導電凸塊的端部，則不易有相鄰之電性接點彼此橋接的問題。基於前述優點，故可減少填充於晶片與基板本體間之底膠的用量，進而具有輕薄化與低成本的優點；再者，本發明之導電凸塊係進一步連接線路的斷面，故可增進導電凸塊與線路間的接合強度(由於線路具凹部，故導電凸塊與線路間之接觸表面增加)；而且，本發明之電性接點無須如習知般增大面積，且銲料被該線路斷開部所限制而不易溢流，所以電性接點間的間距及線路間的間距可縮小，達成高密度線路與細線寬/細線距之目的，使封裝件之效性功能增加。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10,20‧‧‧基板本體
11,21‧‧‧線路
111‧‧‧電性接點
12,22‧‧‧半導體晶片
121,221‧‧‧電極墊
13,23‧‧‧絕緣保護層
130,230‧‧‧絕緣保護層開孔
14,24‧‧‧凸塊底下金屬層
15,251‧‧‧金屬柱
16,252‧‧‧銲料
211‧‧‧電性接點
212‧‧‧線路斷開部
25‧‧‧導電凸塊
26‧‧‧底膠
AA,BB‧‧‧剖面線
第1A與1B圖分別係習知基板結構與封裝結構之示意圖，其中，第1A圖係沿俯視圖第1B圖之剖面線AA之剖視圖；以及第2A與2B圖分別係本發明之基板結構與封裝結構之示意圖，其中，第2A圖係沿俯視圖第2B圖之剖面線BB之剖視圖。
20‧‧‧基板本體
21‧‧‧線路
211‧‧‧電性接點
212‧‧‧線路斷開部
22‧‧‧半導體晶片
221‧‧‧電極墊
23‧‧‧絕緣保護層
230‧‧‧絕緣保護層開孔
24‧‧‧凸塊底下金屬層
251‧‧‧金屬柱
252‧‧‧銲料
25‧‧‧導電凸塊
26‧‧‧底膠

Claims (12)

  1. 一種基板結構，係包括：基板本體；以及複數線路，係形成於該基板本體之一表面上，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有線路凹槽。
  2. 如申請專利範圍第1項所述之基板結構，其中，該線路凹槽係為線路斷開部，以外露該基板本體之表面。
  3. 如申請專利範圍第1項所述之基板結構，其中，該基板本體係為封裝基板或電路板。
  4. 一種封裝結構，係包括：基板本體；複數線路，係形成於該基板本體之一表面上，且至少一該線路具有電性接點，俾用以和外部元件電性連接，其中，該電性接點具有線路凹槽；以及半導體晶片，係覆晶接置於該基板本體上，該半導體晶片之一表面具有複數電極墊，各該電極墊上形成有導電凸塊，該導電凸塊之端部係位於該線路凹槽處，並電性連接該線路。
  5. 如申請專利範圍第4項所述之封裝結構，其中，該線路凹槽係為線路斷開部，以外露該基板本體之表面。
  6. 如申請專利範圍第4項所述之封裝結構，其中，該導電凸塊之端部係連接該線路之斷面。
  7. 如申請專利範圍第4項所述之封裝結構，其中，該導 電凸塊係包括金屬柱與位於其一端上的銲料，且該銲料係位於該線路凹槽處。
  8. 如申請專利範圍第4項所述之封裝結構，其中，該導電凸塊係為銲料。
  9. 如申請專利範圍第4項所述之封裝結構，復包括底膠，係形成於該半導體晶片與基板本體之間。
  10. 如申請專利範圍第4項所述之封裝結構，其中，該半導體晶片具有該電極墊之表面上復形成有絕緣保護層，且該絕緣保護層具有複數對應外露各該電極墊的絕緣保護層開孔。
  11. 如申請專利範圍第4項所述之封裝結構，其中，該電極墊與導電凸塊之間復形成有凸塊底下金屬層。
  12. 如申請專利範圍第4項所述之封裝結構，其中，該基板本體係為封裝基板或電路板。
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