CN103515345A - 基板结构与封装结构 - Google Patents

基板结构与封装结构 Download PDF

Info

Publication number
CN103515345A
CN103515345A CN201210238451.XA CN201210238451A CN103515345A CN 103515345 A CN103515345 A CN 103515345A CN 201210238451 A CN201210238451 A CN 201210238451A CN 103515345 A CN103515345 A CN 103515345A
Authority
CN
China
Prior art keywords
circuit
substrate body
conductive projection
encapsulating structure
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201210238451.XA
Other languages
English (en)
Inventor
林长甫
陈锦德
姚进财
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN103515345A publication Critical patent/CN103515345A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/82385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一种基板结构与封装结构，该基板结构包括基板本体以及多条线路，且至少一该线路具有电性接点，用以和外部组件电性连接，其中，该电性接点具有线路凹槽。本发明能有效达到细线宽/细线距与微型化的目的，并可增进产品可靠度。

Description

基板结构与封装结构
技术领域
本发明涉及一种基板结构与封装结构，尤指一种覆晶封装的基板结构与封装结构。
背景技术
由于电子产品的设计愈来愈朝向轻薄短小的趋势前进，因此电路板或封装基板亦必须往细线宽/细线距（fine line/fine pitch）的方向发展。
请参阅图1A与图1B，分别为现有基板结构与封装结构的示意图，其中，图1A为沿俯视图图1B的剖面线AA的剖视图，且图1B省略部分构件。
如图所示，现有的覆晶工艺先提供一可为封装基板或电路板的基板本体10，于该基板本体10的一表面上形成有多条线路11，该线路11的末端具有面积较大的电性接点111，以供对外的电性连接。
此外，另提供一半导体芯片12，其覆晶接置于该基板本体10上，该半导体芯片12的一表面具有多个电极垫121，于该半导体芯片12具有该电极垫121的表面上形成有绝缘保护层13，且该绝缘保护层13具有多个对应外露各该电极垫121的绝缘保护层开孔130，于该电极垫121上形成有凸块底下金属层（Under Bump Metallurgy，简称UBM）14，并于该凸块底下金属层14上形成有金属柱15，该金属柱15的端部上形成有焊料16，该电极垫121借其上的焊料16对应电性连接该线路11的电性接点111。
但是，由于该等电性接点111的尺寸较该线路11为大，因此在电路板或封装基板上的该等线路11须为细线宽/细线距的要求之下，该等电性接点111间的间距会相当狭窄，而在以焊料16连接半导体芯片12时，会容易因为半导体芯片12的对位偏移或金属柱15上的焊料16因加热接置于电性接点111时下压，而发生焊料16桥接（solder bridge）问题，进而使产品发生电性异常的可靠度问题。
因此，如何避免上述现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
有鉴于上述现有技术的不足，本发明的主要目的在于提供一种基板结构与封装结构，有效达到细线宽/细线距与微型化的目的，并可增进产品可靠度。
本发明的基板结构，包括：基板本体；多条线路，其形成于该基板本体的一表面上，且至少一该线路具有电性接点，用以和外部组件电性连接，其中，该电性接点具有线路凹槽。
本发明还提供一种封装结构，其包括：基板本体；多条线路，其形成于该基板本体的一表面上，且至少一该线路具有电性接点，用以和外部组件电性连接，其中，该电性接点具有线路凹槽；以及半导体芯片，其覆晶接置于该基板本体上，该半导体芯片的一表面具有多个电极垫，各该电极垫上形成有导电凸块，该导电凸块的端部位于该线路凹槽处，并电性连接该线路。
由上可知，由于本发明的导电凸块可直接嵌入至线路断开部所形成的下凹空间中，所以能提升对位精度，又该下凹空间中可容纳导电凸块的端部，并使整体封装结构的高度降低；又下凹空间可容纳导电凸块的端部，则不易有相邻的电性接点彼此桥接的问题。基于前述优点，故可减少填充于芯片与基板本体间的底胶的用量，进而具有轻薄化与低成本的优点。此外，本发明的导电凸块进一步连接线路的断面，故可增进导电凸块与线路间的接合强度(由于线路具凹部，故导电凸块与线路间的接触表面增加)；而且，本发明的电性接点无须如现有般增大面积，且焊料被该线路断开部所限制而不易溢流，所以电性接点间的间距及线路间的间距可缩小，达成高密度线路与细线宽/细线距的目的，使封装件的效性功能增加。
附图说明
图1A与图1B分别为现有基板结构与封装结构的示意图，其中，图1A为沿俯视图图1B的剖面线AA的剖视图。
图2A与图2B分别为本发明的基板结构与封装结构的示意图，其中，图2A为沿俯视图图2B的剖面线BB的剖视图。
主要组件符号说明
10,20          基板本体
11,21          线路
111            电性接点
12,22          半导体芯片
121,221        电极垫
13,23          绝缘保护层
130,230        绝缘保护层开孔
14,24          凸块底下金属层
15,251         金属柱
16,252         焊料
211            电性接点
212            线路断开部
25             导电凸块
26             底胶
AA,BB          剖面线。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“端”、“上”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A与图2B，分别为本发明的基板结构与封装结构的示意图。
如图2A所示，本发明提供一可为封装基板或电路板的基板本体20，于该基板本体20的一表面上形成有多条线路21，又，用以和外部组件电性连接的该多条线路21具有电性接点211，其中，该电性接点211具有线路断开部212，以外露该基板本体20的表面，以供对外的电性连接。
此外，另提供一半导体芯片22，其覆晶接置于该基板本体20上，该半导体芯片22的一表面具有多个电极垫221，于该半导体芯片22具有该电极垫221的表面上形成有绝缘保护层23，且该绝缘保护层23具有多个对应外露各该电极垫221的绝缘保护层开孔230，于该电极垫221上可视情况地形成有凸块底下金属层（Under Bump Metallurgy，简称UBM）24，并可于该凸块底下金属层24上形成有导电凸块25，该导电凸块25的端部对位于该线路断开部212处，并电性连接该线路21，且于该半导体芯片22与基板本体20之间形成有底胶26。
于本实施例中，该导电凸块25包括金属柱251与位于其一端上的焊料252，且该焊料252位于该线路断开部212处；或者，于其它实施例中，该导电凸块25可为焊料。
请同时参照图2B，可知该导电凸块25的端部直接嵌入在该线路断开部212所形成的下凹空间中，且连接该线路21的断面（侧表面）；其中，图2A为沿俯视图图2B的剖面线BB的剖视图，且图2B省略部分构件。
另外，该线路的线路断开部可于制作线路时利用如微影等图案化工艺所形成，且该线路断开部可如图2A所示为完全截断线路的情况，也可为不截断线路而仅形成开孔的样例，或制作成具有一缺口的情况，如U字型。
要补充说明的是，该线路断开部也可改用未断开的线路凹槽取代，且该线路凹槽的深度约为线路厚度的三分之二，然此为本发明所属技术领域中具有通常知识者依据本说明书而能了解者，故不在此加以赘述与图标。
综上所述，相比于现有技术，由于本发明的导电凸块可直接嵌入至线路断开部所形成的下凹空间中，所以能提升对位精度，又该下凹空间中可容纳导电凸块的端部，并使整体封装结构的高度降低；又下凹空间可容纳导电凸块的端部，则不易有相邻的电性接点彼此桥接的问题。基于前述优点，故可减少填充于芯片与基板本体间的底胶的用量，进而具有轻薄化与低成本的优点；此外，本发明的导电凸块进一步连接线路的断面，故可增进导电凸块与线路间的接合强度(由于线路具凹部，故导电凸块与线路间的接触表面增加)；而且，本发明的电性接点无须如现有般增大面积，且焊料被该线路断开部所限制而不易溢流，所以电性接点间的间距及线路间的间距可缩小，达成高密度线路与细线宽/细线距的目的，使封装件的效性功能增加。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (12)

1.一种基板结构，其包括：
基板本体；以及
多条线路，其形成于该基板本体的一表面上，且至少一该线路具有电性接点，用以和外部组件电性连接，其中，该电性接点具有线路凹槽。
2.根据权利要求1所述的基板结构，其特征在于，该线路凹槽为线路断开部，以外露该基板本体的表面。
3.根据权利要求1所述的基板结构，其特征在于，该基板本体为封装基板或电路板。
4.一种封装结构，其包括：
基板本体；
多条线路，其形成于该基板本体的一表面上，且至少一该线路具有电性接点，用以和外部组件电性连接，其中，该电性接点具有线路凹槽；以及
半导体芯片，其覆晶接置于该基板本体上，该半导体芯片的一表面具有多个电极垫，各该电极垫上形成有导电凸块，该导电凸块的端部位于该线路凹槽处，并电性连接该线路。
5.根据权利要求4所述的封装结构，其特征在于，该线路凹槽为线路断开部，以外露该基板本体的表面。
6.根据权利要求4所述的封装结构，其特征在于，该导电凸块的端部连接该线路的断面。
7.根据权利要求4所述的封装结构，其特征在于，该导电凸块包括金属柱与位于其一端上的焊料，且该焊料位于该线路凹槽处。
8.根据权利要求4所述的封装结构，其特征在于，该导电凸块为焊料。
9.根据权利要求4所述的封装结构，其特征在于，该封装结构还包括底胶，其形成于该半导体芯片与基板本体之间。
10.根据权利要求4所述的封装结构，其特征在于，该半导体芯片具有该电极垫的表面上还形成有绝缘保护层，且该绝缘保护层具有多个对应外露各该电极垫的绝缘保护层开孔。
11.根据权利要求4所述的封装结构，其特征在于，该电极垫与导电凸块之间还形成有凸块底下金属层。
12.根据权利要求4所述的封装结构，其特征在于，该基板本体为封装基板或电路板。
CN201210238451.XA 2012-06-19 2012-07-10 基板结构与封装结构 Pending CN103515345A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW101121874A TW201401456A (zh) 2012-06-19 2012-06-19 基板結構與封裝結構
TW101121874 2012-06-19

Publications (1)

Publication Number Publication Date
CN103515345A true CN103515345A (zh) 2014-01-15

Family

ID=49755148

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210238451.XA Pending CN103515345A (zh) 2012-06-19 2012-07-10 基板结构与封装结构

Country Status (3)

Country Link
US (1) US20130334684A1 (zh)
CN (1) CN103515345A (zh)
TW (1) TW201401456A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867901A (zh) * 2014-02-25 2015-08-26 矽品精密工业股份有限公司 基板结构与半导体封装件
CN106463427A (zh) * 2014-06-27 2017-02-22 索尼公司 半导体装置及其制造方法
CN106471612A (zh) * 2014-06-27 2017-03-01 索尼公司 半导体器件及其制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI495052B (zh) * 2012-06-25 2015-08-01 矽品精密工業股份有限公司 基板結構與使用該基板結構之半導體封裝件
US10049893B2 (en) * 2016-05-11 2018-08-14 Advanced Semiconductor Engineering, Inc. Semiconductor device with a conductive post
US10643965B2 (en) * 2016-05-25 2020-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of forming a joint assembly
CN112201640A (zh) * 2019-07-08 2021-01-08 群创光电股份有限公司 电子装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037667A (en) * 1998-08-24 2000-03-14 Micron Technology, Inc. Socket assembly for use with solder ball
TW200616114A (en) * 2004-11-03 2006-05-16 Advanced Semiconductor Eng Bumping process and structure thereof
US20100065966A1 (en) * 2006-12-14 2010-03-18 Stats Chippac, Ltd. Solder Joint Flip Chip Interconnection
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270496A (ja) * 1997-03-27 1998-10-09 Hitachi Ltd 電子装置、情報処理装置、半導体装置並びに半導体チップの実装方法
US7897502B2 (en) * 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
JP5497392B2 (ja) * 2009-09-25 2014-05-21 ルネサスエレクトロニクス株式会社 半導体装置
US20120098120A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Centripetal layout for low stress chip package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037667A (en) * 1998-08-24 2000-03-14 Micron Technology, Inc. Socket assembly for use with solder ball
TW200616114A (en) * 2004-11-03 2006-05-16 Advanced Semiconductor Eng Bumping process and structure thereof
US20100065966A1 (en) * 2006-12-14 2010-03-18 Stats Chippac, Ltd. Solder Joint Flip Chip Interconnection
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867901A (zh) * 2014-02-25 2015-08-26 矽品精密工业股份有限公司 基板结构与半导体封装件
CN106463427A (zh) * 2014-06-27 2017-02-22 索尼公司 半导体装置及其制造方法
CN106471612A (zh) * 2014-06-27 2017-03-01 索尼公司 半导体器件及其制造方法
CN106471612B (zh) * 2014-06-27 2019-07-19 索尼公司 半导体器件及其制造方法
CN106463427B (zh) * 2014-06-27 2020-03-13 索尼公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
US20130334684A1 (en) 2013-12-19
TW201401456A (zh) 2014-01-01

Similar Documents

Publication Publication Date Title
CN103515345A (zh) 基板结构与封装结构
US10879219B2 (en) Lower IC package structure for coupling with an upper IC package to form a package-on-package (PoP) assembly and PoP assembly including such a lower IC package structure
US11791256B2 (en) Package substrate and method of fabricating the same
TWI581397B (zh) 晶片封裝、電腦系統、和電子裝置
CN103579197A (zh) 具有防电磁波干扰的半导体组件
CN104282648B (zh) 半导体装置及其制法
CN104576593A (zh) 封装结构及其制法
CN204335177U (zh) 电子元器件内置模块
US10121043B2 (en) Printed circuit board assembly with image sensor mounted thereon
CN104425417B (zh) 半导体装置及其制法
CN105097759A (zh) 封装堆栈结构及其制法暨无核心层式封装基板及其制法
KR102592972B1 (ko) 센싱 모듈 기판 및 이를 포함하는 센싱 모듈
US20150255423A1 (en) Copper clad laminate having barrier structure and method of manufacturing the same
CN104517922A (zh) 层叠式封装结构及其制法
CN102543894A (zh) 电性连接垫结构及包含有多个电性连接垫结构的集成电路
US9265147B2 (en) Multi-layer wiring board
CN103956366B (zh) 晶圆级芯片封装结构
US20140113464A1 (en) Flexible package-to-socket interposer
CN103985675A (zh) 半导体装置
CN104134641A (zh) 半导体封装件及其制法
CN103137581A (zh) 具有导电凸块的半导体装置、封装结构及制法
CN103199076A (zh) 封装结构及其制法
KR20130101192A (ko) 다수의 단차가 있는 인쇄회로 기판 (ｐｃｂ)을 갖는 반도체 패키지 및 반도체 패키지 제조 방법
CN205542765U (zh) 半导体封装结构
CN105789170A (zh) 封装堆栈结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20140115