CN103515329B - 基板结构与使用该基板结构的半导体封装件 - Google Patents

基板结构与使用该基板结构的半导体封装件 Download PDF

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CN103515329B
CN103515329B CN201210238506.7A CN201210238506A CN103515329B CN 103515329 B CN103515329 B CN 103515329B CN 201210238506 A CN201210238506 A CN 201210238506A CN 103515329 B CN103515329 B CN 103515329B
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circuit
electrical contact
semiconductor package
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package part
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CN103515329A (zh
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林长甫
蔡和易
姚进财
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Siliconware Precision Industries Co Ltd
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Abstract

一种基板结构与使用该基板结构的半导体封装件，该基板结构包括基板本体以及形成于该基板本体上的多条线路，且至少一该线路具有电性接点，用以和外部组件电性连接，其中，该线路于电性接点处缩减其宽度。本发明能有效达到细线宽/细线距与微型化的目的，并可增进产品可靠度，且降低制造成本。

Description

基板结构与使用该基板结构的半导体封装件
技术领域
本发明涉及一种基板结构与半导体封装件，尤指一种用于覆晶封装的基板结构与半导体封装件。
背景技术
由于电子产品的设计愈来愈朝向轻薄短小、多功能及高频工作效能的趋势前进，因此电路板或封装基板也必须往细线宽/细线距（fine line/fine pitch）的方向发展，且因为覆晶式半导体封装件的接脚数远大于打线式半导体封装件的接脚数，所以逐渐以覆晶式半导体封装件取代打线式半导体封装件。
图1所示者，为现有覆晶式封装基板的俯视图，该封装基板1的用以接置半导体芯片的电性接点111须设置于线路11的一端，且该电性接点111的尺寸大于线路11的尺寸，因此线路11的布线密度往往会受限于电性接点111的大小，而无法制作细线宽/细线距的产品，故于固定的封装基板面积的情况下，其布线密度无法提升，而导致半导体封装件的效能受限。
为解决前述问题，业界遂开发出一种应用于覆晶式封装基板的BOT（Ball onTrace）技术，如图2所示，也就是封装基板2的线路于接置半导体芯片处无须设置电性接点，故线路21的布线密度不受电性接点大小的限制，但是为了避免焊球22与线路21间的接触面积过小，业界运用BOT技术时，往往会于线路21欲接至焊球22处稍微设计宽一些，以增加覆晶的接着强度，使产品可靠度增加，但是这样部分较宽的线路21还是会使封装基板2的布线密度受到一定的限制。
此外，由于封装件产品的布线密度提升，且半导体芯片的电极垫数目增加，故用以接置于线路21上的焊球22其体积亦相对缩小，而导致焊球22与线路21间的接着强度下降，进而产生可靠度问题。
因此，如何避免上述现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
有鉴于上述现有技术的不足，本发明的主要目的在于提供一种基板结构与使用该基板结构的半导体封装件，能有效达到细线宽/细线距与微型化的目的，并可增进产品可靠度，且降低制造成本。
本发明的基板结构包括：基板本体；以及多条线路，其形成于该基板本体上，且至少一该线路具有电性接点，用以和外部组件电性连接，其中，该电性接点具有缩减的宽度。
本发明还提供一种使用该基板结构的半导体封装件，其包括：该基板结构；以及半导体芯片，其覆晶接置于该基板本体上，该半导体芯片具有多个电极垫，且该电极垫与基板本体间具有导电凸块，并使该导电凸块结合至该电性接点上，以令该半导体芯片借该导电凸块电性连接该多条线路。
由上可知，由于本发明在保持大部分的线路区域宽度不变的情况下，仅使少数线路区域变细而作为电性接点；相比于现有将电性接点处的宽度保持不变，而去缩小大部分线路区域宽度的基板(同一基板面积下，线与线的排列密度是由每条线路最宽处决定)，本发明的线路的制造难度大为下降，使得封装基板的制造良率上升，进而减低制造成本。此外，本发明也能提供较强的半导体芯片接合强度，而可提升半导体封装件的可靠度。而且，本发明可加大相邻线路间的电性接点间的间距，以达成高密度线路与细线宽/细线距的目的。
附图说明
图1为一种现有覆晶式封装基板的俯视图。
图2为另一种现有覆晶式封装基板的立体图。
图3A、图3B与图3C分别为本发明的基板结构与半导体封装件的立体图、俯视图与剖视图；其中，图3C为沿俯视图图3B的剖面线AA的剖视图。
主要组件符号说明
1,2 封装基板
11,21,31 线路
111,311 电性接点
22 焊球
30 基板本体
310 线路断面
311a 顶面
311b 侧表面
32 半导体芯片
321 电极垫
33 绝缘保护层
330 绝缘保护层开孔
34 凸块底下金属层
35 导电凸块
351 金属柱
352 焊料
36 底胶。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“端”、“侧”、“上”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图3A、图3B与图3C所示者，分别为本发明的基板结构与半导体封装件的立体图、俯视图与剖视图；其中，图3C为沿俯视图图3B的剖面线AA的剖视图，图3A与图3B省略部分构件，且图3A为回焊前的状态，图3B与图3C为回焊后的状态。
如图3A至图3C所示，本发明提供一可为封装基板或电路板的基板本体30，于该基板本体30上形成有多条线路31，此外，用以和外部组件电性连接的该多条线路31具有电性接点311，其中，该线路31于电性接点311处缩减其宽度。
于本实施例中，是将电性接点的宽度缩减至如同图2的较细线路的宽度，并将线路加宽至如同图2的较宽线路的宽度，且使得该线路31较佳是于电性接点311处缩减其宽度至原来的百分的七十至九十。
此外本实施例是令该线路31从其宽度方向的相对两侧表面内缩，而具有缩减的宽度，但不以此为限。
此外，另提供一半导体芯片32，其覆晶接置于该基板本体30上，该半导体芯片32的一表面具有多个电极垫321，于该半导体芯片32具有该电极垫321的表面上形成有绝缘保护层33，且该绝缘保护层33具有多个对应外露各该电极垫321的绝缘保护层开孔330，于该电极垫321上可视情况地形成有凸块底下金属层（Under Bump Metallurgy，简称UBM）34，并可于该凸块底下金属层34上形成有导电凸块35，该导电凸块35的端部位于该电性接点311上，并电性连接该线路31，且于该半导体芯片32与基板本体30之间形成有底胶36。
于本实施例中，该导电凸块35包括金属柱351与位于其一端上的焊料352，且该焊料352位于该电性接点311上；或者，于其它实施例中，该导电凸块35可为焊料。
再参照图3B，可知该导电凸块35的端部除了连接该电性接点311的顶面311a外，该导电凸块35的端部也连接该电性接点311的侧表面311b与相接该侧表面311b的线路断面310，即该导电凸块35与电性接点311的接触面共有一顶面311a、二侧表面311b与二线路断面310，电性接点提供与导电凸块35结合的接触面积显较现有技术为多，故可增进导电凸块35与电性接点311间的接合强度。
此外，由图3B可知，因为该线路31于电性接点311处缩减其宽度，而使得相邻电性接点311的距离增加，且缩减宽度后所形成的空间可容纳部分该焊料352，而不易有相邻的电性接点彼此桥接的问题，所以电性接点间的间距可缩小，达成高密度线路与细线宽/细线距的目的。
综上所述，相比于现有技术，由于本发明是在大部分的线路区域宽度不变的情况下，仅使少数线路区域变细而作为电性接点；相比于现有将电性接点处的宽度保持不变，而去缩小大部分线路区域宽度的基板(同一基板面积下，线与线的排列密度是由每条线路最宽处决定)，本发明的线路的制造难度大为下降，使得封装基板的制造良率上升，进而减低制造成本。此外，本发明也能提供较强的半导体芯片接合强度，而可提升半导体封装件的可靠度。而且，本发明可加大相邻线路间的电性接点间的间距，以达成高密度线路与细线宽/细线距的目的。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种基板结构，其包括：
基板本体；以及
多条线路，其形成于该基板本体上，且至少一该线路具有多个电性接点，以用以和外部组件电性连接，其中，该线路从其宽度方向的相对两侧表面内缩，使该电性接点相对该线路的其它部分均具有缩减的宽度，以令半导体芯片借多个导电凸块电性连接该多条线路，其中，该导电凸块结合至该电性接点上，且各该导电凸块与各该电性接点的接触面共有一顶面、二侧表面与二线路断面。
2.根据权利要求1所述的基板结构，其特征在于，该电性接点的宽度为该线路宽度的百分的七十至九十。
3.一种半导体封装件，其包括：
基板结构，包括有：
基板本体；以及
多条线路，其形成于该基板本体上，且至少一该线路多个具有电性接点，用以和外部组件电性连接，其中，该线路从其宽度方向的相对两侧表面内缩，使该电性接点相对该线路的其它部分均具有缩减的宽度；以及
半导体芯片，其覆晶接置于该基板本体上，该半导体芯片具有多个电极垫，且该电极垫与基板本体间具有导电凸块，并使该导电凸块结合至该电性接点上，且各该导电凸块与各该电性接点的接触面共有一顶面、二侧表面与二线路断面，以令该半导体芯片借该导电凸块电性连接该多条线路。
4.根据权利要求3所述的半导体封装件，其特征在于，该电性接点的宽度为该线路宽度的百分的七十至九十。
5.根据权利要求3所述的半导体封装件，其特征在于，该导电凸块包括金属柱与位于其一端上的焊料，以供该焊料结合于该电性接点上。
6.根据权利要求3所述的半导体封装件，其特征在于，该导电凸块为焊料。
7.根据权利要求3所述的半导体封装件，其特征在于，该半导体封装件还包括底胶，其形成于该半导体芯片与基板本体之间。
8.根据权利要求3所述的半导体封装件，其特征在于，该半导体芯片具有该电极垫的表面上还形成有绝缘保护层，且该绝缘保护层具有多个对应外露各该电极垫的绝缘保护层开孔。
9.根据权利要求3所述的半导体封装件，其特征在于，该电极垫与导电凸块之间还形成有凸块底下金属层。
10.根据权利要求3所述的半导体封装件，其特征在于，该基板本体为封装基板或电路板。
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