1254424 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種具可調式電 指一種利用銲線而形成可調式 & 、 _封裝件，尤 【先前技術】 成了料^之半導體封裝件。 隨著半導體製程技術不曰 能要求亦隨之提昇，伴隨而至之^ :片的處理速度與功 體封裝件之電性，並維擊半 、在於如何提升半導 _ *笊干％體封裝件之信賴性；一 吕，設計者往往係將被動 、 、又 ^ 干正σ至封裝件的電路上，以 猎5玄被動70件之效用而提升產品之電性愈良率。 二板作為晶片承載件之半導體封裝件而 二二板之表面上接置所需例如電感等被動元 牛=错该些破動元件與基板上導電跡線之佈局 至所需的電性效果。 違 對於以導線架為晶片承載件之封裝件而言，例 晶片座Nrleaded)式封装件’其導線架係包括一 線電性連接：於邊晶片座周圍之多數導腳，再藉由多數銲 實已無多餘之空間容置被導腳，該導線架上 整合至銲線之難以將習知被動元件 =之線路布局中’形成電性設計上的—大障礙， ’、=由外加電感，達至調整電感值與阻抗匹配之效果。 ‘、'、解決此-問題，遂有於導線架上設計電感之技術產 要以滿足封裝件上特別係射頻電路對於匹配、遽波、及 偏置網路之電性雪卡·甘、， 而衣，其係如吴國專利第6,621,140號案 17765(修正本） 5 1254424 所揭示，如第1圖之上視圖所示，該半導體 -導線架2。，該導線架2。係包括至少一晶二= 該晶片座22之多數導腳24，該導線架20上復具有多數電 感段 261，262,263( inductive segment)，且該些電感段 ％卜 262、263係分別用以形成導線架上之電感部分，該些電感 段261、262、263係相互平行且位於晶片座。之同侧；同 時，晶片28係接置於該晶片座22上，且多數銲線係用以 電性連接該晶片28與其對應導腳24,並連接該些電感段 261、262、263以形成一電感。 第2圖係第！圖所示之封裝件於模壓後的剖視圖，如 圖所示，其係以封裝膠體27包覆該晶片座22、多數導腳 24、電感段261、262、263及多數銲線，且該晶片座22、 導腳24之底面係外露出該封裝膠體27,且該晶片座η與 ，些導腳24係具有相同的厚度，而該些電感段261、如、 之厚度則略小於該些導聊及晶片座之厚度，而使該些 电感段261、262、263不露出該封裝膠體27。 :此，此設計即如第】圖之線路布局，先以一般之訊 $線25電性連接晶片28上之銲墊23與導腳24，再以 =銲線電性連接該電感段261與該晶片心的一鮮 與二’再稭由三條電感銲線21電性連接電感段262 與：二段263’亚以另三條電感銲線21電性連接電感段w ^感段加。故而’若電感段加如圖示連接至一供應 残妒”电•路位即為.自外界電源沿該電感段262經電 W線^流至該電感段263,再沿該電感段263經另一 17765(修正本) 1254424 f感銲線2〗流至該電感段261，進而再經 、惟，對於此類設計而言，其最大缺點在 對-般封裝產品而言，常因物料:ί 私決差與不同的射頻（RF)電路應用，而必須在 並執行功能驗證時，調整電感值與阻抗匹配，以達到= 的取佳電性。但對於以前述方式形成之電感而言 = 賴«形狀即已固定’若需再進行調整二改變 :感值，在往需另外製作導線架，實不 亦無法提供即時修改之彈性。 、、〜而求， 成所卜.it:述導線架之製程中，需要在相對導腳間形 :曰斤而=段，該些電感段之厚度、形狀均與該些導腳 及日日片座不同，亦將大幅增 提高其製作成本。 了UA之稷雜度’並《 其他例如美國專利第6 5Ή % & ^ 腳形成所H ,遽案，雖然不是以導 被動元件古 以改變晶片座形狀之方式形成 Γ羽Λ 即時調整與製程複雜等諸多缺點。 提供自°半㈣封裝件顯然仍存有極大之問題，·如何 可調式電感之半導體封裝件，同時又能㈣ 【發明内容】、75成—亟待解決之重要課題。 17765(修正本） 7 1254424 供一 件0 本發明之另一目的在於裎 設計的具可調式電感之铸==無需改變習知導線架 易的目：在於提供-種低製作成本且製程簡 /、了凋式电感之半導體封裝件。 丰導2上揭及其他目#，本發明所提出具可調式電成之 +導體封裝件，係包括：= 腳之導線架，其中，該此導 方’丄及夕數导 導腳.一曰H r 二¥腳至^包括有訊號導腳及電感 r線：二丨 置於該導線架之晶片座上；多數訊號 1 ”77牙用以電性連接該晶片與該訊號導腳；以及多 數電感銲線，細串聯方式而分職性連接不同之電感導 腳’俾使该些電感導腳與電感鐸線形成—可調式電感。 該具可調式電感之半導體封裝件復包括一用以包覆該 導線架、該晶片及該些銲線之封裝膠體，且該些導腳復包 括有一用以接地的接地導腳。 同時，該多數電感銲線係以串聯方式連接成一婉蜒 (serpentine)或—螺旋（Spiral)形狀，而該些電感導腳 之其中-者係被定義為該電感的—個端點，以藉該訊號鮮 線而電性連接至該晶片。 因此，本發明用以調整該電感之電感值的方法係為， 選擇該電感導腳中未電性連接至該晶片的任一導腳為該電 感的傳輸導腳’以將該傳輸導腳連接至外界的供給電壓， 17765(修正本) 8 1254424 j =二可凋式電感之電感值；或者，本發明亦可選擇 該可啁：：：其：一者接地來降低電感值，亦同樣可改變 发J凋式電感之電感值。 與 =即知，藉由本發明所提出之藉由電感導腳 泉所組合成之可調式電感，既可解決習知上難以 :日=整電感值之缺點，復可兼顧製程上之簡易性，充分 達至習知技術所無之功效。 【實施方式】 古、> 以下，藉由特定的具體實例說明本發明之實施方式， 、、怂此技π之人士可由本說明書所揭示之内容輕易地暸解 本發明之其他優點與功效。本發明亦可藉由其他不同的且 體實例加以施行或應用，本說明書中的各項細節亦可基於 不同觀點與應用’在不悖離本發明之精神下進行各種修飾 、第3圖係為本發明第一實施例之導線架3〇上視圖，該 ^線架30係具有_晶片座32及圍繞於該晶片座32周圍之 夕數&腳34 ’该晶片座32並非如習知導線架之晶片座恰 位於導線架之中央，而係偏置於該導線架30之一側；其 中，該些導腳34係至少包括多數訊號導腳34a、電感導腳 34b、與接地導腳34c，且該些電感導腳34b與接地導腳3乜 係均位於該晶片座32的同一侧；此外，該電感導腳Mb 與該接地導腳34c係均為該導線架3〇製作過程中預留的 NC (Not C〇nnected)導腳；而該導線架3〇上亦可形成多 數晶片座，惟為簡單起見，本實施例中僅圖示一晶片座， 9 17765(修正本) 1254424 但並非以此為限。 該導線架30係以習知的钱刻（此㈣ (Stamping)技術形成所需的晶片座以及腳 於本實施例中，該導線架3〇得 冷P34形狀， 製成，惟該導線架30亦可由= 列如銅等導電性佳之材賀 _係為本實施例之封二：::前:’=。1254424 IX. Description of the invention: [Technical field of the invention] The present invention relates to a semiconductor package with adjustable electric fingers, which can be formed by using a bonding wire to form a tunable & _ package, especially [previously] Pieces. As the semiconductor process technology can not only meet the requirements, but also the accompanying ^: film processing speed and the electrical properties of the power package, and the half-strength, how to improve the semi-conductor _ * dry % package The reliability of the piece; a Lu, the designer often will be passive, and then dry σ to the circuit of the package, to improve the electrical yield of the product. The second board serves as a semiconductor package for the wafer carrier and the passive elements such as inductors are connected to the surface of the second board. The layout of the conductive elements on the substrate and the conductive traces on the substrate is required to achieve the desired electrical effect. For a package with a lead frame as a wafer carrier, a ferrule-type package of the wafer holder includes a wire electrical connection: a plurality of leads around the wafer holder, and then a plurality of soldering There is no extra space to accommodate the guided pin, and it is difficult to integrate the soldering wire on the lead frame. In the circuit layout of the conventional passive component = the formation of the electrical design - the big obstacle, ', = by the external inductance, up to To adjust the effect of the inductance value and impedance matching. ',', solve this problem, the technical design of the inductor on the lead frame to meet the special RF circuit on the package for the matching, chopping, and bias network of the electric snow card Gan, And the clothing, which is disclosed in the above view of the first embodiment of the present invention, as shown in the above view of FIG. 1 , the semiconductor-lead frame 2 is disclosed in Japanese Patent No. 6,621,140, No. 6,765 (Revised). , the lead frame 2. The system includes at least one crystal 2 = a plurality of lead legs 24 of the wafer holder 22, the lead frame 20 has a plurality of inductive segments 261, 262, 263 (inductive segments), and the inductor segments 262, 263 are respectively formed Inductive portions on the lead frame, the inductive segments 261, 262, 263 are parallel to one another and are located in the wafer holder. At the same time, the wafer 28 is connected to the wafer holder 22, and a plurality of bonding wires are used for electrically connecting the wafer 28 and its corresponding guiding pin 24, and connecting the inductive segments 261, 262, and 263 to form An inductor. Figure 2 is the first! A cross-sectional view of the package shown in the drawing, as shown, encloses the wafer holder 22, a plurality of leads 24, inductor segments 261, 262, 263 and a plurality of bonding wires with a package adhesive 27, and the wafer The bottom surface of the housing 22 and the guiding pin 24 exposes the encapsulant 27, and the wafer holder η and the guiding pins 24 have the same thickness, and the thickness of the inductive segments 261, eg, is slightly smaller than the guiding portions. The thickness of the wafer holder is discussed such that the inductor segments 261, 262, 263 do not expose the encapsulant 27. This is the layout of the circuit as shown in the figure. First, the pad 23 and the pin 24 on the wafer 28 are electrically connected by a general line $25, and then the inductor segment 261 is electrically connected by a = wire. The fresh and the two's of the wafer core are electrically connected to the inductor segment 262 by three inductor wires 21: the second segment 263' is electrically connected to the inductor segment by the other three inductor wires 21. Therefore, if the inductor segment is connected to a supply residue as shown in the figure, the power path is from the external power source along the inductor segment 262 via the electric W line to the inductor segment 263, and then along the inductor segment 263. Another 17765 (amendment) 1254424 f solder wire 2 flows to the inductor segment 261, and then, however, for this type of design, its biggest drawback is in the case of general packaging products, often due to materials: ί Private decision and different radio frequency (RF) circuit applications, and must adjust the inductance value and impedance matching when performing function verification to achieve better electrical conductivity = but for the inductor formed in the foregoing way = Lai «shape is fixed' If you need to make adjustments again, change: Sensing value, in addition to the need to make another lead frame, it can not provide the flexibility of instant modification.,, ~, seeking, into the book. It: said wire In the manufacturing process of the rack, it is necessary to form a shape between the opposite guide legs: the thickness and shape of the inductor segments are different from those of the guide pins and the daily seat, and the production cost thereof will be greatly increased. UA's annoyance' and other such as US patents 65th % & ^ foot formation H, the case, although not the passive component to change the shape of the wafer holder to form the shape of the wafer, the immediate adjustment and the complexity of the process and many other shortcomings. Providing the self-° half (four) package obviously still has a great problem, how can The semiconductor package of the modulated inductor can also (4) [invention content], 75 percent - an important issue to be solved. 17765 (amendment) 7 1254424 for one 0 Another object of the present invention is to design a modified inductor Casting == No need to change the purpose of the conventional lead frame: it is to provide a semiconductor package with low manufacturing cost and simple process, and with the inductance of the inductor. The adjustable electroconductor + conductor package includes: = lead frame of the foot, wherein the guide '丄 and the oxime guide pin. 曰H r 2 ¥ to ^ include signal pin and inductance r line: two turns are placed on the wafer holder of the lead frame; most signals 1" 77 teeth are used to electrically connect the chip and the signal lead; and most of the insulated wire, the thin series and the different positions are different. Inductive lead These inductor leads are formed with the inductor turns - a tunable inductor. The semiconductor package with the adjustable inductor includes a package body for covering the lead frame, the wafer and the bonding wires, and the guiding pins further comprise a grounding pin for grounding. At the same time, the majority of the inductive bonding wires are connected in series to form a serpentine or a spiral (Spiral) shape, and the ones of the inductance guiding legs are defined as the end points of the inductance to borrow The signal is freshly wired and electrically connected to the wafer. Therefore, the method for adjusting the inductance value of the inductor is to select any of the lead pins of the inductor lead that are not electrically connected to the chip as the transmission lead of the inductor to connect the transmission lead. Supply voltage to the outside world, 17765 (Revised) 8 1254424 j = Inductance value of the two-inductive inductor; or, the present invention may also select the 啁::: It: one grounding to reduce the inductance value, also Change the inductance value of the inductor. It is known that the adjustable inductor combined by the inductor guide spring can solve the conventional problem that it is difficult to: the value of the day = the whole inductance value, and the simplicity of the process can be solved. Fully reach the effects of conventional technology. [Embodiment] The following describes the embodiments of the present invention by way of specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present specification. The present invention may be embodied or applied by other different embodiments. The details of the present specification may also be modified based on different viewpoints and applications without departing from the spirit of the invention. The lead frame 3 of the first embodiment of the present invention has a top view, the wire holder 30 has a wafer holder 32 and a circumference & foot 34 surrounding the wafer holder 32. The wafer holder 32 is not a conventional wire. The wafer holder is located at the center of the lead frame and is offset from one side of the lead frame 30. The lead pins 34 include at least a majority of the signal lead 34a, the inductor lead 34b, and the ground lead 34c. The inductive lead 34b and the grounding lead 3 are both located on the same side of the wafer holder 32. In addition, the inductive lead Mb and the grounding lead 34c are both pre-prepared during the manufacturing process of the lead frame 3 The remaining NC (Not C〇nnected) leads; and the lead frame 3 can also form a plurality of wafer holders, but for the sake of simplicity, only one wafer holder is shown in this embodiment, 9 17765 (Revised) 1254424 But it is not limited to this. The lead frame 30 is formed into a desired wafer holder and a foot in the present embodiment by a conventional stamping technique. The lead frame 3 is formed in a cold P34 shape, but the lead frame 30 is formed. It can also be made by == such as copper, etc., which is a good conductivity. It is the cover of this example::: before: '=.
圖，錢於第3圖所示之導線架30上接置一晶片/並 利用銲線進行電性連接且形志 W 曰月36隸罢需之電感，如圖所示，該 日日片36係接置於该導線架3〇之晶片座”上 金線之訊號銲線31a係分別電性連接該晶片36 =周^ 對應甙娩導腳34a’圖示中僅以部份訊號 °一二、 明，惟訊號銲線3la之數量並 〜、干、，、&例不祝 線亦用以電性連接該 34c，以發揮接地之魏。 <接地銲墊與該接地導腳 實施狀特徵即在於，提供多數例如金線之 二b :以串聯方式分別電性連接不同的電感導 列成2 些以串聯方式連接的電感銲線训將排 —Μ形狀，並與其料接的電感導腳 J4b ^成所需的可調式電感。 該電感導腳34b其中之—係被定義為Fig., money is connected to a lead frame 30 shown in Fig. 3, and a wire is connected and electrically connected by a bonding wire, and the inductance of the shape is required. As shown in the figure, the day piece 36 The signal bonding wire 31a connected to the gold wire on the wafer holder of the lead frame 3 is electrically connected to the wafer 36 = weekly ^ corresponding to the guiding pin 34a', only a part of the signal is used. Ming, but the number of signal bonding wires 3la and ~, dry,,, & not wish to use the wire is also used to electrically connect the 34c to play the grounding of the ground. <Ground pad and the grounding pin implementation The feature is that a plurality of gold wires are provided, for example, two wires are connected in series, and different inductances are electrically connected in series to form two series of inductor wire bonds connected in series, and the inductance is guided by the material. Pin J4b ^ becomes the desired adjustable inductor. The inductor lead 34b is defined as
(圖不中之導腳A、，豆仫兹山 U a 9 一讯號銲線31a而電性連接 至该日日片36上之一銲墊35; 腳34b為該電减 "再疋我另1感導 盥外界導腳F)’以為該電感 ㈣號傳輸的傳輸導腳’該傳輸導腳係可與外界 10 17765(修正本） 1254424 之供給電壓連接。 第4 Γ中^為便於說㈣可調式電感之電感值調整方法’ s中係以付號標不6個電感導腳分別為a、b、c、d、(The guide pin A in the figure, the 仫 仫 山 U U 9 a signal wire 31a is electrically connected to one of the pads 35 on the day piece 36; the foot 34b is the electric reduction " I have another sense of the external lead F) 'Thinking that the transmission lead of the inductor (four) transmission' can be connected to the supply voltage of the external 10 17765 (Revised) 1254424. In the fourth section, it is convenient to say that (4) the adjustment method of the inductance value of the adjustable inductor is in the middle of the number, and the six inductor leads are a, b, c, d, respectively.
連接，而：此為限。此時，該導腳A係與該晶片36電性 連接而轉腳F係與外界之供給電壓Vee連接，以作A 该電感導腳34b所形成之雷代沾德^乍為 珉之電感的傳輸導腳，並令該導腳 人二上別為該電感之兩端點。因此’該供給電壓Μ將 流過該電感後再進入該晶片36，如圖所示，該 ;:Ε Γ為.自該傳輸導腳？經該電感銲線训而至該 ::二再由導腳E經電感銲線31“至導腳 娜训至導腳C，復由導腳C經電感鲜線二 由’接者由導經電感銲線训至導腳A，最後， 再由¥腳八經訊號銲線3la流至該晶片36。 者即由前述電感銲線训之電性連接關係，使用 視而要祕不同之導腳（例如導腳B、c 該電感與外界連接之傳輸導 ' )作為 、以调整至所需的電感值； 亦可視需要選擇該接地導腳34c其中之一接 :!侗t而猎其接地提供一參考平面（Ref⑽cepiane)，以 形成的電感值，亦為調整電感值的另—方法；進而 之方式，利用该導線架3〇上所預留的NC導腳及 :、干、、泉，而於導線架3 〇上形成f知技術所無的可 感，適應半導體封裝件於高頻範圍内不同電路之需求。 月，J述實施例於封裝完成後之剖視圖即如第5圖所示， 11 17765(修正本） 1254424 其係以一封裝膠體37包覆該晶片36、該些導腳34、 片座32及多數銲線（包括訊號銲線3丨a及電感銲線3 1 b )， 且該晶片座32及該些導腳34之部份底面係外露出該封妒 膠體37，以與外部例如印刷電路板等電子裝置電性連接。 本發明之設計除前述實施例般將多數電感銲線以串聯 方式連接成婉蜒（Serpentine )形狀外，亦可有其他串聯連 接方式，如第6圖所示的第二實施例，其係為該實施例之 封裝件於模壓製程前的上視圖，其結構與製造方式大致與 前述之第一實施例相似，惟在此第二實施例中，多數電感 崔干線係以串聯方式連接成一螺旋（Spiral )形狀，並分別^ 性連接不同之導腳以形成電感；如圖所示，該導線架3〇, 係具有一晶片座32,及圍繞該晶片座32,之多數導腳34,， 且該導腳34’係至少包括多數訊號導腳34a，及電感導腳 34b’ ；其中，該些電感導腳34b，係為該導線架3〇,製作過 程中所預留的Nc (Not Connected)導腳，且一晶片36,係接 置於=導線架30,之晶片座32，上，並藉該多數訊號銲線 31a電性連接該晶片36,與該訊號導腳34a，；此外，多數電 感銲線31b，係以串聯方式連接成一螺旋（响^如⑷= 狀’以分別電性連接不同之電感導腳34b，，以藉該些電感 杯線31b與電感導腳34b，形成所需的可調式電感。 為説明本實施例之可調式電感的電感值調整方法，第 6曾圖中係以符號標示9個電感導腳34b，，分別為導腳A至 ‘腳I，但其數量與位置均非以此為限。該導腳A係定義 為忒電感之一端點，並藉一訊號銲線31a，電性連接至該晶 17765(修正本） 12 1254424 而料腳1較義為該電感之另一 兮導腳A…4與外界進行訊號傳輸之傳輸導腳，並令 為該電感之兩端點。因此，該辑 示，於流過該電感後再進人該晶片％，，如圖所 之連Γ :自料腳1而藉由該些電感銲線31b, 分別經過導腳^〇、卜£、〇、^、八，再藉 該導腳h、g、f、e =3:’，亦可視需要選擇 ^ 之其中任一者作為該電感 4: 連接至外界供給㈣，藉此調整出所需的 ^ aa 、之罘一貫轭例，利用該導線架 ^所預㈣NC導腳及各種銲線，而於導線架％，上形 =技#所無的可調式電感，適應半導體封裝件於 乾圍内不同電路之需求。 貝 此=實施例亦可進行模壓作業，而形成一包覆該晶 丄"¥腳、以片及多數銲線（包括訊號料&，及電 感銲線3lb’)的封裝膠體，其剖視 例剖視圖相同。 弟^ ^ 因此’藉由本發明所提出之半導體封料，即可利 二數銲線及導線架上預留的狀導腳形成所需之電感，而 热需在導線架之任兩導腳間形成與晶片座及導腳厚度不同 ，電感段，充分解決了習知製程成本過高與製程繁複之問 題。 此外，相較於習知技術，本發明所提出之半導體封裴 件’僅需改變該電感銲線之接設，即可變更該電感:的^ 17765(修正本〕 13 1254424 輸導腳位置，快读 將接地導腳1中之—者^/變電感值；同時復可視需要 值變更之…·;彈Γ 低電感值，既可兼顧電感 本。 ' 使可大幅縮短調整電感值之時間與成 开^戶’ ί發明所提出之半導體封裝件’由於係以銲線 整㈣"曰線改變銲線的線徑與數目，以調 件之電性。 ㈣卜低‘線祕而提升半導體封裝 上述實施例僅例示性說 非用於限制本發明。任行m 原理及其功效，而 背本發明之精神及範:;τ項技藝之人士均可在不違 變。因此，本Μ之^ 貫施例進行修飾與改 範圍所列。 _保護範圍，應如後述之申請專利 【圖式簡單説明】 第1圖係為習知具電感之導線 第2圖係第！圖之丰……衣仵上視圖’ <牛V體封1件於模壓後丨 =係本發明第—實施例之導線架上7 後之L見=3圖…糊於接叫與形成電感 弟5圖係弟3圖所示之導岭架 圖；以及 斤下之¥線木於完成封裳後之剖視 第6圖係本發明第二實施例之導線 成電感後之上視圖。 接置日日片與形 【主要元件符號說明】 17765(修正本) 14 1254424 10， 20，30 ，3(T 導線架 11， 21 銲線 31a ，31a， 訊號銲 線 31b ，31b， 電感銲 線 16， 28，36 ，36, 晶片 18， 23，35 ，35, 銲墊 261 ，262， 263 電感段 31a ^ 31a5 訊號銲 線 31b ，31b， 電感鲜 線 12， 22，32 晶片座 14， 24，34 導腳 34, 導腳 34a ，34a， 訊號導 腳 34b ，34b’ 電感導 腳 34c ，34c” 接地導 腳 27， 37 封裝膠 體 15 17765(修正本)Connected, and: this is limited. At this time, the lead A is electrically connected to the wafer 36, and the turn F is connected to the external supply voltage Vee, so that the inductance of the inductor lead 34b is 电感 沾 德 电感 电感The lead pin is transmitted, and the pin is placed on both ends of the inductor. Therefore, the supply voltage 流 will flow through the inductor and then enter the wafer 36. As shown, this is: Ε Γ is the transmission lead? Through the induction welding line training to:: two by the lead E through the induction welding line 31 "to the guide foot Na training to the guide pin C, the re-guided foot C through the inductor fresh line two by the 'receiver led by The inductive welding line is trained to the lead pin A, and finally, the foot line 8 is sent to the chip 36 via the signal bonding wire 3la. The electric connecting relationship of the inductive welding line is used, and the guiding pin is different depending on the use. (For example, the lead B, c, the transmission connection of the inductor to the outside world) is adjusted to the required inductance value; one of the grounding pins 34c can also be selected as needed: !侗t and the grounding is provided a reference plane (Ref(10)cepiane) to form an inductance value is also another method of adjusting the inductance value; and further, the NC guide pins reserved on the lead frame 3 and: dry, spring, and Forming a sensation that is not available in the lead frame 3 ,, and adapting to the requirements of different circuits in the high frequency range of the semiconductor package. The cross-sectional view of the embodiment of the present invention after the package is completed is as shown in FIG. 5 . 11 17765 (Revised) 1254424, which is covered with a package of adhesive 37, the leads 34, the holder And a plurality of bonding wires (including the signal bonding wire 3丨a and the inductor bonding wire 3 1 b ), and the bottom surface of the wafer holder 32 and the guiding legs 34 are exposed to the sealing body 37 to be externally The electronic device such as the printed circuit board is electrically connected. The design of the present invention, except for the foregoing embodiments, connects a plurality of inductor wires in a series connection to a Serpentine shape, and may also have other series connection methods, as shown in FIG. The second embodiment shown is a top view of the package of the embodiment before the molding process, and the structure and manufacturing method are substantially similar to the first embodiment described above, but in the second embodiment, most of the inductors The Cuigan line is connected in series to form a spiral shape, and the different lead pins are respectively connected to form an inductor; as shown, the lead frame 3 has a wafer holder 32 and surrounds the wafer holder. 32, the majority of the lead 34, and the lead 34' includes at least a majority of the signal lead 34a, and the inductor lead 34b'; wherein the lead 34b is the lead frame 3, the manufacturing process Nc (Not Connected) guide pin reserved in the middle, A chip 36 is connected to the die holder 30, the wafer holder 32, and electrically connected to the wafer 36 by the majority of the signal bonding wires 31a, and the signal guiding pin 34a. In addition, most of the inductor bonding wires 31b Connected in series to form a spiral (resonance such as (4) = shape to electrically connect different inductance leads 34b, respectively, to form the desired adjustable inductance by the inductor cup line 31b and the inductor lead 34b. In order to explain the method for adjusting the inductance value of the tunable inductor of the present embodiment, the sixth inductor lead 34b is denoted by a symbol in the sixth figure, which is the lead pin A to the foot I, respectively, but the number and position thereof are not This is limited to this. The lead A is defined as one end of the 忒 inductor, and is electrically connected to the crystal 17765 (Revised) 12 1254424 by a signal bonding wire 31a, and the foot 1 is equivalent to the other guiding pin A of the inductor. ...4 The transmission pin of the signal transmission with the outside world, and the point of the two ends of the inductance. Therefore, the series shows that after the inductor flows, the wafer is fed into the wafer, and as shown in the figure: the feed pin 1 and the inductor wire 31b pass through the lead wires, respectively. , 〇, ^, 八, then borrow the lead h, g, f, e = 3: ', or select any of them as the inductor 4: connect to the external supply (4), thereby adjusting the outlet The required ^ aa, the 轭 罘 罘 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The need for different circuits within the perimeter. In this case, the molding process can also be performed to form a package colloid covering the wafer, the foot, the wafer, and the plurality of bonding wires (including the signal material & and the inductor wire 3lb'). The cross-sectional view is the same as the case. Brother ^ ^ Therefore, by the semiconductor sealing material proposed by the present invention, the required lead wires can be formed on the second welding wire and the lead frame to form the required inductance, and the heat needs to be between the two guiding legs of the lead frame. Forming a different thickness from the wafer holder and the lead, the inductor section fully solves the problems of high cost of the conventional process and complicated process. In addition, compared with the prior art, the semiconductor sealing member proposed by the present invention only needs to change the connection of the insulated bonding wire, and the inductance can be changed: ^ 17765 (Revised) 13 1254424 The position of the guiding pin, The fast reading will change the inductance value of the grounding lead 1; at the same time, the value of the complex visible change...·; impeachment Γ low inductance value, can take into account the inductance. 'It can greatly shorten the time to adjust the inductance value The semiconductor package proposed by the invention is based on the wire diameter and number of the wire bond to adjust the wire diameter and number of the wire to adjust the electrical properties. (4) The above embodiments are merely illustrative and are not intended to limit the present invention. The principle of m and its functions, and the spirit and scope of the present invention: the person skilled in the art can not be violated. Therefore, the present invention ^ The application examples are modified and modified. _Protection scope should be patented as described later [Simple description of the diagram] The first diagram is the conventional conductor with inductance. Figure 2: Figure... Upper view of the placket ' < cattle V body seal 1 piece after molding 丨 = system of the invention - After the lead frame on the lead frame of the embodiment 7 see = 3 figure... paste in the contact and form the inductive brother 5 picture shows the map of the guide frame shown in Figure 3; and the line below the line of the line Figure 6 is a top view of the wire of the second embodiment of the present invention after being inductive. Connecting the day and the film [Description of the main components] 17765 (amendment) 14 1254424 10, 20, 30, 3 ( T lead frame 11, 21 bonding wires 31a, 31a, signal bonding wires 31b, 31b, inductive bonding wires 16, 28, 36, 36, wafers 18, 23, 35, 35, pads 261, 262, 263 inductor segment 31a ^ 31a5 Signal Bonding Wires 31b, 31b, Inductive Fresh Wire 12, 22, 32 Wafer Holders 14, 24, 34 Leads 34, Leads 34a, 34a, Signal Pins 34b, 34b' Inductance Leads 34c, 34c" Grounding Pins 27, 37 encapsulant 15 17765 (amendment)