TW201619988A - 電子封裝件 - Google Patents
電子封裝件 Download PDFInfo
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- TW201619988A TW201619988A TW103141348A TW103141348A TW201619988A TW 201619988 A TW201619988 A TW 201619988A TW 103141348 A TW103141348 A TW 103141348A TW 103141348 A TW103141348 A TW 103141348A TW 201619988 A TW201619988 A TW 201619988A
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- 230000005291 magnetic effect Effects 0.000 claims abstract description 63
- 239000004020 conductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000008393 encapsulating agent Substances 0.000 claims description 9
- 239000005022 packaging material Substances 0.000 claims description 5
- 229910000859 α-Fe Inorganic materials 0.000 claims description 3
- 230000004907 flux Effects 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 23
- 235000012431 wafers Nutrition 0.000 description 15
- 230000001939 inductive effect Effects 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/02—Casings
- H01F27/022—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/24—Magnetic cores
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2809—Printed windings on stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
- Geometry (AREA)
Abstract
一種電子封裝件,係包括:基體、嵌埋於該基體中之導磁件、以及設於該導磁件周圍之導體結構,使該結構產生較高磁通量,進而增加電感量。
Description
本發明係有關一種電子封裝件,尤指一種具導磁件(ferromagnetic material)之電子封裝件。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微小化(miniaturization)的封裝需求,係朝降低承載晶片之封裝基板的厚度發展。電子產品能否達到輕、薄、短、小、快之理想境界,取決於晶片在高記憶容量,寬頻及低電壓化需求之發展,惟晶片能否持續提高記憶容量與操作頻率並降低電壓需求,端視晶片上電子電路與積體化的程度,以及作為提供電子電路訊號與電源傳遞媒介所用之輸入/輸出接腳(I/O Connector)密度而定。
一般半導體應用裝置,例如通訊或高頻半導體裝置中,常需要將電阻器、電感器、電容器及振盪器(oscillator)等多數射頻(radio frequency)被動元件電性連接至所封裝之半導體晶片,俾使該半導體晶片具有特定之電流特性或發出訊號。
以球柵陣列(Ball Grid Array,簡稱BGA)半導體裝置
為例,多數被動元件雖安置於基板表面,而為了避免該等被動元件阻礙半導體晶片與多數銲墊間之電性連結及配置,傳統上多將該等被動元件安置於基板角端位置或半導體晶片接置區域以外基板之額外佈局面積上。
然而,限定被動元件之位置將縮小基板線路佈局(Routability)之靈活性;同時此舉需考量銲墊位置會導致該等被動元件佈設數量受到侷限,不利半導體裝置高度集積化之發展趨勢;甚者,被動元件佈設數量隨著半導體封裝件高性能之要求而相對地遽增,如採習知方法該基板表面必須同時容納多數半導體晶片以及較多被動元件而造成封裝基板面積加大,進而迫使封裝件體積增大,亦不符合半導體封裝件輕薄短小之發展潮流。
基於上述問題,遂將該多數被動元件製作成集總元件(如晶片型電感)整合至半導體晶片與銲墊區域間之基板區域上。如第1圖所示之半導體封裝件1,其於一具有線路層11之基板10上設置一半導體晶片13及複數電感元件12,且該半導體晶片13藉由複數銲線130電性連接該線路層11之銲墊110。
惟,隨著半導體裝置內單位面積上輸出/輸入連接端數量的增加,銲線130之數量亦隨之提昇,且一般電感元件12之高度(0.8毫米)係高於該半導體晶片13之高度(0.55毫米),故銲線130容易碰觸該電感元件12而造成短路。
再者,若欲避免上述短路問題,需將該銲線130之弧
度拉高並橫越該電感元件12之上方,但此方式將提高銲接之困難度並增加製程複雜性,且增加該銲線130之弧線(Wire Loop)之長度,故將大幅提升該銲線130之製作成本,且該銲線130本身具有重量,若拉高之銲線130缺乏支撐,易因該銲線130本身重力崩塌(Sag)而碰觸該電感元件12,因而導致短路。
又,該電感元件12係為晶片型,故其所需體積大,特別是電源電路所需之電感元件12,且寄生(parasitic)效應隨著該電感元件12遠離該半導體晶片13而增加。
另外,以線圈型電感12’取代該電感元件12,如第1’圖所示,以避免上述問題,但該線圈型電感12’僅設在該基板10上,使該線圈型電感12’所產生之電感模擬值為17nH(於2.0mm×1.25mm之面積上),致使該線圈型電感12’之電感值過小而不符合需求。
因此,如何克服上述習知技術之種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:基體,係具有相對之第一側與第二側;導磁件,係嵌埋於該基體中,且該導磁件具有與該第一側同向之第一表面、相對該第一表面之第二表面、及鄰接該第一與第二表面之側面;以及導體結構,係設於該導磁件周圍。
前述之電子封裝件中,該基體係包含具有開口之芯
板,且該導磁件位於該開口中。
前述之電子封裝件中,該基體係包含封裝膠體,使該導磁件嵌埋於該封裝膠體中。
前述之電子封裝件中,該導磁件係為鐵素體。
前述之電子封裝件中,該導體結構係為迴狀線圈,使該導磁件位於該迴狀線圈中。例如,該迴狀線圈之路徑係依序經過該導磁件之第一表面、側面、第二表面及側面;或者,該迴狀線圈之路徑係環繞該導磁件之側面。
前述之電子封裝件中,該導體結構具有分別設於該第一側與第二側上之金屬層、及連通該第一側與第二側並連接該金屬層之複數導電柱。
前述之電子封裝件中,該導體結構係接觸該導磁件。例如,該導體結構係包含形成於該導磁件上之複數導電跡線。
前述之電子封裝件中,該導磁件外包覆有封裝材,且該封裝材嵌埋於該基體中。
另外,前述之電子封裝件中,該導體結構係為跡線層,且設於該導磁件之第一表面上方及/或第二表面上方,而未設於該導磁件之側面上。
由上可知,本發明之電子封裝件中,主要藉由該導體結構環繞該導磁件,使該導磁件與該導體結構產生之磁通量增加,以增加電感量,而增加電感值。
再者,藉由該導磁件之設計,可增加單一線圈之電感值,故相較於習知無導磁件之線圈型電感,本發明可用較
少的線圈數量達到相同的電感值,因而能微小化電感之體積。
1‧‧‧半導體封裝件
10‧‧‧基板
11‧‧‧線路層
110‧‧‧銲墊
12‧‧‧電感元件
12’‧‧‧線圈型電感
13‧‧‧半導體晶片
130‧‧‧銲線
2,2’,3,4,5,5’‧‧‧電子封裝件
20,20’‧‧‧基體
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧芯板
200a‧‧‧開口
200’‧‧‧封裝膠體
201‧‧‧介電層
21‧‧‧導磁件
21a‧‧‧第一表面
21b‧‧‧第二表面
21c‧‧‧側面
22,22’,32,52,52’‧‧‧導體結構
220,220’‧‧‧金屬層
221‧‧‧導電柱
322‧‧‧導電跡線
44‧‧‧封裝材
第1及1’圖係為習知半導體封裝件之剖視示意圖;第2A圖係為本發明之電子封裝件之第一實施例之剖視示意圖;其中,第2A’圖係為第2A圖之局部立體圖;第2B圖係為本發明之電子封裝件之第二實施例之剖視示意圖;其中,第2B’圖係為第2B圖之局部立體分解圖;第3圖係為本發明之電子封裝件之第三實施例之剖視示意圖;其中,第3’圖係為第3圖之局部立體圖,且第3”圖係為第3圖之局部上視圖;第4圖係為本發明之電子封裝件之第四實施例之剖視示意圖;以及第5A及5B圖係為本發明之電子封裝件之第五實施例之不同態樣之剖視示意圖;其中,第5A’圖係為第5圖之局部上視圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定
條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A及2A’圖係為本發明之電子封裝件2之第一實施例之示意圖。
如第2A及2A’圖所示,該電子封裝件2係包括:一基體20、嵌埋於該基體20中之一導磁件21、設於該導磁件21周圍的導體結構22、設於該基體20上之電子元件(圖略)、以及結合該基體20之線路層(圖略)。
所述之基體20係具有相對之第一側20a與第二側20b,且該基體20包含一具有開口200a之芯板200及一覆蓋該芯板200之介電層201,使該導磁件21位於該開口200a中,並以該介電層201包覆該導磁件21,其中,該介電層201之表面係作為該第一側20a之表面與該第二側20b之表面。具體地,該芯板200係為陶瓷基板、金屬板、銅箔基板、線路板等。
所述之導磁件21係為高磁導率(permeability)之導磁件,如鐵素體(ferrite),其具有與該第一側20a同向之第一表面21a、相對該第一表面21a之第二表面21b(其與該
第二側20b同向)、及鄰接該第一與第二表面21a,21b之側面21c,其中,該介電層201流入該開口200a中以包覆該導磁件21之第一表面21a、第二表面21b及側面21c。
所述之導體結構22係與該導磁件21產生磁通量,並使該導體結構22與該導磁件21構成電感。
所述之電子元件係為主動元件、被動元件或其組合者,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於此,該電子元件係為主動元件。
所述之線路層係設於該芯板200與該介電層201上,且該線路層具有複數貫穿該芯板200與該介電層201之導電盲孔(圖略)。
於本實施例中,該導體結構22係為一橫向迴狀線圈,使該導磁件21位於該迴狀線圈中,且該迴狀線圈之路徑係依序經過該導磁件21之第一表面21a、側面21c、第二表面21b及側面21c。
具體地,該導體結構22具有分別設於該第一側20a與第二側20b上之金屬層220、及連通該第一側20a與第二側20b並連接該金屬層220之複數導電柱221,且該金屬層220係為直線狀跡線層(如第2A’圖所示),使該金屬層220之佈設對應該導磁件21之第一表面21a及第二表面21b,而該些導電柱221之佈設對應該導磁件21之側面21c。
又,於製作時,先將該導磁件21放入該開口200a中,再形成該介電層201以包覆該導磁件21,之後製作該導體結構22。
另外,該金屬層220與該導電柱221係為銅材,且以佈線(routing)製程製作。
第2B及2B’圖係為本發明之電子封裝件2’之第二實施例之示意圖。本實施例與第一實施例之差異在於迴狀線圈之態樣與基體之態樣,故僅說明相異處,而其它相同處不再贅述。
如第2B及2B’圖所示,該導體結構22’係為一縱向迴狀線圈,且該迴狀線圈之路徑係環繞該導磁件21之側面21c。
於本實施例中,該金屬層220’係為繞圈狀跡線層,且該金屬層220’之佈設對應該導磁件21之側面21c,並使該些導電柱221疊架各該金屬層220’。
再者,該金屬層220’係為銅層,且以佈線(routing)製程製作。
又,該基體20’係以模壓(molding)製程製作之封裝膠體200’取代芯板200,使該導磁件21嵌埋於該封裝膠體200’中,且可選擇性形成該介電層201。具體地,若該封裝膠體200’外露該導磁件21之第一表面21a及/或第二表面21b,該介電層201將壓合於該導磁件21之第一表面21a及/或第二表面21b上,如第2B圖所示,該介電層201覆蓋該導磁件21之第一表面21a及第二表面21b;若該封裝膠體200’包覆該導磁件21之第一表面21a、第二表面21b及側面21c時,則可省略該介電層201之製作。
另外,亦可將封裝膠體200’應用於第一實施例之電
子封裝件。
第3、3’及3”圖係為本發明之電子封裝件3之第三實施例之示意圖。本實施例與第一實施例之差異在於迴狀線圈之設計,故僅說明相異處,而其它相同處不再贅述。
如第3、3’及3”圖所示,該導體結構32係接觸該導磁件21。
於本實施例中,該導體結構32係包含附著於該導磁件21上之複數導電跡線322,且該導電跡線322自該第一表面21a經該側面21c而延伸至該第二表面21b,使該導電柱221接觸該第一表面21a與該第二表面21b上之導電跡線322,以令該導體結構32構成另一橫向迴狀線圈,且該導磁件21位於該迴狀線圈中。
再者,該導電跡線322可用濺鍍(Sputtering)、塗佈(coating)或電鍍(plating)製程製作。
另外,亦可將導電跡線322應用於第二實施例之電子封裝件,且該金屬層220’或導電柱221接觸該導電跡線322。
第4圖係為本發明之電子封裝件4之第四實施例之剖視示意圖。本實施例與第一實施例之差異在於導磁件之設計,故僅說明相異處,而其它相同處不再贅述。
如第4圖所示,該導磁件21外包覆有封裝材44,使該封裝材44嵌埋於該基體20中。
於本實施例中,先將封裝材44包覆該導磁件21,再一併埋設於該開口200a中,並以該介電層201包覆該封裝
材44。具體地,該封裝材44覆蓋該導磁件21之第一表面21a、第二表面21b及側面21c。
再者,該金屬層220係為線路重佈層(Redistribution layer,簡稱RDL),故該金屬層220可與該線路層一同製作於該芯板200或該介電層201上。
另外,亦可將該導磁件21外包覆有封裝材44之態樣應用於第二及第三實施例之電子封裝件。
第5A、5A’及5B圖係為本發明之電子封裝件5,5’之第五實施例之示意圖。本實施例與第一實施例之差異在於該導體結構之態樣,故僅說明相異處,而其它相同處不再贅述。
如第5A及5A’圖所示,該導體結構52係為繞圈狀跡線層且無導電柱,該導體結構52係設於該導磁件21之第一表面21a上方及/或第二表面21b上方,而未設於該導磁件21之側面21c。
於本實施例中,該導體結構52係設於對應該導磁件21之第一表面21a上之該基體20之第一側20a上,如第5A’圖所示,該導體結構52盤據於該第一表面21a上方。
或者,如第5B圖所示,該導體結構52’設於對應該導磁件21之第一表面21a上之該基體20之第一側20a上、及對應該導磁件21之第二表面21b上之該基體20之第二側20b上。
另外,亦可將封裝膠體200’、導電跡線322與導電柱221、封裝材44等結構應用於第五實施例之電子封裝件。
本發明之電子封裝件2,2’,3,4,5,5’藉由該導體結構22,22’,32,52,52’環繞該導磁件21,使磁場將趨向於集中在低磁阻的鐵磁路徑(ferromagnetic path),即該導磁件21,因而得以增加磁通量,進而增加電感量,使本發明之電感值可提高至75nH(Henry)(遠大於習知技術之17nH)。
再者,本發明藉由該導磁件21之設計,可增加單一線圈之電感值,故相較於習知無磁鐵之線圈型電感,本發明可用較少的線圈數量達到相同的電感值。例如,習知線圈型電感需三圈線圈才能達到17nH,而本發明之迴狀線圈僅需一圈即可達到17nH。
又,本發明之電感係由該導體結構22,22’,32,52,52’與該導磁件21所構成,故能依需求微小化電感之體積。例如,欲達到相同的電感值,本發明之迴狀線圈之圈數少於習知線圈型電感之圈數圈,因而減少電感之體積,且該導磁件21內部可無需設計線路(即純導磁材質),因而其體積可依需求減少,故本發明之電感符合微小化之需求。
因此,相較於習知技術,本發明之電子封裝件2,2’,3,4,5,5’能以更小的佈設範圍製作電感並產生更大的電感值。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧基體
20a‧‧‧第一側
20b‧‧‧第二側
200‧‧‧芯板
200a‧‧‧開口
201‧‧‧介電層
21‧‧‧導磁件
21a‧‧‧第一表面
21b‧‧‧第二表面
21c‧‧‧側面
22‧‧‧導體結構
220‧‧‧金屬層
221‧‧‧導電柱
Claims (12)
- 一種電子封裝件,係包括:基體,係具有相對之第一側與第二側;導磁件,係嵌埋於該基體中,且該導磁件具有與該第一側同向之第一表面、相對該第一表面之第二表面、及鄰接該第一與第二表面之側面;以及導體結構,係設於該導磁件周圍。
- 如申請專利範圍第1項所述之電子封裝件,其中,該基體係包含具有開口之芯板,且該導磁件位於該開口中。
- 如申請專利範圍第1項所述之電子封裝件,其中,該基體係包含封裝膠體,使該導磁件嵌埋於該封裝膠體中。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導磁件係為鐵素體。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導體結構係為迴狀線圈,使該導磁件位於該迴狀線圈中。
- 如申請專利範圍第5項所述之電子封裝件,其中,該迴狀線圈之路徑係依序經過該導磁件之第一表面、側面、第二表面及側面。
- 如申請專利範圍第5項所述之電子封裝件,其中,該迴狀線圈之路徑係環繞該導磁件之側面。
- 如申請專利範圍第1項所述之電子封裝件,其中,該 導體結構具有分別設於該第一側與第二側上之金屬層、及連通該第一側與第二側並連接該金屬層之複數導電柱。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導體結構係接觸該導磁件。
- 如申請專利範圍第9項所述之電子封裝件,其中,該導體結構係包含形成於該導磁件上之複數導電跡線。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導磁件外包覆有封裝材,且該封裝材嵌埋於該基體中。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導體結構係為跡線層,且設於該導磁件之第一表面上方及/或第二表面上方。
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