TW201304092A - 半導體承載件暨封裝件及其製法 - Google Patents

半導體承載件暨封裝件及其製法 Download PDF

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TW201304092A
TW201304092A TW100124166A TW100124166A TW201304092A TW 201304092 A TW201304092 A TW 201304092A TW 100124166 A TW100124166 A TW 100124166A TW 100124166 A TW100124166 A TW 100124166A TW 201304092 A TW201304092 A TW 201304092A
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Taiwan
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nickel
gold
encapsulation layer
semiconductor
palladium
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TW100124166A
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林邦群
蔡岳穎
陳泳良
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矽品精密工業股份有限公司
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Priority to TW100124166A priority Critical patent/TW201304092A/zh
Priority to CN2011102080312A priority patent/CN102867801A/zh
Priority to US13/308,938 priority patent/US20130009311A1/en
Publication of TW201304092A publication Critical patent/TW201304092A/zh

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    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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  • Lead Frames For Integrated Circuits (AREA)

Abstract

一種半導體承載件暨封裝件及其製法，該半導體封裝件包括：第一封裝層、電性接點、複數線路、半導體晶片與第二封裝層，該第一封裝層具有複數貫穿之頂寬底窄之錐形孔，該電性接點形成於各該錐形孔中而呈錐形，該等線路形成於該第一封裝層之頂面上，各該線路之一端連接各該電性接點，另一端形成有銲指墊，該等銲指墊係圍繞配置以藉之定義出一置晶區，俾供半導體晶片設置於該置晶區中的第一封裝層頂面上，並令該半導體晶片電性連接各該銲指墊，且該第二封裝層覆蓋該半導體晶片、線路與第一封裝層。本發明能有效避免電性接點脫落、並縮減導電元件的長度。

Description

半導體承載件暨封裝件及其製法
本發明係有關於一種承載件暨封裝件及其製法，尤指一種半導體承載件暨封裝件及其製法。
四方平面無導腳(Quad Flat No Lead，簡稱QFN)半導體封裝件為一種使晶片座和接腳底面外露於封裝層底部表面的封裝單元，一般係採用表面黏著技術(surface mount technology，簡稱SMT)將四方平面無導腳半導體封裝件接置於印刷電路板上，藉此以形成一具有特定功能之電路模組。
請參閱第1圖，美國專利第6635957號、第6872661號、第7009286號、第7081403號、與第7371610號等先前技術揭示一種習知之四方平面無導腳半導體封裝件之剖視圖，其係先於承載板10中形成複數固定孔徑的通孔100，並以電鍍方式於各該通孔100中形成電性接點11，其中，各該電性接點11係由多次電鍍不同金屬層所疊接形成，之後再將半導體晶片12接置於該承載板10上，並進行打線製程，以將該半導體晶片12電性連接至各該電性接點11，最後，以封裝層13包覆該半導體晶片12、電性接點11與承載板10。
習知之四方平面無導腳半導體封裝件具有製作簡單、及電鍍方式形成的電性接點較小之優點；惟，由於容置該電性接點的通孔係固定孔徑，所以該電性接點容易從該通孔中脫落；此外，由於部分電性接點距離半導體晶片較遠，故其打線須耗費較長的金屬線材(例如金線)，而造成整體成本的上升。
因此，如何避免上述習知技術中之種種問題，俾使四方平面無導腳半導體封裝件的電性接點不易脫落，並減低打線所需的材料成本，實已成為目前亟欲解決的課題。
有鑒於上述習知技術之缺失，本發明提供一種半導體承載件，係包括：第一封裝層，係具有複數貫穿之頂寬底窄之錐形孔；電性接點，係形成於各該錐形孔中而呈錐形；以及複數線路，係形成於該第一封裝層之頂面上，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層之頂面上定義出一置晶區。
本發明提供一種半導體封裝件，係包括：具有複數貫穿之頂寬底窄之錐形孔的第一封裝層；形成於各該錐形孔中而呈錐形的電性接點；形成於該第一封裝層之頂面上的複數線路，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層之頂面上定義出一置晶區；設置於該置晶區中的該第一封裝層的頂面上的半導體晶片；將該半導體晶片電性連接至各該銲指墊的複數導電元件；以及覆蓋該半導體晶片、導電元件、線路與第一封裝層的第二封裝層。
本發明復提供一種半導體承載件之製法，係包括：於一承載板上形成第一封裝層；於該第一封裝層中形成複數頂寬底窄之錐形孔，以外露該承載板；以及於各該錐形孔中形成錐形之電性接點，並於該第一封裝層上形成複數線路，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層上定義出一置晶區。
本發明復提供一種半導體封裝件之製法，係包括：於一承載板上形成第一封裝層；於該第一封裝層中形成複數頂寬底窄之錐形孔，以外露該承載板；於各該錐形孔中形成錐形之電性接點，並於該第一封裝層上形成複數線路，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層上定義出一置晶區；於該置晶區中的該第一封裝層上接置半導體晶片；形成複數導電元件，以藉由該導電元件將該半導體晶片電性連接至該銲指墊；形成覆蓋該半導體晶片、導電元件、線路與第一封裝層的第二封裝層；以及移除該承載板。
由上可知，本發明之半導體承載件暨封裝件係於第一封裝層中形成孔徑漸縮之錐形孔，所以該電性接點無法從該錐形孔滑出或脫落，而能提升整體可靠度；此外，本發明之封裝件可於接置有半導體晶片之該側的表面上佈設複數連接各該電性接點的線路，並藉由該線路的銲指墊以拉近導電元件的打線距離，故能有效縮減導電元件所需之長度，進而減低整體製造成本。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“頂”、“底”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2L圖，係本發明之半導體承載件暨封裝件及其製法之剖視圖，其中，第2F’圖係部分第2F圖的俯視圖。
如第2A圖所示，準備一承載板20。
如第2B圖所示，於該承載板20上形成第一封裝層21。
如第2C圖所示，以例如雷射鑽孔或機械鑽孔的技術於該第一封裝層21中形成複數頂寬底窄之錐形孔210，以外露該承載板20。
如第2D圖所示，於該具有錐形孔210之第一封裝層21上形成阻層22，該阻層22具有複數外露該錐形孔210與第一封裝層21之阻層開口區220。
如第2E圖所示，於該阻層開口區220中的錐形孔210中形成電性接點231，並於該阻層開口區220中的電性接點231與第一封裝層21上形成線路232；要注意的是，該電性接點231與線路232可如前述地一體成型，或者，該電性接點231與線路232可分別成型，即先形成該電性接點231，之後再形成該線路232，然而由於此分別成型之步驟係本發明所屬技術領域之通常知識者所能輕易瞭解，故在此並未加以圖示說明。
如第2F與2F’圖所示，移除該阻層22，由圖可知，該線路232之一端連接各該電性接點231，各該線路232之另一端具有銲指墊(finger)232a，該等銲指墊232a係圍繞配置，以於該第一封裝層21上定義出一置晶區B；其中，第2F’圖係第2F圖之區域A的俯視圖。
要注意的是，至此即完成本發明之半導體承載件，但是本發明之半導體承載件可不具有該承載板20，因此亦可於此時即移除該承載板20，然而由於此步驟係本發明所屬技術領域之通常知識者所能輕易瞭解，故在此並未加以圖示說明。
如第2G圖所示，藉由黏著層24而於該置晶區B中的該第一封裝層21上接置半導體晶片25。
如第2H圖所示，形成複數導電元件26，以藉由該導電元件26將該半導體晶片25電性連接至該銲指墊232a，其中，該導電元件26可為金屬線。
如第2I圖所示，形成覆蓋該半導體晶片25、導電元件26、線路232與第一封裝層21的第二封裝層27。
如第2J圖所示，移除該承載板20。
如第2K圖所示，於該第一封裝層21底面之各該電性接點231上形成銲球28。
如第2L圖所示，進行切單製程，以得到複數四方平面無導腳半導體封裝件2。
本發明復提供一種半導體承載件，係包括：第一封裝層21，係具有複數貫穿之頂寬底窄之錐形孔210；電性接點231，係形成於各該錐形孔210中而呈錐形；以及複數線路232，係形成於該第一封裝層21之頂面上，各該線路232之一端連接各該電性接點231，各該線路232之另一端形成有銲指墊(finger)232a，該等銲指墊232a係圍繞配置，以於該第一封裝層21之頂面上定義出一置晶區B。
於前述之半導體封承載件中，復可包括承載板20，係設於該第一封裝層21之底面上。
依上所述之半導體承載件，該電性接點231可為金/鈀/鎳/鈀、金/鎳/銅/鎳/金、金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金、或鈀/鎳/金之自底部依序構成的多層金屬。
於本實施例之半導體承載件中，該電性接點與線路可一體成型或分別成型。
本發明復提供一種半導體封裝件2，係包括：第一封裝層21，係具有複數貫穿之頂寬底窄之錐形孔210；電性接點231，係形成於各該錐形孔210中而呈錐形；複數線路232，係形成於該第一封裝層21之頂面上，各該線路232之一端連接各該電性接點231，各該線路232之另一端形成有銲指墊(finger)232a，該等銲指墊232a係圍繞配置，以於該第一封裝層21之頂面上定義出一置晶區B；半導體晶片25，係設置於該置晶區B中的該第一封裝層21的頂面上；複數導電元件26，係將該半導體晶片25電性連接至各該銲指墊232a；以及第二封裝層27，係覆蓋該半導體晶片25、導電元件26、線路232與第一封裝層21。
於前述之半導體封裝件2中，復可包括銲球28，係形成於該第一封裝層21底面之各該電性接點231上。
所述之半導體封裝件2中，於該半導體晶片25與該第一封裝層21之間復可包括黏著層24，且該黏著層24之材質可為玻璃粉(glass frit)、環氧樹脂(epoxy)、或乾膜(dry film)。
依上所述之半導體封裝件2，該電性接點231可為金/鈀/鎳/鈀、金/鎳/銅/鎳/金、金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金、或鈀/鎳/金之自底部依序構成的多層金屬。
於本實施例之半導體封裝件2中，該電性接點與線路可一體成型或分別成型。
綜上所述，相較於習知技術，本發明之半導體承載件暨封裝件係於第一封裝層中形成頂寬底窄之錐形孔，所以於該錐形孔中所形成的電性接點在最終封裝完成後不會有滑出或脫落的問題發生，而能提升整體可靠度；其次，本發明之封裝件可於接置有半導體晶片之該側的表面上佈設複數連接各該電性接點的線路，且各該線路具有鄰近半導體晶片的銲指墊，使得導電元件不需連接在距離較遠的電性接點位置處，而僅需連接在距離較近的銲指墊上，再經由該線路而連接至電性接點，故可有效縮減導電元件之長度，進而減低整體製造成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10,20．．．承載板
100．．．通孔
11．．．電性接點
12．．．半導體晶片
13．．．封裝層
2．．．半導體封裝件
21．．．第一封裝層
210．．．錐形孔
22．．．阻層
220．．．阻層開口區
231．．．電性接點
232．．．線路
232a．．．銲指墊
24．．．黏著層
25．．．半導體晶片
26．．．導電元件
27．．．第二封裝層
28．．．銲球
A．．．區域
B．．．置晶區
第1圖係一種習知之四方平面無導腳半導體封裝件之剖視圖；以及
第2A至2L圖係本發明之半導體承載件暨封裝件及其製法之剖視圖，其中，第2F’圖係部分第2F圖的俯視圖。
21．．．第一封裝層
210．．．錐形孔
231．．．電性接點
232．．．線路
232a．．．銲指墊
24．．．黏著層
25．．．半導體晶片
26．．．導電元件
27．．．第二封裝層
28．．．銲球
2．．．半導體封裝件
B．．．置晶區

Claims (25)

  1. 一種半導體承載件，係包括：第一封裝層，係具有複數貫穿之頂寬底窄之錐形孔；電性接點，係形成於各該錐形孔中而呈錐形；以及複數線路，係形成於該第一封裝層之頂面上，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層之頂面上定義出一置晶區。
  2. 如申請專利範圍第1項所述之半導體承載件，復包括承載板，係設於該第一封裝層之底面上。
  3. 如申請專利範圍第1項所述之半導體承載件，其中，該電性接點係為金/鈀/鎳/鈀、金/鎳/銅/鎳/金、金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金、或鈀/鎳/金之自底部依序構成的多層金屬。
  4. 如申請專利範圍第1項所述之半導體承載件，其中，該電性接點與線路係一體成型或分別成型。
  5. 一種半導體封裝件，係包括：第一封裝層，係具有複數貫穿之頂寬底窄之錐形孔；電性接點，係形成於各該錐形孔中而呈錐形；複數線路，係形成於該第一封裝層之頂面上，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層之頂面上定義出一置晶區；半導體晶片，係設置於該置晶區中的該第一封裝層的頂面上；複數導電元件，係將該半導體晶片電性連接至各該銲指墊；以及第二封裝層，係覆蓋該半導體晶片、導電元件、線路與第一封裝層。
  6. 如申請專利範圍第5項所述之半導體封裝件，復包括銲球，係形成於該第一封裝層底面之各該電性接點上。
  7. 如申請專利範圍第5項所述之半導體封裝件，其中，於該半導體晶片與該第一封裝層之間復包括黏著層。
  8. 如申請專利範圍第7項所述之半導體封裝件，其中，該黏著層之材質係為玻璃粉、環氧樹脂、或乾膜。
  9. 如申請專利範圍第5項所述之半導體封裝件，其中，該電性接點係為金/鈀/鎳/鈀、金/鎳/銅/鎳/金、金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金、或鈀/鎳/金之自底部依序構成的多層金屬。
  10. 如申請專利範圍第5項所述之半導體封裝件，其中，該電性接點與線路係一體成型或分別成型。
  11. 一種半導體承載件之製法，係包括：於一承載板上形成第一封裝層；於該第一封裝層中形成複數頂寬底窄之錐形孔，以外露該承載板；以及於各該錐形孔中形成錐形之電性接點，並於該第一封裝層上形成複數線路，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層上定義出一置晶區。
  12. 如申請專利範圍第11項所述之半導體承載件之製法，復包括移除該承載板。
  13. 如申請專利範圍第11項所述之半導體承載件之製法，其中，該電性接點與線路之形成步驟係包括：於該具有錐形孔之第一封裝層上形成阻層，該阻層具有複數外露該錐形孔與第一封裝層之阻層開口區；於該阻層開口區中形成該電性接點與線路；以及移除該阻層。
  14. 如申請專利範圍第11項所述之半導體承載件之製法，其中，該電性接點係為金/鈀/鎳/鈀、金/鎳/銅/鎳/金、金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金、或鈀/鎳/金之自底部依序構成的多層金屬。
  15. 如申請專利範圍第11項所述之半導體承載件之製法，其中，形成該錐形孔之方式係為雷射鑽孔或機械鑽孔。
  16. 如申請專利範圍第11項所述之半導體承載件之製法，其中，該電性接點與線路係一體成型或分別成型。
  17. 一種半導體封裝件之製法，係包括：於一承載板上形成第一封裝層；於該第一封裝層中形成複數頂寬底窄之錐形孔，以外露該承載板；於各該錐形孔中形成錐形之電性接點，並於該第一封裝層上形成複數線路，各該線路之一端連接各該電性接點，各該線路之另一端形成有銲指墊，該等銲指墊係圍繞配置，以於該第一封裝層上定義出一置晶區；於該置晶區中的該第一封裝層上接置半導體晶片；形成複數導電元件，以藉由該導電元件將該半導體晶片電性連接至該銲指墊；形成覆蓋該半導體晶片、導電元件、線路與第一封裝層的第二封裝層；以及移除該承載板。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該電性接點與線路之形成步驟係包括：於該具有錐形孔之第一封裝層上形成阻層，該阻層具有複數外露該錐形孔與第一封裝層之阻層開口區；於該阻層開口區中形成該電性接點與線路；以及移除該阻層。
  19. 如申請專利範圍第17項所述之半導體封裝件之製法，復包括於該第一封裝層底面之各該電性接點上形成銲球。
  20. 如申請專利範圍第17或19項所述之半導體封裝件之製法，復包括進行切單製程。
  21. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該半導體晶片係藉由黏著層而接置於該第一封裝層上。
  22. 如申請專利範圍第21項所述之半導體封裝件之製法，其中，該黏著層之材質為玻璃粉、環氧樹脂、或乾膜。
  23. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該電性接點係為金/鈀/鎳/鈀、金/鎳/銅/鎳/金、金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金、或鈀/鎳/金之自底部依序構成的多層金屬。
  24. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，形成該錐形孔之方式係為雷射鑽孔或機械鑽孔。
  25. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該電性接點與線路係一體成型或分別成型。
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