TW201508881A - 一種無基板器件及其製造方法 - Google Patents

一種無基板器件及其製造方法 Download PDF

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TW201508881A
TW201508881A TW103125213A TW103125213A TW201508881A TW 201508881 A TW201508881 A TW 201508881A TW 103125213 A TW103125213 A TW 103125213A TW 103125213 A TW103125213 A TW 103125213A TW 201508881 A TW201508881 A TW 201508881A
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conductive elements
circuit pattern
pattern layer
conductive
terminals
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Bau-Ru Lu
Ming-Chia Wu
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Cyntec Co Ltd
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Abstract

一種無基板器件包含複數個第一導電元件和一封裝材料(encapsulant)。該封裝材料包覆該複數個第一導電元件，其中上述複數個第一導電元件的位置係由封裝材料來固定，以及所述複數個第一導電元件的複數個端子係露出於封裝材料的外部，其中所述複數個第一導電元件係沒有基板支撐的。

Description

一種無基板器件及其製造方法
本發明係有關於一種封裝結構，特別是有關於一種無基板器件。
導線架是用於集成電路封裝的材料，並且能以在各種封裝形式如QFP，TSOP，SOT 或SOJ。模制半導體器件係由組裝及互連一半導體器件與一導線架所構成。這樣的結構經常以塑性材料來模制成型。一導線架係由具有一連接盤（也稱為裸晶連接盤(die paddle)，裸晶黏著標簽(die-attach tab)或島狀物）之金屬帶用以黏接一半導體器件於其上以及複數個導線製作而成。複數個導線以不會重疊到有半導體器件接著於上的焊盤之方式來配置。
通常，導線架係用於集成電路晶片的裸晶連接。製程包括許多階段，包括引線接合，IC晶片的鑄型，並經過修整或鑄型之後的測試。各種產品可以透過整合或封裝導線架及其他器件如電感器或電容器等來製成。由於其容易，成熟及較佳的可信度，在工業上這是一主要封裝製程。然而，這樣一種常規製程有許多缺點，包括：a. 較高的成本和鑄型器件的更多開發工程; b.僅是在平面的形式之區域設計力較差；c. 它唯一好的僅是封裝單一器件，欠缺模組化能力；d. 散熱和產量之表現差；及e. 因為一大塊體積的導線架，難以縮小模組尺寸。因此，本發明提出了一種無基板器件及其製造方法以克服上述的缺點。
本發明的一個目的係提供一種沒有基板支撐的無基板器件。它不需要的導線架或印刷電路板以支持導電元件，使得該材料成本可降低，並且元件尺寸可以縮小。此外，該引腳位置和器件的引腳數量可根據設計需求而更動。無基板器件包含：複數個第一導電元件，以及ㄧ包覆所述複數個第一導電元件之封裝材料，其中上述複數個第一導電元件的位置係由封裝材料來固定，以及所述複數個第一導電元件的複數個端子係露出於封裝材料的外部，其中所述複數個第一導電元件係沒有基板支撐的。
最好地是第一導電元件的端子係露出於封裝材料的底部表面之外。這無基板器件更能包含一配置於封裝材料的底部表面上的一電路圖案層。
本發明的另一個目的係提供一種形成無基板器件的方法。該方法包含了下列步驟：提供複數個第一導電元件，並形成一封裝材料以包覆該複數個第一導電元件，其中上述複數個第一導電元件的位置係由封裝材料來固定，以及所述複數個第一導電元件的複數個端子係露出於封裝材料的外部，其中所述複數個第一導電元件係沒有基板支撐的。
在一個實施例中，提供一支橕體；在該支橕體上配置複數個第一導電元件；並形成一封裝材料以包覆該複數個第一導電元件；以及移除該支橕體以將上述複數個第一導電元件的複數個端子露出於外。上述支橕體的功用係使沒有基板支撐的第一導電元件定位於其上。上述支橕體可能是一載體 (例如玻璃基板) 或是一膠帶。
在參閱接下來的段落及所附圖式所描述之本發明的實施例及詳細技術之後，該技術領域具有通常知識者便可瞭解本發明之技術特徵及實施態樣。
本發明的詳細說明於隨後描述，這裡所描述的較佳實施例是作為說明和描述的用途，並非用來限定本發明之範圍。
本發明揭露一種沒有基板支撐的無基板器件。一種無基板器件包含: 複數個第一導電元件；和一封裝材料(encapsulant)。該封裝材料包覆該複數個第一導電元件，其中上述複數個第一導電元件的位置係由封裝材料來固定，以及所述複數個第一導電元件的複數個端子係露出於封裝材料的外部，其中所述複數個第一導電元件係沒有基板支撐的。該無基板器件的包含如下優點: 1. 它無需一導電架或依印刷電路板支撐導電元件，因此可降低材料成本並可縮小器件的尺寸；2. 可依據設計上的需要修改器件的引腳位置和引腳數量；3. 該器件具有最短的電路路徑以致可降低電路阻抗及提高電效率；4. 它是適合用於電路模組化；5. 表面黏著技術；6. 該封裝材料可保護在其中的導電元件；7. 電鍍導孔製程可用來形成一電路圖案層以降低阻抗及散熱；8. 因器件整合及空間堆疊，使它佔有較小的模組面積。
第1A圖例示本發明之一種無基板器件10的剖面示意圖。第1B圖例示在封裝材料12的底部表面上具有一電路圖案層13之一種無基板器件10的剖面示意圖。該無基板器件10包含複數個第一導電元件11及一封裝材料12。最好是該無基板器件10具有一電路圖案層13於封裝材料12的底部表面上。
每個第一導電元件可包含積體電路晶片、□氧半場效電晶體(MOSFET)、絕緣閘雙極電晶體(IGBT)、二極體、電阻、電感或者電容之至少其中一個元件。一封裝材料12形成以包覆該第一導電元件11。該封裝材料12可係由任何適合的材料而形成，例如環氧樹脂，氧化物，或高分子為基礎的材料。複數個第一導電元件11的複數個端子係露出於封裝材料12的外部以做為類似電極的作用。最好是第一導電元件11的端子係露出於封裝材料12的底部表面之外。換言之，第一導電元件11的電極係配置於表面，為了做外部的電連接，最好是配置於封裝材料12的底部表面，因此可縮點與第一導電元件11之間的距離。
請參閱實施例的第1B圖，在封裝材料12的底部表面上形成一電路圖案層13以電連接第一導電元件11的端子，更使得第一導電元件11之一電極延伸以作為第一導電元件11與外部的電連接。最好是電路圖案層13直接連接於第一導電元件11的端子。電路圖案層13可包含複數個電路層。例如，電路圖案層13包含一上方重新分配層(RDL)13a，一下方重新分配層(RDL)13b以及一位於上方重新分配層(RDL)13a 與一下方重新分配層(RDL)13b之間的導孔層13c。一上方重新分配層13a使得第一導電元件11之間的電連接，而一下方重新分配層13b更進一步延伸第一導電元件11之電極以做外部連接。
第1C圖例示一種無基板器件10的剖面示意圖，其中第二導電元件14係配置於電路圖案層13。為了縮小模組尺寸，第二導電元件14可配置於電路圖案層13裡。第二導電元件14至少具有一端子(未顯示)，至少第二導電元件14的一端子係電連接於電路圖案層13。配置第二導電元件14有許多方式：每一第二導電元件14可配置於其中之一電路層；其中之一第二導電元件14可配置於其中之一電路層，而另一第二導電元件14可配置於另一電路層；或者是全部的第二導電元件14可配置於其中之一電路層。
第1D圖至第1F圖例示裡面具有一遮蔽物15之一種無基板器件10的剖面示意圖。依據電力規格的要求，無基板器件10更可包含一遮蔽物15以降低在導電元件之間或模組之間的干擾。例如,第一導電元件11的表面或周邊之至少一部分係具有封裝材料12中的一遮蔽物15以遮蓋(第1D圖)；在封裝材料12表面之至少一部分係具有一遮蔽物15以遮蓋(第1D圖及第1F圖)。
第2圖為製造第1A圖及第1B圖之一種無基板器件的製程。
製程的步驟31係提供複數個第一導電元件11，而該複數個第一導電元件的每個第一導電元件可包含積體電路晶片、□氧半場效電晶體(MOSFET)、絕緣閘雙極電晶體(IGBT)、二極體、電阻、電感或者電容之至少其中一個元件。
製程的步驟32係形成一封裝材料12以包覆該複數個第一導電元件11， 其中複數個第一導電元件11的位置係由封裝材料12以固定；而該複數個第一導電元件11的複數個端子係露出於封裝材料12的外部, 其中所述複數個第一導電元件係沒有基板支撐的。最好是第一導電元件11的端子係露出於封裝材料12的底部表面之外。然後施行烘烤(post molding cure)。該封裝材料12可係由任何適合的材料而形成, 例如環氧樹脂, 氧化物, 或高分子為基礎的材料。在製程的步驟32之前，在一實施例中，該複數個第一導電元件11之至少表面的部分係具有一遮蔽物15以遮蓋。
在一個實施例中，提供一支橕體 (未顯示)；在該支橕體上配置複數個第一導電元件11；並形成一封裝材料12以包覆該複數個第一導電元件11；以及移除該支橕體以將上述複數個第一導電元件11的複數個端子露出於外。換言之, 步驟31更包含提供一支橕體並在該支橕體上配置複數個第一導電元件11；其中步驟31更包含在形成用以包覆該複數個第一導電元件11的封裝材料12之後, 移除該支橕體以將上述複數個第一導電元件11的複數個端子露出於外。另一種方式為步驟31更包含在該複數個第一導電元件11與支橕體之間形成一黏附層(未顯示)；並且步驟32更包含在移除該支橕體之後, 移除該黏附層以將上述複數個第一導電元件11的複數個端子露出於外。上述支橕體的功用係使第一導電元件定位於其上。上述支橕體可能是一載體 (例如玻璃基板) 或是一膠帶。
製程的步驟33係在封裝材料12的底部表面上形成一電路圖案層13以電連接複數個第一導電元件11的複數個端子。具體而言，電路圖案層13係形成於封裝材料12的反面底部表面上。電路圖案層13可藉由執行一微影製程而形成，其廣泛適用於形成多數個引腳以符合客戶的需要。相較於做為引腳的導電架(導電架的空間太大而無法定義製程精確度)，然而微影製程可精確地定義較小尺寸的引腳。電路圖案層13可包含複數個電路層。例如, 電路圖案層13包含一上方重新分配層(RDL)13a，一下方重新分配層(RDL)13b以及一位於上方重新分配層(RDL)13a 與一下方重新分配層(RDL)13b之間的導孔層13c。一上方重新分配層(RDL)13a使得第一導電元件11之間的電連接，而一下方重新分配層(RDL)13b更進一步延伸第一導電元件11的電極用以做外部連接。為了縮小模組尺寸，第二導電元件14可配置於電路圖案層13裡。在一實施例中, 配置一遮蔽物15以遮蓋封裝材料12表面之至少部分。
以電路圖案層13為例，其包含一上方重新分配層(RDL)13a，一下方重新分配層(RDL)13b以及一位於上方重新分配層(RDL)13a與一下方重新分配層(RDL)13b之間的導孔層13c，如下列出其詳細製程。任何電路圖案皆可由以下的製程步驟而得到，在此不會進一步詳細敘述。 (a) 執行第一微影製程以形成一上方重新分配層(RDL)13a。這步驟包含濺鍍(sputter)、乾膜壓合(dry film lamination)、曝光(exposure)、顯影(development)、電鍍(plating)、去膜 (de-film) 以及蝕刻(etching)。 (b) 執行第二微影製程以形成一導孔層13c。這步驟包含印刷(printing)、曝光(exposure)、顯影(development)以及烘烤(cure)。 (c) 執行第三微影製程以形成一下方重新分配層(RDL)13b。這步驟包含濺鍍(sputter)、乾膜壓合(dry film lamination)、曝光(exposure)、顯影(development)、電鍍(plating)、去膜 (de-film) 以及蝕刻(etching)。 (d) 執行第四微影製程以執行鎳/金電鍍。這步驟包含印刷(printing)、曝光(exposure)、顯影(development)、烘烤(cure) 、鎳電鍍以及金電鍍。
雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發明，任何熟習相像技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾。雖然在上述描述說明中並無完全揭露這些可能的更動與替代，而接著本說明書所附之專利保護範圍實質上已經涵蓋所有這些態樣。
10‧‧‧無基板器件
11‧‧‧第一導電元件
12‧‧‧封裝材料
13‧‧‧電路圖案層
13a‧‧‧上方重新分配層
13b‧‧‧下方重新分配層
13c‧‧‧導孔層
14‧‧‧第二導電元件
15‧‧‧遮蔽物
本發明之前面所述的態樣及所伴隨的優點將藉著參閱以下的詳細說明及結合圖式更加被充分瞭解。
第1A圖例示本發明之一種無基板器件的剖面示意圖；
第1B圖例示在封裝材料的底部表面上具有一電路圖案層之一種無基板器件的剖面示意圖；
第1C圖例示一種無基板器件的剖面示意圖，其中第二導電元件係配置於電路圖案層；
第1D圖至第1F圖例示裡面具有一遮蔽物之一種無基板器件的剖面示意圖；及
第2圖為製造第1A圖及第1B圖之一種無基板器件的製程。
10‧‧‧無基板器件
11‧‧‧第一導電元件
12‧‧‧封裝材料
13‧‧‧電路圖案層
13a‧‧‧上方重新分配層
13b‧‧‧下方重新分配層
13c‧‧‧導孔層
14‧‧‧第二導電元件
15‧‧‧遮蔽物

Claims (18)

  1. 一種無基板器件，包含： 複數個第一導電元件；及                   一封裝材料，包覆該複數個第一導電元件，其中上述複數個第一導電元件的位置係由封裝材料來固定，所述複數個第一導電元件的複數個端子露出於封裝材料的外部，其中所述複數個第一導電元件沒有被基板支撐。
  2. 如申請專利範圍第1項所述之無基板器件，其中所述複數個第一導電元件的複數個端子露出於封裝材料的底部表面之外。
  3. 如申請專利範圍第1項所述之無基板器件，更包含形成於封裝材料的底部表面上之一電路圖案層，其中該電路圖案層電連接於所述複數個第一導電元件的複數個端子。
  4. 如申請專利範圍第3項所述之無基板器件，更包含一配置於電路圖案層中的一第二導電元件，其中所述第二導電元件之至少一端子電連接於電路圖案層。
  5. 如申請專利範圍第3項所述之無基板器件，其中該電路圖案層包含一上方重新分配層、一下方重新分配層以及一位於該上方重新分配層與該下方重新分配層之間的一導孔。
  6. 如申請專利範圍第3項所述之無基板器件，其中該電路圖案層電路圖案層直接接觸到所述複數個第一導電元件的複數個端子。
  7. 如申請專利範圍第1項所述之無基板器件，更包含一配置於封裝材料中的一遮蔽物質以遮蓋至少該複數個第一導電元件的表面或周邊之一部分。
  8. 如申請專利範圍第1項所述之無基板器件，更包含一遮蓋了封裝材料表面的至少一部分之遮蔽物質。
  9. 如申請專利範圍第1項所述之無基板器件，其中所述複數個第一導電元件的每一元件至少包含積體電路晶片、□氧半場效電晶體(MOSFET)、絕緣閘雙極電晶體(IGBT)、二極體、電阻、電感或者電容的其中一者。
  10. 一種形成一無基板器件的方法，包含： (a) 提供一支橕體及複數個第一導電元件，並在該支橕體上配置該複數個第一導電元件； (b) 形成一封裝材料以包覆該複數個第一導電元件，其中複數個第一導電元件的位置係由封裝材料以固定; 以及 (c) 移除該支橕體以將所述複數個第一導電元件的複數個端子露出於封裝材料的外部。
  11. 如申請專利範圍第10項所述之方法，其中該複數個第一導電元件的複數個端子露出於封裝材料的底部表面之外。
  12. 如申請專利範圍第10項所述之方法，其中步驟(a)更包含在該複數個第一導電元件11與支橕體之間形成一黏附層，其中步驟(b)更包含在移除該支橕體之後，移除該黏附層以將所述複數個第一導電元件11的複數個端子露出於外。
  13. 如申請專利範圍第10項所述之方法，更包含：(c)形成一電路圖案層於封裝材料的底部表面上以電連接所述複數個第一導電元件的複數個端子。
  14. 如申請專利範圍第13項所述之方法，其中步驟(c)更包含一微影製程以形成該電路圖案層。
  15. 如申請專利範圍第14項所述之方法，其中一第二導電元件配置於電路圖案層中，其中所述第二導電元件之至少一端子電連接於該電路圖案層。
  16. 如申請專利範圍第14項所述之方法，其中該電路圖案層包含一上方重新分配層、一下方重新分配層以及一位於該上方重新分配層與該下方重新分配層之間的一導孔。
  17. 如申請專利範圍第10項所述之方法，其中該支橕體為一載體。
  18. 如申請專利範圍第10項所述之方法，其中該支橕體為一玻璃基板或一膠帶。
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US20150029678A1 (en) 2015-01-29
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US9655253B2 (en) 2017-05-16
US10529680B2 (en) 2020-01-07
US20170221849A1 (en) 2017-08-03

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