TW201630075A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TW201630075A
TW201630075A TW104135663A TW104135663A TW201630075A TW 201630075 A TW201630075 A TW 201630075A TW 104135663 A TW104135663 A TW 104135663A TW 104135663 A TW104135663 A TW 104135663A TW 201630075 A TW201630075 A TW 201630075A
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Taiwan
Prior art keywords
film
rewiring
metal film
cap
semiconductor device
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TW104135663A
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English (en)
Inventor
Kazuyoshi Maekawa
Yuichi Kawano
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201630075A publication Critical patent/TW201630075A/zh

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Abstract

本發明之半導體裝置係具有：焊墊電極9a，其形成於複數之配線層之最上層；底層絕緣膜11，其於焊墊電極9a上具有開口11a；底層金屬膜UM，其形成於底層絕緣膜11上；再配線RM，其形成於底層金屬膜UM上；及蓋金屬膜CM，其以覆蓋再配線RM之上表面及側面之方式形成。且，於再配線RM之外側之區域中，於形成於再配線RM之側壁上之蓋金屬膜CM與底層絕緣膜11之間，形成有與再配線RM不同材料之底層金屬膜UM、及與再配線RM不同材料之蓋金屬膜CM，於再配線RM之外側區域，底層金屬膜UM與蓋金屬膜CM直接相接。

Description

半導體裝置及其製造方法
本發明係關於一種半導體裝置及其製造方法，尤其是關於有效應用於在形成於半導體基板之主表面上之複數之配線層之上部具有以金屬膜構成之再配線之半導體裝置及其製造方法之技術者。
半導體裝置於形成有例如CMIS(Complementary Metal Insulator Semiconductor：互補型金屬絕緣體半導體)電晶體等之半導體元件之半導體基板之上部，以例如Cu(銅)或Al(鋁)作為主成分之金屬膜形成多層配線，且於多層配線之上部形成最終鈍化膜。
於日本特開2003-234348號公報(專利文獻1)，揭示有於最終鈍化膜上形成以Cu作為主成分之再配線，且將形成於最終鈍化膜之下之最上層配線之電極焊墊與再配線電性連接之技術。
於日本特開2012-4210號公報(專利文獻2)之圖25，揭示有於以部分覆蓋以Cu作為主要成分之再配線15之上表面及側面之方式形成之焊墊18連接導線20之構造。
於日本特開2000-306938號公報(專利文獻3)之摘要，揭示有藉由利用具有突出於鈍化膜6上之突出部位9之障壁金屬膜8完全覆蓋形成於鈍化膜4上之包含鋁合金之再配線層6，而抑制再配線層6之電子遷移或腐蝕之產生。
於“Development of highly reliable Cu wiring of L/S=1/1μm for chip to chip interconnection”(非專利文獻1)，揭示有為了提高以SAP (semi-Additive Process：半加成製程)法形成之Cu配線之可靠性，而設置以無電解鍍敷法形成於Cu配線之上表面及側面之金屬障壁膜之構造。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2003-234348號公報
[專利文獻2]日本特開2012-4210號公報
[專利文獻3]日本特開2000-306938號公報
[非專利文獻]
[非專利文獻1]T. Kanki et al., “Development of highly reliable Cu wiring of L/S=1/1μm for chip to chip interconnection” Interconnect Technology Conference, 2012 IEEE International, 4-6 June 2012
本申請案發明人所研究之具有再配線之半導體裝置(半導體積體電路裝置)具有半導體晶片、連接於半導體晶片之導線、及密封半導體晶片及導線之密封體。半導體晶片具有半導體元件、電性連接於半導體元件之以Cu作為主成分之再配線、及電性連接半導體元件與再配線之包含多層配線層之配線。再配線係連接於以多層配線層之最上層之配線層形成之配線之一部分即焊墊電極。以最上層之配線層形成之配線與再配線之間，覆蓋以最上層之配線層形成之配線之表面保護膜、與形成於表面保護膜上之第1有機保護膜被電性分離，但經由以露出焊墊電極之方式設置之表面保護膜與第1有機保護膜之開口，使再配線與焊墊電極電性連接。再配線之上表面與側面被第2有機保護膜覆蓋，但第2有機保護膜具有使形成於再配線之上表面之外部焊墊電極露出之開口，於該開口部與再配線連接。
於半導體晶片，形成有複數條再配線，再配線之最小線寬為12μm，鄰接之再配線之最小間隔為15μm。於再配線之下表面設置有包含用以形成再配線之金屬膜(例如Cr膜)之籽晶層，再配線之上表面及側面與第2有機保護膜相接。
本申請案發明人所研究之半導體裝置，為了謀求高耐壓、高可靠性，而實施被稱為HAST(Highly Accelerated temperature and humidity Stress Test：高加速溫度及濕度應力測試)試驗之於高溫高濕氣體環境中之動作試驗。根據本申請案發明人之研究，判明於HAST試驗中，於鄰接之再配線之間，自一再配線樹枝狀地析出Cu，產生鄰接之再配線間之耐壓劣化或短路，降低了半導體裝置之可靠性。且，亦了解Cu之樹枝狀之析出產生於表面保護膜與第1有機保護膜之界面或第1及第2有機保護膜之界面。
根據本申請案發明人之分析，覆蓋包含Cu之再配線之第1及第2有機保護膜係包含聚醯亞胺膜，由於含有水分或鹵素離子，故構成再配線之Cu之表面被氧化，其結果產生Cu離子(離子化之Cu)。已知於上述半導體裝置中，鄰接之再配線之最小間隔(15μm)雖然較大，但存在有被施加高壓電，於鄰接之再配線間造成高電場之區域，於該區域產生有Cu之樹枝狀析出。即，認為因Cu離子受高電場之影響而於表面保護膜與第1有機保護膜之界面或第1及第2有機保護膜之界面移動(擴散)，而產生鄰接之再配線間之耐壓劣化或短路，致使半導體裝置之可靠性下降。
本發明之目的在於提供一種可提高具有再配線之半導體裝置之可靠性之技術。
本發明之上述及其他目的與新穎之特徵，可由本說明書之記述及附加圖式而明瞭。
一實施形態之半導體裝置具有：焊墊電極，其形成於複數之配線層之最上層；保護膜，其於焊墊電極上具有開口；底層金屬膜，其形成於保護膜上；再配線，其形成於底層金屬膜上；及蓋金屬膜，其以覆蓋再配線之上表面及側面之方式形成。且，於再配線之外側之區域，於形成於再配線之側壁上之蓋金屬膜與保護膜之間，形成有與再配線不同材料之底層金屬膜、及與再配線不同材料之蓋金屬膜，於再配線之外側之區域，底層金屬膜與蓋金屬膜直接相接。
根據一實施形態，可提高具有再配線之半導體裝置之可靠性。
1A~1F‧‧‧半導體晶片
1P‧‧‧半導體基板
2N‧‧‧n型井
2P‧‧‧p型井
3‧‧‧元件分離槽
3a‧‧‧元件分離絕緣膜
4‧‧‧鈍化膜
5‧‧‧第1層Al配線
6‧‧‧鈍化膜
7‧‧‧第2層Al配線
8‧‧‧障壁金屬膜
9‧‧‧第3層Al配線
9a‧‧‧焊墊電極
10‧‧‧表面保護膜
10a‧‧‧焊墊開口
11‧‧‧底層絕緣膜
11a‧‧‧開口
12‧‧‧保護膜
12a‧‧‧開口
13‧‧‧再黏著物
15‧‧‧再配線
18‧‧‧外部焊墊電極
20‧‧‧導線
25D‧‧‧晶片焊墊部
25L‧‧‧引線
26‧‧‧密封體
27‧‧‧導線
30‧‧‧配線基板
31‧‧‧核心層
32‧‧‧焊接指
33‧‧‧焊盤
34‧‧‧通孔內配線
35‧‧‧阻焊劑
36‧‧‧凸塊電極
37‧‧‧導線
38‧‧‧密封體
39‧‧‧接著層
CM‧‧‧蓋金屬膜
CM1‧‧‧第1蓋障壁膜
CM2‧‧‧第2蓋障壁膜
CM3‧‧‧第3蓋障壁膜
GND‧‧‧電源
L‧‧‧配線寬度
nd‧‧‧汲極區域
ng‧‧‧閘極電極
ni‧‧‧閘極絕緣膜
ns‧‧‧源極區域
P1‧‧‧第1平面圖案
p1~p3‧‧‧插塞
P2‧‧‧第2平面圖案
pd‧‧‧汲極區域
pg‧‧‧閘極電極
pi‧‧‧閘極絕緣膜
PP‧‧‧突出部
PR1‧‧‧抗蝕遮罩
PR2‧‧‧抗蝕遮罩
ps‧‧‧源極區域
Qn‧‧‧n通道型MIS電晶體
Qp‧‧‧p通道型MIS電晶體
RM‧‧‧再配線
RM1‧‧‧籽晶膜
RM1a~RM1d‧‧‧籽晶膜
RM2‧‧‧鍍敷膜
RM2a~RM2d‧‧‧鍍敷膜
RMa~RMd‧‧‧再配線
RMS‧‧‧再配線
RMV‧‧‧再配線
S1~S2‧‧‧間隔
S3‧‧‧突出量
S3L‧‧‧突出量
S3R‧‧‧突出量
UM‧‧‧底層金屬膜
UM1‧‧‧第1底層障壁膜
UM1a‧‧‧第1底層障壁膜
UM2‧‧‧第2底層障壁膜
UM2a‧‧‧第2底層障壁膜
UM3‧‧‧第3底層障壁膜
UM3a‧‧‧第3底層障壁膜
UMa‧‧‧底層金屬膜
Vcc‧‧‧電源
X‧‧‧虛線
Y‧‧‧虛線
α‧‧‧偏移量
圖1係本發明之實施形態1之半導體裝置之電路方塊圖。
圖2係形成有本發明之實施形態1之半導體裝置之半導體晶片之整體俯視圖。
圖3係放大顯示圖2之一部分之俯視圖。
圖4係沿圖3之A-A線之剖視圖。
圖5係本實施形態1之半導體裝置之製造步驟中之剖視圖。
圖6係接續圖5之半導體裝置之製造步驟中之剖視圖。
圖7係接續圖6之半導體裝置之製造步驟中之剖視圖。
圖8係接續圖7之半導體裝置之製造步驟中之剖視圖。
圖9係接續圖8之半導體裝置之製造步驟中之剖視圖。
圖10係接續圖9之半導體裝置之製造步驟中之剖視圖。
圖11係接續圖10之半導體裝置之製造步驟中之剖視圖。
圖12係接續圖11之半導體裝置之製造步驟中之剖視圖。
圖13係接續圖12之半導體裝置之製造步驟中之剖視圖。
圖14係變化例1之半導體裝置之製造步驟中之剖視圖。
圖15係變化例2之半導體裝置之製造步驟中之剖視圖。
圖16係變化例3之半導體裝置之製造步驟中之剖視圖。
圖17係變化例4之半導體裝置之製造步驟中之剖視圖。
圖18係比較例之半導體裝置之製造步驟中之剖視圖。
圖19係接續圖18之比較例之半導體裝置之製造步驟中之剖視圖。
圖20係實施形態2之半導體裝置之製造步驟中之剖視圖。
圖21係接續圖20之半導體裝置之製造步驟中之剖視圖。
圖22係變化例5之半導體裝置之製造步驟中之剖視圖。
於以下之實施形態中為了方便起見而於必要時，分割成複數個部分或實施形態進行說明，但除了特別明示之情形外，該等並非彼此無關係者，存在一者為另一者之一部分或全部之變化例、應用例、詳細說明、補充說明等之關係。又，於以下之實施形態中，言及要件之數等(包含個數、數值、量、及範圍等)之情形，除了特別明示之情形及原理上明確限定於特定之數之情形等外，並非限定於該特定之數，而可為特定之數以上或以下。
再者，於以下實施形態中，其構成要件(亦包含要件步驟等)除了特別明示之情形及認為原理上明確必須之情形等外，並非必須者。同樣地，於以下實施形態中，言及構成要件等之形狀、位置關係等時，除了特別明示之情形及認為原理上明確並非如此之情形等外，包含實質上與該形狀等近似或類似者等。此點對上述數等(包含個數、數值、量、範圍等)亦相同。
以下，基於圖式對本發明之實施形態進行詳細說明。另，於用以說明實施形態之全部圖中，對具有相同功能之構件附註相同或關連之符號，並省略其重複之說明。又，於存在複數個類似之構件(部位)之情形時，有對總稱之符號追加記號而顯示個別或特定之部位之情 形。又，於以下實施形態中，除了特別必要時以外，原則上不重複同一或相同部分之說明。
又，於實施形態所使用之圖式中，即便為剖視圖亦有為了容易觀察圖式而省略陰影線之情形。又，即便為俯視圖，亦有為了容易觀察圖式而附註陰影線之情形。
又，於剖視圖及俯視圖中，各部位之大小並非與實際裝置對應者，為了使圖式易懂，而有相對較大地顯示特定部位之情形。又，於俯視圖與剖視圖對應之情形時，亦有改變各部位之大小而顯示之情形。
(實施形態1)
本實施形態1及以下之實施形態之半導體裝置(半導體積體電路裝置)係例如包含：複數個半導體元件；複數層之配線(多層配線)，其形成於複數個半導體元件之上部；及半導體晶片，其具有連接於複數層內之最上層配線之複數條再配線；且藉由上述多層配線及複數條再配線連接複數之半導體元件而構成。
<關於半導體裝置>
圖1係顯示半導體裝置之電路方塊圖。如圖1所示，半導體裝置具備例如形成於半導體晶片1A之裝置面之輸出入(I/O)電路、類比電路、CMIS-邏輯電路、功率MIS電路、及記憶體電路，而構成半導體裝置。
於構成半導體裝置之上述電路中，CMIS-邏輯電路以例如動作電壓為1~3V之CMIS電晶體構成，I/O電路及記憶體電路以例如動作電壓為1~3V及5~8V之CMIS電晶體構成。
動作電壓為1~3V之CMIS電晶體以具有第1閘極絕緣膜之第1之n通道型MISFET(Metal Insulator Semiconductor Field Effect Transistor：金屬絕緣半導體場效應電晶體)、與具有第1閘極絕緣膜之第1之p通道 型MISFET構成。又，動作電壓為5~8V之CMIS電晶體以具有第2閘極絕緣膜之第2之n通道型MISFET、與具有第2閘極絕緣膜之第2之p通道型MISFET構成。第2閘極絕緣膜之膜厚較第1閘極絕緣膜之膜厚更厚而構成。於以下說明中，將MISFET稱為MIS電晶體。
又，類比電路以例如動作電壓為5~8V之CMIS電晶體(或雙極電晶體)、電阻元件、及電容元件構成，功率MIS電路以例如動作電壓為5~8V之CMIS電晶體與動作電壓為20V~100V之高耐壓MIS電晶體(高耐壓元件)構成。
高耐壓MIS電晶體以例如具有第3閘極絕緣膜之第3之n通道型MISFET、或具有第3閘極絕緣膜之第3之p通道型MISFET、或兩者而構成。於閘極電極與汲極區域之間、或閘極電極與源極區域之間施加20V~100V之電壓時，第3閘極絕緣膜之膜厚以變得較第2閘極絕緣膜之膜厚更厚之方式構成。
圖2係顯示半導體晶片1A之一例之整體俯視圖，圖3係被圖2之虛線X包圍之區域之放大俯視圖，圖4係沿圖3之A-A線之剖視圖。
圖2係顯示形成於半導體晶片1A之裝置面上之再配線RM、RMV、RMS之佈局之一例。再配線RM、RMV、RMS與半導體晶片1A之複數層之配線(如圖4所示之第1層Al配線5、第2層Al配線7、第3層Al配線9)相比，其膜厚及配線寬皆較大，因而與複數層之配線相比，阻抗極低。再配線RM、RMV、RMS例如作為信號輸出入用之再配線RM、電源(Vcc、GND)供給用之再配線RMV及內部電路間之連接用之再配線RMS而使用。
如圖2所示，於半導體晶片1A之周邊部配置有構成半導體裝置之外部連接端子之複數條再配線RM。於構成半導體裝置之外部連接端子之再配線RM之各者之一端形成有外部焊墊電極18，另一端如圖3、4所示連接於形成於最上層之配線之焊墊電極9a。外部焊墊電極18並 未特別限定，係沿半導體晶片1A之各邊配置成一行。另，外部焊墊電極18當然可沿半導體晶片1A之各邊以鋸齒狀或成3行以上之行之方式配置。即，再配線RM係例如構成圖1之輸出入(I/O)電路之信號輸出入用之再配線。
又，如圖2所示之再配線RMV為電源(Vcc、GND)供給用之再配線。因於再配線RMV之一端形成外部焊墊電極18，另一端連接於形成於半導體晶片1A內之電源配線之焊墊電極9a，故可以低阻抗將自半導體晶片1A之外部供給之電源(Vcc、GND)電壓供給至半導體晶片1A內之複數條電源配線。
又，如圖2所示之再配線RMS係作為連接形成於半導體晶片1A之電路間或元件間之配線而使用。因此，於再配線RMS未形成外部焊墊電極18。再配線RMS之兩端連接於形成於配線之焊墊電極9a。
圖3係顯示鄰接之2條信號輸出入用之再配線RM之放大俯視圖。鄰接之2條再配線RM因具有彼此相等之平面形狀，故以位於紙面上部之再配線RM為例進行說明。再配線RM延伸於紙面之X方向，其一端電性連接於延伸於紙面之X方向之配線9之焊墊電極9a。於再配線RM之另一端，形成有外部焊墊電極18。再配線RM具有第1平面圖案P1，底層金屬膜UM及蓋金屬膜CM具有第2平面圖案P2。第1平面圖案P1與第2平面圖案P2為相似形狀，第2平面圖案P2具有放大第1平面圖案P1之形狀。於再配線RM之整周圍，配置有以底層金屬膜UM及蓋金屬膜CM構成之突出部PP。即，若第1平面圖案P1放大突出部PP之寬度S3則成為第2平面圖案P2。
又，再配線RM之最小配線寬度L例如為12μm，鄰接之再配線RM之最小配線間隔S1為15μm，鄰接之突出部PP間之最小間隔S2為10μm，突出部PP之突出量S3為2.5μm。
理想而言，於再配線RM之整周圍，突出部PP之突出量S3變得相 等，但亦可使第2平面圖案P2相對於第1平面圖案P1，例如於X方向偏移α。於相對於第1平面圖案P1，第2平面圖案P2於X方向偏移α之情形，第1平面圖案P1之右側之邊之突出量成為S3R=(S3+α)，左側之邊之突出量成為S3L=(S3-α)。
於本實施形態1中，充分確保突出量S3，且減少之側之突出量S3L=(S3-α)，較圖4所示之形成於再配線RM之側面上之蓋金屬膜CM之膜厚更大。
如圖4所示，於包含例如p型單結晶矽之半導體基板1P，形成有p型井2P、n型井2N及元件分離槽3，於元件分離槽3之內部，嵌入有包含例如氧化矽膜之元件分離絕緣膜3a。
於上述p型井2P內，形成有n通道型MIS電晶體(Qn)。n通道型MIS電晶體(Qn)具有形成於元件分離槽3所限定之活性區域且形成於p型井2P內之源極區域ns及汲極區域nd、及於p型井2P上介隔閘極絕緣膜ni而形成之閘極電極ng。又，於上述n型井2N內形成有p通道型MIS電晶體(Qp)，具有源極區域ps及汲極區域pd、及於n型井2N上介隔閘極絕緣膜pi而形成之閘極電極pg。
於上述n通道型MIS電晶體(Qn)及p通道型MIS電晶體(Qp)之上部，形成有連接半導體元件間之包含金屬膜之配線。連接半導體元件間之配線一般具有3層~10層左右之多層配線構造，於圖4中，作為多層配線之一例，顯示有以Al合金為主體之金屬膜所構成之3層之配線層(第1層Al配線5、第2層Al配線7、第3層Al配線9)。配線層係於將各配線層所形成之複數條配線總稱表示時使用。配線層之膜厚係第2層之配線層較第1層之配線層更厚，第3層之配線層較第2層之配線層更厚。
於n通道型MIS電晶體(Qn)及p通道型MIS電晶體(Qp)與第1層Al配線5之間、第1層Al配線5與第2層Al配線7之間、及第2層Al配線7與第3 層Al配線9之間，形成有將各自包含氧化矽膜等之層間絕緣膜4、6、8、與3層之配線間電性連接之插塞p1、p2、p3。
上述層間絕緣膜4以例如覆蓋半導體元件之方式，形成於半導體基板1P上，第1層Al配線5形成於該層間絕緣膜4上。第1層Al配線5經由例如形成於層間絕緣膜4之插塞p1而電性連接於半導體元件即n通道型MIS電晶體(Qn)之源極區域ns、汲極區域nd、閘極電極ng。又，第1層Al配線5係經由形成於層間絕緣膜4之插塞p1而電性連接於半導體元件即p通道型MIS電晶體(Qp)之源極區域ps、汲極區域pd、閘極電極pg。閘極電極ng、pg與第1層Al配線5之連接未予以圖示。
第2層Al配線7經由例如形成於層間絕緣膜6之插塞p2而電性連接於第1層Al配線5。第3層Al配線9經由例如形成於層間絕緣膜8之插塞p3而電性連接於第2層Al配線7。插塞p1、p2、p3係以金屬膜，例如W(鎢)膜構成。
另，藉由化學性機械研磨法(CMP法)以Cu為主體之金屬膜形成多層配線(3層配線)之情形，當然亦可藉由使配線與插塞一體形成之雙金屬鑲嵌法而形成。又，層間絕緣膜4、6、8包含氧化矽膜(SiO2)，當然亦可以包含碳之氧化矽膜(SiOC膜)、包含氮與碳之氧化矽膜(SiCON膜)、包含氟之氧化矽膜(SiOF膜)之單層膜或積層膜構成。
於多層配線之最上層之配線層即上述第3層Al配線9之上部，作為最終鈍化膜，形成有例如氧化矽膜、氮化矽膜等單層膜、或包含該等之2層膜之表面保護膜(保護膜、絕緣膜)10。且，露出於形成於該表面保護膜10之焊墊開口(開口)10a之底部之最上層之配線層即第3層Al配線9，係構成Al焊墊即焊墊電極(電極焊墊、第1電極焊墊)9a。
上述第3層Al配線9亦可例如構成一體形成於焊墊電極9a之配線、未連接於焊墊電極9a之配線等，而未限定於焊墊電極9a。未連接於焊墊電極9a之配線，係將半導體元件間或電路間電性連接，作為構成半 導體積體電路之配線而使用。
於上述表面保護膜10上，形成有於焊墊開口10a之上方具有開口11a之絕緣膜即底層絕緣膜(有機保護膜、絕緣膜)11。又，於底層絕緣膜11上，形成有通過底層絕緣膜11之開口11a、及表面保護膜10之焊墊開口10a而電性連接於焊墊電極9a之再配線RM。開口11a較焊墊開口10a大，且於焊墊開口10a之整週，限定焊墊開口10a之表面保護膜10之上表面(表面)自開口11a露出。再配線RM以完全填埋焊墊開口10a及開口11a之方式，形成於焊墊開口10a及開口11a之內部，進而延伸於底層絕緣膜11上。
於焊墊電極9a與再配線RM之間，介存有底層金屬膜UM。底層金屬膜UM接觸且電性連接於焊墊電極9a，且於表面保護膜10之焊墊開口10a及底層絕緣膜11之開口11a中，沿表面保護膜10之側面(側壁)及上表面、以及底層絕緣膜11之側面(側壁)形成，進而延伸於底層絕緣膜11之上表面。底層金屬膜UM具有上表面與下表面，上表面與再配線RM相接，下表面相接於焊墊電極9a、表面保護膜10及底層絕緣膜11。如後述，底層金屬膜UM以3層構造之底層障壁膜構成，自焊墊電極9a之側起包含第1底層障壁膜UM1、第2底層障壁膜UM2及第3底層障壁膜UM3。因此，底層金屬膜UM之上表面意指第3底層障壁膜UM3之上表面，下表面意指第1底層障壁膜UM1之下表面。第1底層障壁膜UM1、第2底層障壁膜UM2及第3底層障壁膜UM3例如依序以鈦(Ti)膜、氮化鈦(TiN)膜及鈦(Ti)膜構成，該等之膜厚依序設為10nm、50nm及10nm。該膜厚為底層絕緣膜11之上表面上之膜厚。
又，再配線RM具有上表面、下表面及側面，再配線RM之下表面與底層金屬膜UM之上表面相接。再配線RM為以銅(Cu)作為主成分之銅膜，且以籽晶膜RM1與鍍敷膜RM2之積層構造構成。因此，再配線RM之下表面意指籽晶膜RM1之下表面，上表面意指鍍敷膜RM2之上 表面。又，再配線RM之側面(側壁)意指籽晶膜RM1與鍍敷膜RM2之積層構造之側面(側壁)。籽晶膜RM1及鍍敷膜RM2之膜厚分別為250nm及6μm。此外，因第3層Al配線9之膜厚為400nm~600nm，故再配線RM係具有第3層Al配線9、換言之形成有焊墊電極9a之配線9之10倍以上之膜厚之低電阻之配線。即，再配線RM之膜厚大於形成有焊墊電極9a之配線9之膜厚。期望再配線RM之膜厚為形成有焊墊電極9a之配線9之膜厚之10倍以上。
相接於再配線RM之上表面及側面，以完全覆蓋再配線RM之方式形成有蓋金屬膜CM。蓋金屬膜CM覆蓋再配線RM之上表面之整體及側面之整體。蓋金屬膜CM完全覆蓋構成再配線RM之籽晶膜RM1之側面(側壁)及鍍敷膜RM2之側面(側壁)。蓋金屬膜CM具有上表面與下表面，下表面與再配線RM之上表面及再配線RM之側面相接，於再配線RM之外側之區域(未形成再配線RM之區域)中，與底層金屬膜UM之上表面直接相接。
底層金屬膜UM及蓋金屬膜CM自再配線RM之側面(嚴格來講為再配線RM之側面之下端部分)至再配線RM之外側之區域(未形成再配線RM)具有突出部PP，於突出部PP中，底層金屬膜UM之上表面與蓋金屬膜CM之下表面直接相接。又，突出部PP之突出量S3大於形成於再配線RM之側面(側壁)上之蓋金屬膜CM之膜厚，例如為2.5μm。即，於俯視時，突出部PP之前端即底層金屬膜UM及蓋金屬膜CM之端部位於較形成於再配線RM之側面(側壁)上之蓋金屬膜CM更於再配線RM之外側。又，突出部PP形成於俯視時之再配線RM之整周。突出量S3意指突出部PP之寬度，且為再配線RM之外側之區域中自再配線RM之端部至底層金屬膜UM或蓋金屬膜CM之端部之距離。
如後述，蓋金屬膜CM包含第1蓋障壁膜CM1及第2蓋障壁膜CM2之積層構造，第1蓋障壁膜CM1之下表面與再配線RM之上表面及側面 相接，進而，與底層金屬膜UM之上表面(正確而言，為第3底層障壁膜UM3之上表面)相接。蓋金屬膜CM之下表面意指第1蓋障壁膜CM1之下表面，上表面意指第2蓋障壁膜CM2之上表面。第1蓋障壁膜CM1包含鈦(Ti)膜，其膜厚為50nm，第2蓋障壁膜CM2包含鈀(Pd)膜，該等膜厚為175nm。該膜厚為再配線RM之上表面上之膜厚。
又，藉由將構成底層金屬膜UM之第3底層障壁膜UM3與構成蓋金屬膜CM之第1蓋障壁膜CM1設為包含相同材質之膜(具體而言為鈦(Ti)膜)，可強固突出部PP之底層金屬膜UM與蓋金屬膜CM之接著性，降低構成再配線RM之銅之移動(擴散)。
又，於突出部PP中，採用於底層金屬膜UM上積層蓋金屬膜CM之構造，因此再配線RM之外側之區域之突出部PP中底層金屬膜UM之膜厚與蓋金屬膜CM之膜厚之和變得較夾於再配線RM與底層絕緣膜11中之底層金屬膜UM之膜厚更厚。又，再配線RM之外側區域之突出部PP中之底層金屬膜UM之膜厚與第1蓋障壁膜CM1之膜厚之和變得較夾於再配線RM與底層絕緣膜11中之底層金屬膜UM之膜厚更厚。
以整體覆蓋再配線RM之方式形成有保護膜12。保護膜12具有使再配線RM之上表面(正確而言為該金屬膜CM之上表面、第2蓋金屬膜CM2之上表面)部分地露出之開口12a，再配線RM之露出部分成為外部焊墊電極18。
此處，底層絕緣膜11及保護膜12皆可使用有機膜，例如聚醯亞胺系樹脂或苯并環丁烯系樹脂、丙烯酸系樹脂、環氧系樹脂、矽系樹脂等。
另，底層金屬膜UM及蓋金屬膜CM係防止構成再配線RM之銅(Cu)膜成為銅離子而移動(擴散)至外部者，以與再配線RM不同之材料(不同材料)構成。又，於底層金屬膜UM及蓋金屬膜CM，未含銅(Cu)膜。
又，雖以信號輸出入用之再配線RM為例進行說明，但電源供給用之再配線RMV及連接電路間或元件間之再配線RMS亦為與再配線RM相同之構造。
<半導體裝置之特徵>
以下，說明本實施形態1之半導體裝置之主要特徵。
包含銅膜之再配線RM被覆蓋再配線RM之下表面且包含與再配線RM不同之材料之底層金屬膜UM、與覆蓋再配線RM之上表面及側面且包含與再配線RM不同之材料之蓋金屬膜CM完全包圍。且，於再配線RM之外側之區域中，底層金屬膜UM與蓋金屬膜CM具有突出部PP，於突出部PP中，底層金屬膜UM與蓋金屬膜CM直接接觸。藉由此種構造，即便於鄰接之再配線RM之間施加電場，亦可防止因構成再配線RM之銅移動(擴散)至再配線RM之外側之區域而產生之鄰接之再配線RM間之耐壓劣化或短路。又，因可防止構成底層絕緣膜11或保護膜12之聚醯亞胺膜所含之水分、鹵素離子等侵入包含銅膜之再配線RM中，故可防止銅膜之氧化，且可防止鄰接之再配線RM間之耐壓劣化或短路。
上述突出部之突出量較覆蓋再配線RM之側面之蓋金屬膜CM之膜厚更大。又，於因第2圖案相對於第1圖案之偏移而使突出量減少之情形時，亦因減少之突出量大於覆蓋再配線RM之側面之蓋金屬膜CM之膜厚，故於存在製造不均一之情形時，亦可防止鄰接之再配線RM間之耐壓劣化或短路。可防止構成再配線RM之銅膜之氧化。
又，將作為底層金屬膜UM之上表面之底層障壁膜與作為蓋金屬膜之下表面之蓋障壁膜設為包含相同材質之膜。因此，可提高突出部中底層金屬膜UM與蓋金屬膜CM之接著性，且可充分防止構成再配線RM之銅移動(擴散)至再配線RM之外側之區域，因而可防止鄰接之再配線RM間之耐壓劣化或短路、以及再配線RM之氧化。
又，因於俯視時，於再配線RM之整周範圍內形成有突出部PP，故可防止與於所有方向鄰接之再配線RM之間之耐壓劣化或短路以及再配線之氧化。
於俯視時，以具有較包含銅膜之再配線RM所具有之第1平面圖案P1更大之第2平面圖案P2之底層金屬膜UM與蓋金屬膜CM完全包入再配線RM，且於再配線RM之外側之區域中，底層金屬膜UM之上表面與蓋金屬膜CM之下表面直接接觸。藉由該構造，即便於鄰接之再配線RM間施加高電場，亦可防止再配線RM之氧化，且可防止鄰接之再配線RM間之耐壓劣化或短路。又，即便構成再配線RM之銅膜氧化產生銅離子，亦可防止銅離子移動(擴散)至再配線RM之外側。
又，於第1平面圖案P1之整周，因第2平面圖案P2較第1平面圖案P1更大，故可防止與於所有方向鄰接之再配線RM之間之耐壓劣化或短路。
<半導體裝置之製造方法>
其次，對本實施形態1之半導體裝置之製造方法進行說明，但以本實施形態1之特徵的再配線之製造方法為中心進行說明。再配線之製造方法與圖4所示之剖面對應。
圖5~圖13係本實施形態1之半導體裝置之製造步驟中之剖視圖。
圖5係顯示準備形成有複數之配線層與焊墊電極之半導體基板之步驟。於半導體基板1P上形成有p通道型MIS電晶體(Qp)及n通道型MIS電晶體(Qn)後，形成包含複數之配線層之配線。具體而言，如圖4所說明，形成有3層之配線層(第1層Al配線5、第2層Al配線7、第3層Al配線9)。且，於第3層Al配線9之上部，形成有表面保護膜10，表面保護膜10具有焊墊開口10a，最上層之配線層即第3層Al配線9之自焊墊開口10a露出之部分作為焊墊電極9a。圖5所示之剖面構造如圖4所說明。
圖6顯示底層絕緣膜11、底層金屬膜UM及籽晶膜RM1之形成步驟。首先，於表面保護膜10上形成底層絕緣膜11，作為底層絕緣膜11係使用感光性聚醯亞胺樹脂。於表面保護膜10上塗佈感光性聚醯亞胺並曝光，使焊墊開口10a及焊墊電極9a露出後，進行固化而硬化。即，形成具有較焊墊開口10a及焊墊電極9a更大之開口11a之底層絕緣膜11。
其次，形成(堆積)經由開口11a、焊墊開口10a而電性連接於焊墊電極9a之底層金屬膜及籽晶膜RM1。構成底層金屬膜UM之第1底層障壁膜UM1、第2底層障壁膜UM2及第3底層障壁膜UM3依序以鈦(Ti)膜為5~50nm，氮化鈦(TiN)膜為10~100nm，鈦(Ti)膜為5~50nm之膜厚形成較為適當。此處，作為一例，將鈦(Ti)膜設為10nm，氮化鈦(TiN)膜設為50nm，且鈦(Ti)膜設為10nm。該等第1底層障壁膜UM1、第2底層障壁膜UM2及第3底層障壁膜UM3例如藉由濺鍍法形成。其次，使用濺鍍法而於第3底層障壁膜UM3上形成包含銅(Cu)膜之籽晶膜RM1。籽晶膜RM1設為250nm左右之膜厚。
圖7顯示再配線RM之形成步驟之鍍敷步驟。於籽晶膜RM1上，形成使再配線RM之形成區域露出且覆蓋未形成再配線RM之區域的抗蝕遮罩(抗蝕圖案)PR1。即，抗蝕遮罩PR1成為第1平面圖案P1之反轉圖案，具有與第1平面圖案P1對應之開口。其次，將底層金屬膜UM及籽晶膜RM1設為籽晶層，藉由電解(電性)鍍敷法，於自抗蝕遮罩PR1露出之區域之籽晶膜RM1上選擇性形成包含銅(Cu)膜之鍍敷膜RM2。鍍敷膜RM2之膜厚例如約為6μm。鍍敷膜RM2之膜厚亦可設於2μm~10μm之範圍內，鍍敷膜RM2之膜厚若太薄，則因再配線RM之電阻變高，故一般需要能取得滿足裝置之要求之電阻值之膜厚，即某程度之膜厚。但，若太厚則晶圓之翹曲變大，於其後之微影法或加工裝置產生搬送誤差，使加工變難，產生製造成本增加或生產性降低之弊端。 另，例如，底層金屬膜UM等於圖案化之前後附註相同之符號。於該步驟，形成具有第1平面圖案P1之鍍敷膜RM2。
圖8顯示再配線RM之形成步驟即籽晶膜RM1之去除(加工)步驟。於鍍敷膜RM2形成後，去除抗蝕遮罩PR1。其次，藉由去除自鍍敷膜RM2露出之區域之籽晶膜RM1，而於鍍敷膜RM2下，殘留具有與鍍敷膜RM2相等之平面圖案之圖案化籽晶膜RM1。於該步驟中，形成具有第1平面圖案P1且包含籽晶膜RM1與鍍敷膜RM2之積層構造之再配線RM。
此時，重要的是使自鍍敷膜RM2露出之區域(換言之，為再配線RM之外側之區域)之底層金屬膜UM不被去除而殘留。但，重要的是底層金屬膜UM殘留於自鍍敷膜RM2露出之區域，例如，亦可將自鍍敷膜RM2露出之區域之底層金屬膜UM蝕刻去除一半左右之膜厚。即，亦可將自鍍敷膜RM2露出之區域之底層金屬膜UM之膜厚設為被鍍敷膜RM2覆蓋之區域之底層金屬膜UM之膜厚之一半左右。藉由使自鍍敷膜RM2露出之區域之底層金屬膜UM之膜厚較薄，可防止自底層絕緣膜11剝離底層金屬膜UM。藉由降低底層金屬膜UM之膜厚，而獲得可降低底層金屬膜UM具有之應力且減低自底層絕緣膜11剝離之效果。此處，蝕刻係將鍍敷膜RM2或籽晶膜RM1作為硬遮罩，進行包含氯系氣體之乾蝕刻。
圖9顯示形成蓋金屬膜CM之步驟之一部分。以完全覆蓋再配線RM之上表面及側面之方式形成(堆積)蓋金屬膜CM。圖案化之前之蓋金屬膜CM稱為蓋金屬材料膜。蓋金屬膜CM以複數層之蓋障壁膜構成。為了形成蓋金屬膜CM，而依序形成第1蓋障壁膜(第1蓋金屬材料膜)CM1、第2蓋障壁膜(第2蓋金屬材料膜)CM2及第3蓋障壁膜(第3蓋金屬材料膜)CM3。另，於本實施形態1中，第3蓋障壁膜CM3亦作為蓋金屬膜CM之一部分處理。第1蓋障壁膜CM1、第2蓋障壁膜CM2及 第3蓋障壁膜CM3以鈦(Ti)膜為10~200nm，鈀(Pd)膜為10~200nm，鈦(Ti)膜為10~200nm之膜厚形成較為適當。此處，作為一例，將下層之鈦(Ti)膜設為10nm，鈀(Pd)膜設為50nm，上層之鈦(Ti)膜設為175nm。第1蓋障壁膜CM1、第2蓋障壁膜CM2及第3蓋障壁膜CM3為了完全覆蓋再配線RM之側面，以使用CVD法等之保形成膜方法較佳，但並未限定於此。
此處，藉由將與第3底層障壁膜UM3相接之第1蓋障壁膜CM1設為與第3底層障壁膜UM3之膜相同材質之膜，可使突出部PP中第3底層障壁膜UM3與第1蓋障壁膜CM1之接著性提高。換言之，藉由使作為積層構造之底層金屬膜UM之上表面之膜、與作為積層構造之蓋金屬膜CM之下表面之膜之材質相等，可提高突出部PP中之底層金屬膜UM與蓋金屬膜CM之接著性，且可防止構成再配線RM之銅離子朝外部移動(擴散)，並可防止自底層絕緣膜11或保護膜12之水分等之侵入。
又，亦可於第1蓋障壁膜CM1之成膜前，對再配線RM及底層金屬膜UM(尤其，第3底層障壁膜UM3)之表面實施氫電漿處理，去除再配線RM之上表面及側面以及底層金屬膜UM之上表面之氧化膜而清淨化，使底層金屬膜UM與蓋金屬膜CM之接著性提高。
其次，如圖9所示，於第3蓋障壁膜CM3上形成抗蝕遮罩PR2。抗蝕遮罩PR2成為與第2平面圖案P2對應，於俯視時覆蓋再配線RM及再配線RM周圍之突出部PP且露出其以外之圖案。
圖10接續圖9，顯示形成蓋金屬膜CM之步驟之一部分之步驟。以乾蝕刻或濕蝕刻去除自抗蝕遮罩PR2露出之區域之第3蓋障壁膜CM3，形成具有第2平面圖案P2之第3蓋障壁膜CM3。包含鈦(Ti)膜之第3蓋障壁膜CM3使用氨水過氧化氫溶液進行濕蝕刻。即，使用抗蝕遮罩PR2，使第3蓋障壁膜CM3圖案化。
其次，去除抗蝕遮罩PR2。接著，將圖案化之包含鈦(Ti)膜之第3蓋障壁膜CM3作為硬遮罩，蝕刻第2蓋障壁膜CM2，形成具有第2平面圖案P2之第2蓋障壁膜CM2。包含鈀(Pd)膜之第2蓋障壁膜CM2係使用碘-碘化鉀溶液進行濕蝕刻，但亦可以乾蝕刻進行蝕刻。即，將第3蓋障壁膜CM3作為遮罩，使第2蓋障壁膜CM2圖案化(蝕刻)。
即便對第3蓋障壁膜CM3及第2蓋障壁膜CM2實施濕蝕刻，亦因於再配線RM之外側之區域即突出部PP存在底層金屬膜UM，且於突出部PP中之蓋金屬膜CM與底層金屬膜UM直接相接，故蝕刻液未滲入再配線RM。
圖11接續圖10，顯示形成蓋金屬膜CM之步驟之一部分及底層金屬膜UM之加工步驟。蝕刻去除自第3蓋障壁膜CM3及第2蓋障壁膜CM2露出之區域之第1蓋障壁膜CM1及底層金屬膜UM，使底層絕緣膜11之上表面露出。因以鈦(Ti)膜及氮化鈦(TiN)膜形成第1蓋障壁膜CM1及底層金屬膜UM，故例如可藉由使用氨水過氧化氫溶液之濕蝕刻，去除第1蓋障壁膜CM1及底層金屬膜UM，形成具有第2平面圖案P2之第1蓋障壁膜CM1及底層金屬膜UM。此時，以鈦(Ti)膜形成之第3蓋障壁膜CM3亦被同時去除，露出第2蓋障壁膜CM2之上表面。藉由以與第1蓋障壁膜CM1及底層金屬膜UM之蝕刻時間大致相等之方式設定第3蓋障壁膜CM3之膜厚，可降低與第2蓋障壁膜CM2之端部相對之第1蓋障壁膜CM1及底層金屬膜UM之側蝕刻。
經過上述步驟，使覆蓋鄰接之再配線RM之上表面及側面之蓋金屬膜CM及連接於下表面之底層金屬膜UM分離，形成具有相等之第2平面圖案P2之蓋金屬膜CM與底層金屬膜UM。此處，「相等」亦包含有因上述之側蝕刻而具有尺寸差之情形。
即便對第3蓋障壁膜CM3、第1蓋障壁膜CM1及底層金屬膜UM實施濕蝕刻，亦因於再配線RM之外側之區域即突出部PP存在底層金屬 膜UM，於突出部PP中，蓋金屬膜CM與底層金屬膜UM直接相接，故蝕刻液未滲入再配線RM。
圖12顯示有保護膜12之形成步驟。形成覆蓋再配線RM之上表面及側面，且具有使設置於再配線RM之上表面之外部焊墊電極18露出之開口12a之保護膜12。保護膜12較再配線RM之膜厚更厚，於鄰接之再配線RM之間之區域，與底層絕緣膜11之上表面相接。作為保護膜12，使用例如感光性聚醯亞胺樹脂。於再配線RM上塗佈感光性聚醯亞胺並曝光，形成使外部焊墊電極18露出之開口12a後，進行固化使其硬化。
圖13係顯示半導體晶片1A之安裝步驟。於上述步驟後，於晶片焊墊部25D上搭載半導體晶片1A，且以導線27連接再配線RM與引線25L後，以密封體(密封樹脂)26密封引線25L之一部分(內引線部)、晶片焊墊部25D、半導體晶片1A及導線27，完成本實施形態1之半導體裝置(半導體積體電路裝置)。
如圖13所示，具有複數條再配線RM之半導體晶片1A搭載於晶片焊墊部25D，以導線27電性連接於複數條引線25L。引線25L之一部分(內引線部)、晶片焊墊部25D、半導體晶片1A及導線27以例如熱硬化性環氧樹脂等密封體(密封樹脂)26予以密封。又，於密封體26中，除環氧樹脂外亦含有二氧化矽(SiO2)等填料。引線25具有自密封體26所覆蓋之內引線部延伸至密封體26之外側之外引線部。
導線27之一端連接於如圖4或圖12所示之形成於半導體晶片1A之再配線RM之上表面之外部焊墊電極18，另一端連接於引線25L之內引線部。晶片焊墊部25D及複數條引線25L例如由銅(Cu)或42合金(鐵鎳合金)所構成，導線27由銅(Cu)所構成。
於外部焊墊電極18之表面露出包含鈀(Pd)膜之第2蓋障壁膜CM2，包含銅之導線27與包含鈀(Pd)膜之第2蓋障壁膜CM2焊接連 接，因而可進行穩定且具有足夠焊接強度之接合，可形成剪切強度高之高可靠性之焊接。
另，作為導線27，亦可使用於表面被覆鈀(Pd)之銅導線(包覆Pd之Cu導線)、金導線(Au導線)。
作為第1蓋障壁膜CM1係使用鈦(Ti)膜，但亦可為以Ni、Mo、W、Co、Ru、Ta等為主成分之合金或該等金屬之積層膜。又，作為第3底層障壁膜UM3係使用鈦(Ti)膜，但亦可為Ni、Mo、W、Co、Ru、Ta等之金屬或其氮化物、碳化物等、以該等金屬為主成分之合金或該等金屬之積層膜。
<半導體裝置之製造方法之特徵>
以下，說明本實施形態1之半導體裝置之製造方法之主要特徵。
如使用圖10及圖11所說明，於第2蓋障壁膜CM2之蝕刻步驟、以及第1蓋障壁膜CM1及第3蓋障壁膜CM3之蝕刻步驟中，於再配線RM之外側之區域即突出部PP，底層金屬膜UM自再配線RM下連續而延伸。又，於形成於再配線RM之側面(側壁)上之蓋金屬膜CM與底層絕緣膜11之間存在底層金屬膜UM。因此，可於上述之兩個蝕刻步驟中，防止形成再配線RM之銅(Cu)膜剝離之不良產生。其次，說明其效果。
圖18與圖19係本實施形態1之比較例之半導體裝置之製造步驟中之剖視圖。
圖18係顯示接續使用圖8說明之籽晶膜RM1之去除步驟，而去除自鍍敷膜RM2露出之區域之底層金屬膜UM之狀態。與上述本實施形態1之製造方法不同，為了於去除籽晶膜RM1後，完全去除自鍍敷膜RM2或籽晶膜RM1露出之區域之底層金屬膜UM，必須於底層金屬膜UM之蝕刻步驟中進行過度蝕刻。即，如圖18所示，發生底層金屬膜UM之端部自再配線RM之端部後退之側蝕刻，而成為再配線RM自底 層金屬膜UM之端部檐狀伸出之構造。
其次，根據本申請案發明人之研究判明，如圖19所示之蓋金屬膜CM堆積於再配線RM之上表面及側面上，但於圖19之虛線Y所包圍之部分中，產生被稱為「斷開」之蓋金屬膜CM之不連續部分。又，判明該斷開係因上述之底層金屬膜UM之側蝕刻而產生，進而於蓋金屬膜CM之蝕刻步驟中，蝕刻液自斷開部滲入再配線RM或再配線RM下之底層金屬膜UM，使再配線RM之一部分剝離。
於比較例中，於去除籽晶膜RM1後，連續地完全去除自鍍敷膜RM2露出之區域之底層金屬膜UM。然而，於本實施形態1中，去除再配線RM外側之區域之蓋金屬膜CM之階段之前，底層金屬膜UM仍殘留，由於接續蓋金屬膜CM之去除(亦可為同一步驟)而去除再配線RM之外側區域之底層金屬膜UM，故可防止上述之斷開，且可防止再配線RM之剝離。
又，於外部焊墊電極18之表面露出包含鈀(Pd)膜之第2蓋障壁膜CM2，包含銅之導線27焊接連接於包含鈀(Pd)膜之第2蓋障壁膜CM2，因而可進行穩定且具有足夠焊接強度之接合。
<變化例1>
圖14係本實施形態1之變化例1的半導體裝置之製造步驟中之剖視圖。
於半導體晶片1B之製造方法中，於使用圖8說明之籽晶膜RM1之去除步驟、與使用圖9說明之蓋金屬膜CM之形成步驟之間，追加將再配線RM之側面(側壁)設為正錐之步驟。具體而言，藉由對再配線RM實施氬(Ar)濺鍍蝕刻，可獲得於剖面視時側面成正錐之梯形形狀之再配線RMa。梯形形狀係再配線RMa之下表面較上表面更廣之形狀，或亦可說是於剖面視時，下表面之寬較上表面之寬更大之形狀。又，再配線RMa為籽晶膜RM1a與鍍敷膜RM2a之積層構造，籽晶膜RM1a與 鍍敷膜RM2a之側面成連續之正錐。
於以使用圖7說明之電解鍍敷法形成鍍敷膜RM2之情形，因抗蝕遮罩PR1之側面成正錐，故鍍敷膜RM2之側面成倒錐，鍍敷膜RM2之剖面視之形狀為倒梯形形狀。於側面為倒錐之情形時，以覆蓋再配線RM之側面之方式形成之蓋金屬膜CM之被覆性降低，會成為帶有不連續部或針孔之蓋金屬膜CM。因此，根據本申請案發明人之研究判明，於蓋金屬膜CM之濕蝕刻步驟中蝕刻液滲入再配線RM，產生再配線RM之側面被蝕刻(異常蝕刻)之現象。
藉由將再配線RM之側面設為正錐，可防止蓋金屬膜CM之不連續部或針孔之產生，且可防止再配線RM之異常蝕刻。
於上述步驟後，繼續實施形態1之蓋金屬膜CM之形成步驟。
<變化例2>
圖15係本實施形態1之變化例2之半導體裝置之製造步驟中之剖視圖。
於半導體晶片1C之製造方法中，於使用圖8說明之籽晶膜RM1之去除步驟、與使用圖9說明之蓋金屬膜CM之形成步驟之間，追加使再配線RM之肩部或側面整體變圓之步驟。具體而言，藉由對再配線RM實施回焊(熱處理)，可成為肩部變圓之再配線RMb。例如，藉由氫(H2)電漿處理或於氫(H2)氣體環境中以300℃~450℃左右之溫度進行退火將再配線RM之銅膜之表面之氧化膜還原後，以300℃~450℃退火而對銅膜進行回焊。又，再配線RMb成為籽晶膜RM1b與鍍敷膜RM2b之積層構造。
藉由使再配線RM之肩部變圓，側面變得圓滑，可提高蓋金屬膜CM之被覆性，且防止因蓋金屬膜CM之不連續部或針孔引起之再配線RM之異常蝕刻。
於上述步驟後，繼續實施形態1之蓋金屬膜CM之形成步驟。
<變化例3>
圖16係本實施形態1之變化例3之半導體裝置之製造步驟中之剖視圖。
圖16係顯示圖4所示之半導體晶片1A之變化例之半導體晶片1D，與半導體晶片1A不同處在於，於表面保護膜10之上未介存底層絕緣膜11而配置有再配線RM。底層金屬膜UM接觸且電性連接於焊墊電極9a，於表面保護膜10之焊墊開口10a中，於表面保護膜10之側壁及上表面延伸。底層金屬膜UM之下表面與表面保護膜10之上表面相接。相接於再配線RM之下表面之底層金屬膜UM及蓋金屬膜CM與實施形態1相同。又，其他構成、製造方法亦與實施形態1相同。
藉由成為以底層金屬膜UM完全被覆再配線RM之下表面，且以蓋金屬膜CM完全被覆上表面及側面，並於突出部PP使底層金屬膜UM與蓋金屬膜CM直接接觸之構造，可防止構成再配線RM之銅變為銅離子而朝外部移動(擴散)。又，可防止因保護膜12或密封體26所含之水分或鹵素離子等使構成再配線RM之銅膜被氧化。即，因可提高鄰接之再配線RM間之電性可靠性，故可省略圖4所示之底層絕緣膜11。
因於再配線RM及表面保護膜上，設置有包含有機膜之保護膜12，故如圖13所示，以包含二氧化矽之密封體26密封半導體晶片1D，亦可防止因密封體26與表面保護膜10接觸而引起之表面保護間膜10之裂痕。
又，如上所述，因可提高鄰接之再配線RM間之電性可靠性，不僅可省略底層絕緣膜11，亦可省略保護膜12。即便於密封體26中包含水分或鹵素離子，亦可藉由成為上述構造，而防止水分或鹵素離子侵入再配線RM中。
<變化例4>
圖17係本實施形態1之變化例4之半導體裝置之製造步驟中之剖視圖。
圖17係圖13所說明之安裝步驟之變化例。於將半導體晶片1A介隔接著層39搭載於配線基板30上，且以導線37連接再配線RM與焊接指(bonding finger)32後，以密封體(密封樹脂)38密封配線基板30之上表面側、半導體晶片1A及導線37，完成變化例4之半導體裝置(半導體積體電路裝置)。
如圖17所示，配線基板30於包含絕緣層之核心層31之上表面具有包含導體層之複數個焊接指32，且於下表面具有包含導體層之複數個焊盤33。複數個焊接指32間及複數個焊盤33間藉由包含絕緣層之阻焊劑35而電性絕緣。再者，焊接指32與焊盤33係經由形成於核心層31之包含導體層之通孔內配線34而電性連接，於焊盤33連接有包含焊料之凸塊電極36。再者，密封體38包含熱硬化性環氧樹脂等，且含有二氧化矽(SiO2)等之填料。
導線37之一端連接於如圖4或圖16所示之形成於半導體晶片1A之再配線RM之上表面之外部焊墊電極18，另一端連接於焊接指32。導線27為銅(Cu)導線，亦可使用於表面被覆鈀(Pd)之銅導線(包覆Pd之Cu導線)、金導線(Au導線)。
又，對外部焊墊電極18與焊接指32間以導線電性連接之例進行說明，亦可於再配線RM之上表面之外部焊墊電極18形成焊料球，且以焊料球電性連接外部焊墊電極18與焊接指針32之間。於該情形時，亦可使半導體晶片1A之形成有再配線RM之側與配線基板30之上表面側對向，且以焊料球連接外部焊墊電極18與焊接指32之間。
另，亦可取代半導體晶片1A，作成半導體晶片1B~1F。
(實施形態2)
實施形態2與實施形態1之半導體裝置之製造方法之變化例對 應。
圖20及圖21係實施形態2之半導體裝置之製造步驟中之剖視圖。為了與實施形態1之半導體裝置區分，而以半導體晶片1E表示實施形態2之半導體裝置。對與實施形態1之製造方法共通之部分附註相同之符號。
接續使用實施形態1之圖8進行說明之籽晶膜RM1之去除步驟，而去除自籽晶膜RM1露出之區域之底層金屬膜UM。與實施形態1之製造方法不同，為了於去除籽晶膜RM1後，完全去除自籽晶膜RM1露出之區域之底層金屬膜UM，必須於底層金屬膜UM之蝕刻步驟中進行過度蝕刻。即，如圖20所示，產生底層金屬膜UMa之端部自再配線RM之端部後退之側蝕刻，而成為再配線RM自底層金屬膜UMa之端部檐狀伸出之構造。即，於再配線RM產生伸出部，且於再配線RM與底層絕緣膜11之間產生空間(狹縫、間隙)。再配線RM為籽晶膜RM1與鍍敷膜RM2之積層構造，底層金屬膜UMa為第1底層障壁膜UM1a、第2底層障壁膜UM2a、及第3底層障壁膜UM3a之積層構造。
其次，對再配線RM進行蝕刻，刮削再配線RM直至再配線RM之側面與底層金屬膜UMa之側面一致為止、或較底層金屬膜UMa之側面更成為再配線RM之內部側為止。即，以蝕刻去除上述伸出部。如此，如圖21所示，形成具有與底層金屬膜UMa之側面一致之側面之再配線RMc。再配線RMc為籽晶膜RM1c與鍍敷膜RM2c之積層構造。又，如上所述，更好再配線RMc之側面與底層金屬膜UMa之側面相比，成為再配線RMc之內部側。
另，對於上述之底層金屬膜UM之濕蝕刻係使用例如氨水過氧化氫溶液。且，對於再配線RM之蝕刻可為濕蝕刻或乾蝕刻之任一者。
雖於上述蝕刻步驟後，實施實施形態1之蓋金屬膜CM之形成步驟以後之步驟並完成具有半導體晶片1E之半導體裝置，但因已去除上述 伸出部，故可防止因蓋金屬膜CM之斷開而引起之再配線RMc之剝離。且，因可為蓋金屬膜CM之下表面與底層金屬膜UM之側面或上表面接觸之構造，故可防止構成再配線RMc之銅膜之氧化或銅離子之移動(擴散)。
<變化例5>
變化例5係與實施形態2之半導體裝置之製造方法之變化例對應。
圖22係實施形態2之變化例5之半導體裝置之製造步驟中之剖視圖。為了與實施形態2之半導體裝置區分，以半導體晶片1F表示變化例5之半導體裝置。對與實施形態1或2之製造方法共通之部分附註相同之符號。
於實施形態2中，使用圖20說明之底層金屬膜UM之蝕刻步驟後，為了填埋再配線RM之伸出部之下之空間而對再配線RM實施濺鍍蝕刻。藉由對圖20所示之再配線RM實施氬(Ar)濺鍍蝕刻，可如圖22所示，獲得於剖面視時，側面成正錐之梯形形狀之再配線RMd。再者，於氬濺鍍蝕刻之步驟中，可以再黏著物(再附著物)13埋於再配線RMc之伸出部與底層絕緣膜11之間。再配線RMd為籽晶膜RM1d與鍍敷膜RM2d之積層構造。
於上述濺鍍蝕刻步驟後，實施實施形態1之蓋金屬膜CM之形成步驟以後之步驟並完成具有半導體晶片1F之半導體裝置之上述空間被填埋，因而可防止蓋金屬膜CM之斷開，且可防止再配線RMd之剝離。
以上，雖基於實施形態而具體說明由本發明人完成之發明，但本發明並未限定於上述實施形態，在未脫離其主旨之範圍內當然可進行各種變更。
例如，於實施形態2中，亦可取代蝕刻去除伸出部而藉由實施變化例2之回焊，消除再配線RM之伸出部與底層絕緣膜11之間之空間。 又，亦可於實施形態2或變化例5之半導體晶片1E或1F，應用變化例4之安裝步驟。
其他，於下文中記述上述實施形態所記述之內容之一部分。
[附記1]
一種半導體裝置之製造方法，其具有：(a)於半導體基板之主表面上形成焊墊電極之步驟；(b)於上述焊墊電極上形成具有開口之第1絕緣膜之步驟；(c)於上述第1絕緣膜上形成經由上述開口而電性連接於上述焊墊電極之底層金屬膜之步驟；(d)於上述底層金屬膜上形成經由上述底層金屬膜而電性連接於上述焊墊電極之再配線之步驟；(e)形成覆蓋上述再配線之上表面及側面之蓋金屬膜之步驟；且上述步驟(d)包含：(d-1)於上述底層金屬膜上，形成介隔上述底層金屬膜而電性連接於上述焊墊電極之上述再配線之步驟；(d-2)完全蝕刻自上述再配線露出之區域之上述底層金屬膜之步驟；(d-3)其後，濕蝕刻上述再配線使之後退之步驟；上述步驟(e)包含：(e-1)於上述半導體基板之主表面之整面上形成蓋障壁膜之步驟；(e-2)藉由使上述蓋障壁膜圖案化，而形成上述蓋金屬膜之步驟。
[附記2]
如上述附記1之半導體裝置之製造方法，其中上述再配線包含Cu膜，上述焊墊電極包含Al膜。
[附記3]
如上述附記1之半導體裝置之製造方法，其中上述再配線之膜厚較上述焊墊電極之膜厚更厚，上述焊墊電極於複數之配線層中最厚。
[附記4]
一種半導體裝置，其具有：半導體基板；複數之配線層，其形成於上述半導體基板上；焊墊電極，其形成於上述複數之配線層之最上層；絕緣膜，其於上述焊墊電極上具有開口；底層金屬膜，其形成於上述絕緣膜上，具有第1下表面與第1上表面；再配線，其形成於上述底層金屬膜之上述第1上表面，具有第2下表面與第2上表面、及側面；蓋金屬膜，其以覆蓋上述再配線之上述第2上表面及上述側面之方式形成，具有第3下表面與第3上表面；上述再配線具有第1平面圖案；上述底層金屬膜及上述蓋金屬膜具有較上述第1平面圖案更大之第2平面圖案；於上述再配線之外側，上述底層金屬膜之上述第1上表面與上述蓋金屬膜之上述第3下表面相接。
[附記5]
如上述附記4之半導體裝置，其中於上述第1平面圖案之整周圍，上述第2平面圖案較上述第1平面圖案大；於上述再配線之外側，上述底層金屬膜之上述第1上表面與上述蓋金屬膜之上述第3下表面相接。
1A‧‧‧半導體晶片
1P‧‧‧半導體基板
2N‧‧‧n型井
2P‧‧‧p型井
3‧‧‧元件分離槽
3a‧‧‧元件分離絕緣膜
4‧‧‧鈍化膜
5‧‧‧第1層Al配線
6‧‧‧鈍化膜
7‧‧‧第2層Al配線
8‧‧‧障壁金屬膜
9‧‧‧第3層Al配線
9a‧‧‧焊墊電極
10‧‧‧表面保護膜
10a‧‧‧焊墊開口
11‧‧‧底層絕緣膜
11a‧‧‧開口
12‧‧‧保護膜
12a‧‧‧開口
18‧‧‧外部焊墊電極
CM‧‧‧蓋金屬膜
nd‧‧‧汲極區域
ng‧‧‧閘極電極
ni‧‧‧閘極絕緣膜
ns‧‧‧源極區域
P1‧‧‧第1平面圖案
p1~p3‧‧‧插塞
P2‧‧‧第2平面圖案
pd‧‧‧汲極區域
pg‧‧‧閘極電極
pi‧‧‧閘極絕緣膜
PP‧‧‧突出部
ps‧‧‧源極區域
Qn‧‧‧n通道型MIS電晶體
Qp‧‧‧p通道型MIS電晶體
RM‧‧‧再配線
RM1‧‧‧籽晶膜
RM2‧‧‧鍍敷膜
UM‧‧‧底層金屬膜

Claims (19)

  1. 一種半導體裝置，其包含：半導體基板；複數之配線層，其形成於上述半導體基板上；焊墊電極，其形成於上述複數之配線層之最上層；絕緣膜，其於上述焊墊電極上具有開口；底層金屬膜，其形成於上述絕緣膜上；再配線，其形成於上述底層金屬膜上；及蓋金屬膜，其以覆蓋上述再配線之上表面及側面之方式形成；且於上述再配線之外側之區域，於形成於上述再配線之側壁上之上述蓋金屬膜與上述絕緣膜之間，形成有上述底層金屬膜；上述再配線與上述底層金屬膜係以不同材料形成；上述再配線與上述蓋金屬膜係以不同材料形成；於上述再配線之外側之區域中，上述底層金屬膜與上述蓋金屬膜直接相接。
  2. 如請求項1之半導體裝置，其中存在於上述再配線外側之區域之上述底層金屬膜之膜厚、與上述蓋金屬膜之膜厚之和，較上述再配線之下之上述底層金屬膜之膜厚更厚。
  3. 如請求項1之半導體裝置，其中上述蓋金屬膜以包含第1蓋障壁膜、第2蓋障壁膜之積層膜形成；上述第1蓋障壁膜為Ti膜；上述第2蓋障壁膜為Pd膜；上述底層金屬膜為包含Ti膜及TiN膜之積層膜。
  4. 如請求項1之半導體裝置，其中上述再配線以Cu為主成分而構 成；上述焊墊電極以Al為主成分而構成；上述再配線之膜厚較上述焊墊電極之膜厚更厚。
  5. 如請求項3之半導體裝置，其中於形成於上述再配線上之上述第2蓋金屬膜上，包含銅導線。
  6. 一種半導體裝置之製造方法，其包含：(a)準備包含複數之配線層、及形成於上述複數之配線層之最上層之焊墊電極之半導體基板之步驟；(b)於上述焊墊電極上形成具有第1開口之第1絕緣膜之步驟；(c)於上述第1絕緣膜上，形成經由上述開口而電性連接於上述焊墊電極之底層金屬膜之步驟；(d)於上述底層金屬膜上，形成經由上述底層金屬膜而電性連接於上述焊墊電極之再配線之步驟；(e)形成覆蓋上述再配線之上表面及側面之蓋金屬膜之步驟；且上述步驟(e)包含：(e-1)於上述半導體基板之主表面上，形成蓋金屬材料膜之步驟；(e-2)藉由蝕刻上述第1絕緣膜上之上述蓋金屬材料膜，而形成上述蓋金屬膜之步驟；上述步驟(e-2)之上述蝕刻，係於上述底層金屬膜之一部分存在於上述再配線之外側之區域之狀態下實施；於上述步驟(e-2)後，於上述再配線之外側之區域中，上述底層金屬膜與上述蓋金屬膜直接相接。
  7. 如請求項6之半導體裝置之製造方法，其中上述再配線與上述底層金屬膜係以不同材料形成； 上述再配線與上述蓋金屬膜係以不同材料形成。
  8. 如請求項6之半導體裝置之製造方法，其中上述蓋金屬材料膜以包含第1蓋障壁膜、第2蓋障壁膜及第3蓋障壁膜之積層膜形成；上述底層金屬膜與上述第3蓋障壁膜包含相同材料。
  9. 如請求項6之半導體裝置之製造方法，其中上述步驟(d)包含：(d-1)於上述底層金屬膜上形成籽晶膜之步驟；(d-2)於上述籽晶膜上形成露出上述籽晶膜之一部分之抗蝕圖案之步驟；(d-3)於自上述抗蝕圖案露出之上述籽晶膜上，藉由電鍍而形成上述再配線之步驟；(d-4)去除上述抗蝕圖案之步驟；及(d-5)去除上述再配線之外側之區域之上述籽晶膜之步驟；且於上述步驟(e)中，上述蓋金屬膜以覆蓋上述籽晶膜之側面之方式形成。
  10. 如請求項6之半導體裝置之製造方法，其中上述步驟(e-2)包含進行上述底層金屬膜之濕蝕刻之步驟。
  11. 如請求項6之半導體裝置之製造方法，其中上述再配線以Cu為主成分而構成；上述焊墊電極以Al為主成分而構成；上述再配線之膜厚較上述焊墊電極之膜厚更厚。
  12. 如請求項6之半導體裝置之製造方法，其中於上述第1絕緣膜與上述焊墊電極之間形成有第2絕緣膜；上述第2絕緣膜於上述第1絕緣膜之上述第1開口內，具有較上述第1開口小之第2開口。
  13. 如請求項6之半導體裝置之製造方法，其中進而包含於上述步驟(e)後，於上述蓋金屬膜上形成具有第3開口之第3絕緣膜之步 驟；且上述第1絕緣膜與上述第3絕緣膜之各者包含聚醯亞胺膜。
  14. 如請求項6之半導體裝置之製造方法，其中於上述再配線上之上述蓋金屬膜連接銅導線。
  15. 如請求項6之半導體裝置之製造方法，其中進而包含於上述步驟(d)之後，且於上述步驟(e)之前，部分蝕刻上述底層金屬膜之步驟。
  16. 一種半導體裝置之製造方法，其包含：(a)準備半導體基板之步驟；(b)於上述半導體基板上形成絕緣膜之步驟；(e)於上述絕緣膜上，形成底層金屬膜之步驟；(d)於上述底層金屬膜上，形成再配線之步驟；(e)以覆蓋上述再配線之上表面及側面之方式，於上述絕緣膜上依序形成第1蓋障壁膜、第2蓋障壁膜、及第3蓋障壁膜之步驟；(f)使用抗蝕遮罩，於上述再配線之上表面上及側面上殘留上述第3蓋障壁膜，且使形成於上述絕緣膜上之上述第3蓋障壁膜圖案化之步驟；(g)去除上述抗蝕遮罩之步驟；(h)將圖案化之上述第3蓋障壁膜設為遮罩，蝕刻形成於上述絕緣膜上之上述第2蓋障壁膜之步驟；及(i)蝕刻上述再配線之上表面上及側面上之上述第3蓋障壁膜，且蝕刻上述絕緣膜上之上述第1蓋障壁膜及上述底層金屬膜之步驟。
  17. 如請求項16之半導體裝置之製造方法，其中於上述步驟(i)後，於上述再配線之外側之區域，且上述絕緣膜上之區域，存在上 述底層金屬膜與上述第1蓋障壁膜；存在於上述再配線外側之區域之上述底層金屬膜之膜厚、與上述第1蓋障壁膜之膜厚之和，較上述再配線下之上述底層金屬膜之膜厚更厚。
  18. 如請求項16之半導體裝置之製造方法，其中上述第1、第2及第3蓋障壁膜分別為Ti膜、Pd膜及Ti膜；上述底層金屬膜為包含Ti膜、TiN膜及Ti膜之積層膜。
  19. 如請求項16之半導體裝置之製造方法，其中於上述(i)步驟後，露出形成於上述再配線之上表面之上述第2蓋障壁膜；且於上述(i)步驟後，進而包含：(j)於上述第2蓋障壁膜上形成銅導線之步驟。
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