JP2007103714A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2007103714A JP2007103714A JP2005292417A JP2005292417A JP2007103714A JP 2007103714 A JP2007103714 A JP 2007103714A JP 2005292417 A JP2005292417 A JP 2005292417A JP 2005292417 A JP2005292417 A JP 2005292417A JP 2007103714 A JP2007103714 A JP 2007103714A
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Abstract
【解決手段】電子回路が設けられた半導体を含んでパッケージ化された半導体装置であって、基板20に、電子回路が形成された半導体本体(10a,10b)と、半導体本体上に形成されたパッド電極(11a,11b)と、パッド電極に接続して半導体本体表面から突出して形成された突起電極(16a,16b)とを有する半導体チップ(1a,1b)が、突起電極の形成面の裏面側からマウントされ、半導体チップを埋め込んで絶縁層22が形成され、この絶縁層は、突起電極の頂部が露出する高さまで上面から平坦化研削されている構成とする。
【選択図】図1
Description
上記のSiPの構成や製造方法は、例えば特許文献1〜3に開示されている。
次に、半導体チップを埋め込んで絶縁層を形成し、さらに、突起電極の頂部が露出する高さまで、絶縁層の上面から平坦化研削する。
図1は、本実施形態に係る半導体装置の模式断面図である。
例えば、シリコンからなる半導体基板20上に、酸化シリコンなどの絶縁膜21が形成されており、その上層に、例えばトランジスタなどの能動素子を含む電子回路が形成されたシリコンからなる、例えば2個の半導体チップ(1a,1b)がダイアタッチフィルム17によりマウントされている。
上記の第2絶縁層23の開口部内及び第2絶縁層23の上層に、バンプ(16a,16b)に接続して、シード層24及び銅層26からなる第1配線が形成されている。
第3樹脂層27の開口部内及び第3絶縁層27上に、第1配線に接続して、シード層28及び銅層29からなる第2配線が形成されている。
また、導電性ポスト30の外周部において、第2絶縁層23と第3絶縁層27が積層した絶縁層上に形成され、半導体装置が実装基板に実装されたときに発生する応力を緩和する絶縁性のバッファ層31が形成されている。
さらにバッファ層31の表面から突出するように導電性ポスト30に接続してバンプ(突起電極)32が形成されている。
まず、図2(a)に示すように、例えば、φ200mm、0.725mm厚の半導体ウェハ10wにトランジスタなどの能動素子を含む電子回路を形成し、電子回路に接続するパッド電極11と、パッド電極11を開口し、電子回路を被覆するように保護絶縁膜12を形成する。
例えば、感光性ポリイミドをスピンコートで形成する場合、(1000rpm,30秒)+(2000rpm,40秒)+(1000rpm,10秒)+(1500rpm,10秒)で行い、プリベーク処理として(90℃,120秒)+(100℃,120秒)の熱処理を行う。
上記の樹脂絶縁層13のパターニングの後、樹脂絶縁層13の硬化処理を行う。
さらに、例えば、半導体ウェハ10wの裏面にダイアタッチフィルム17をラミネートして張り合わせる。ラミネート条件は、例えばスピード1m/分、圧力10N/cm、温度65℃とする。
以上のようにして本実施形態の半導体装置に内蔵する半導体チップを形成する。得られる半導体チップの板厚は、上記のように数100μm程度となっている。
上記のようにして半導体チップを複数種類作成する。
平坦化の条件は、例えば、#600のホイールでスピンドル回転数3500rpmとして行う。
上記のように、半導体チップ(1a,1b)の板厚(t1,t2)が異なっていても、それぞれに100μmの高さのバンプが形成されており、両半導体チップ(1a,1b)のバンプ(16a,16b)が露出するように第1絶縁層22を研削することで、複数の半導体チップ間で、板厚とバンプの高さの総計が略等しくなるように加工される。このように、バンプの高さを利用して、半導体チップ(1a,1b)の板厚の差を吸収してバンプの頂部では等しい高さとすることが可能となる。
例えば、感光性ポリイミドをスピンコートで78μmの膜厚で形成する場合、(7000rpm,25秒)+(1000rpm,125秒)+(1000rpm,10秒)+(1500rpm,10秒)の塗布条件で行い、プリベークとして(60℃,240秒)+(90℃,240秒)+(110℃,120秒)の熱処理を行う。
上記の第2絶縁層23のパターニングの後、第2絶縁層23の硬化処理を行う。
これにより、シード層24及び銅層26からなる第1配線が形成される。
ここでは、まず、第1配線を被覆して第2絶縁層23の上層に第3絶縁層27を形成し、露光及び現像し、第1配線に達する開口部を開口し、さらに、全面にTiとCuを堆積してシード層28を形成し、第2配線形成領域を開口するレジスト膜をパターン形成し、シード層28を一方の電極とする電解メッキ処理により銅層29を形成し、レジスト膜を除去する。シード層28は、次工程で導電性ポストを形成する電解メッキ処理工程においても用いるので、エッチングせずにおく。
この後、レジスト膜を除去し、さらに導電性ポスト30及び銅層29をマスクとしてウェットエッチングなどを行い、各銅層29間におけるシード層28を除去する。
ポリイミド系樹脂の場合には、印刷法によりNV値27.5のペーストを使用し、スキージで印刷を行うことで形成する。硬化は(100℃,10分)+(150℃,10分)+(200℃,10分)+(250℃,60分)の熱処理で行う。
上記のように研削した後で、バッファ層38の上面縁部の形状は上記のような形状を保っている。
図11は、本実施形態に係る半導体装置の模式断面図である。
実質的に第1実施形態に係る半導体装置と同様である。絶縁層中に埋め込まれる半導体チップ(1c,1d)は、第1実施形態と同様に、半導体本体(10c,10d)の表面にパッド電極(11c,11d)が形成されており、パッド電極(11c,11d)を開口するように保護絶縁膜(12c,12d)が形成され、保護絶縁膜(12c,12d)の上層に、保護絶縁膜(12c,12d)と同様のパターンでパッド電極(11c,11d)を開口する樹脂絶縁膜(13c,13d)が形成されており、その保護絶縁膜(12c,12d)及び樹脂絶縁膜(13c,13d)の形成された開口部内から、所定の高さで、パッド電極(11c,11d)に接続するバンプ(突起電極、16c,16d)が形成された構成であり、パッド電極(11c,11d)と突起電極(16c,16d)の界面に形成されているシード層については図示を省略している。
絶縁層中に埋め込まれる半導体チップ(1c,1d)は、第1実施形態と同様にして形成できる。
但し、ウェハレベルで裏面から研削し、板厚(t3,t4)がいずれも数10μmとなるまで薄型化する。
平坦化の条件は、例えば、#600のホイールでスピンドル回転数3500rpmとして行う。
以降の工程は、第1実施形態と同様にして行うことができる。
図11は、本実施形態に係る半導体装置の模式断面図である。
実質的に第1実施形態に係る半導体装置と同様である。絶縁層中には1個の半導体チップ1eが埋め込まれていることが異なる。半導体チップ1eは、第1実施形態と同様に、半導体本体10eの表面にパッド電極11eが形成されており、パッド電極11eを開口するように保護絶縁膜12eが形成され、保護絶縁膜12eの上層に、保護絶縁膜12eと同様のパターンでパッド電極11eを開口する樹脂絶縁膜13eが形成されており、その保護絶縁膜12e及び樹脂絶縁膜13eの形成された開口部内から、所定の高さで、パッド電極11eに接続するバンプ(突起電極、16e)が形成された構成であり、パッド電極11eとバンプ16eの界面に形成されているシード層については図示を省略している。
上記以外は、実質的に第1実施形態と同様である。
半導体チップ1eの半導体本体10eの板厚は、例えば数100μm程度、あるいは、数10μmにまで薄型化されている。
(1)埋め込む半導体チップを薄化しなくてもチップ埋め込み型のウェーハレベルSiPが実現できる。
(2)埋め込み用樹脂に高価な感光性樹脂を使用する必要がなく、安価な非感光性樹脂を採用できる。
(3)埋め込み用半導体チップの厚みが厚くてもSiPの全厚を厚くすることなく、薄型化にも対応することができる。例えば、電気的特性検査法では400μm厚のウェハ状態で供給されているなど、一部の半導体ウェハやチップは400μm程度の厚みを有し、ウェハあるいはチップの状態で市場に流通されており、このような半導体チップあるいは半導体ウェハから得られるチップをSiPに採用する場合にもそのままの状態で用いることが可能になる。
例えば、基板にも電子回路が形成されていてもよい。この場合には絶縁層に埋め込まれる配線が基板に接続するように形成される。
半導体チップを埋め込む樹脂絶縁層の材料は、上記のように非感光性樹脂材料が用いることができるが、感光性樹脂材料を用いてもよい。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。
また、本発明の半導体装置の製造方法は、システムインパッケージ形態の半導体装置を製造する方法に適用できる。
Claims (12)
- 電子回路が設けられた半導体を含んでパッケージ化された半導体装置であって、
基板と、
前記電子回路が形成された半導体本体と、前記半導体本体上に形成されたパッド電極と、前記パッド電極に接続して前記半導体本体表面から突出して形成された突起電極とを有し、前記突起電極の形成面の裏面側から前記基板にマウントされた半導体チップと、
前記半導体チップを埋め込んで形成され、前記突起電極の頂部が露出する高さまで、上面から平坦化研削された絶縁層と
を有する半導体装置。 - 前記絶縁層の上層に、前記突起電極に接続する上層配線と、前記上層配線を埋め込む上層絶縁層が形成されている
請求項1に記載の半導体装置。 - 前記半導体チップとして複数の半導体チップが前記絶縁層中に埋め込まれている
請求項1に記載の半導体装置。 - 前記複数の半導体チップの板厚が異なる
請求項3に記載の半導体装置。 - 前記板厚が異なる前記複数の半導体チップ間で、前記板厚と前記突起電極の高さの総計が略等しくなるように、前記突起電極が形成されている
請求項4に記載の半導体装置。 - 前記絶縁層が非感光性樹脂から形成されている
請求項1に記載の半導体装置。 - 電子回路が設けられた半導体を含んでパッケージ化された半導体装置の製造方法であって、
基板に、前記電子回路が形成された半導体本体と、前記半導体本体上に形成されたパッド電極と、前記パッド電極に接続して前記半導体本体表面から突出して形成された突起電極とを有する半導体チップを、前記突起電極の形成面の裏面側からマウントする工程と、
前記半導体チップを埋め込んで絶縁層を形成する工程と、
前記突起電極の頂部が露出する高さまで、前記絶縁層の上面から平坦化研削する工程と
を有する半導体装置の製造方法。 - 前記絶縁層の上層から平坦化研削する工程の後に、前記絶縁層の上層に前記突起電極に接続する上層配線と前記上層配線を埋め込む上層絶縁層とを形成する工程をさらに有する
請求項7に記載の半導体装置の製造方法。 - 前記半導体チップをマウントする工程において複数の半導体チップをマウントし、前記絶縁層を形成する工程において前記複数の半導体チップを埋め込み、前記絶縁層を平坦化研削する工程において前記複数の半導体チップのそれぞれの突起電極の頂部が露出する高さまで研削する
請求項7に記載の半導体装置の製造方法。 - 前記複数の半導体チップとして、板厚が異なる複数の半導体チップを用いる
請求項9に記載の半導体装置の製造方法。 - 前記複数の半導体チップとして、前記板厚が異なる前記複数の半導体チップ間で前記板厚と前記突起電極の高さの総計が略等しくなるように前記突起電極が形成されている、複数の半導体チップを用いる
請求項10に記載の半導体装置の製造方法。 - 前記絶縁層を形成する工程において、非感光性樹脂により形成する
請求項7に記載の半導体装置の製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005292417A JP4395775B2 (ja) | 2005-10-05 | 2005-10-05 | 半導体装置及びその製造方法 |
US11/524,957 US7429793B2 (en) | 2005-10-05 | 2006-09-22 | Semiconductor device having an electronic circuit disposed therein |
KR1020060097159A KR101316645B1 (ko) | 2005-10-05 | 2006-10-02 | 반도체 장치 및 그 제조 방법 |
TW095136496A TW200729420A (en) | 2005-10-05 | 2006-10-02 | Semiconductor apparatus and its manufacturing method |
CN2006101421427A CN1945816B (zh) | 2005-10-05 | 2006-10-08 | 半导体器件及其制造方法 |
US12/007,072 US7981722B2 (en) | 2005-10-05 | 2008-01-07 | Semiconductor device and fabrication method thereof |
US12/656,621 US7892887B2 (en) | 2005-10-05 | 2010-02-04 | Semiconductor device and fabrication method thereof |
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US7892887B2 (en) | 2011-02-22 |
CN1945816B (zh) | 2010-12-08 |
US7429793B2 (en) | 2008-09-30 |
KR20070038426A (ko) | 2007-04-10 |
US20070096306A1 (en) | 2007-05-03 |
JP4395775B2 (ja) | 2010-01-13 |
KR101316645B1 (ko) | 2013-10-10 |
US20100144092A1 (en) | 2010-06-10 |
TWI325616B (ja) | 2010-06-01 |
CN1945816A (zh) | 2007-04-11 |
TW200729420A (en) | 2007-08-01 |
US7981722B2 (en) | 2011-07-19 |
US20080138937A1 (en) | 2008-06-12 |
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