JP3925503B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP3925503B2 JP3925503B2 JP2004072265A JP2004072265A JP3925503B2 JP 3925503 B2 JP3925503 B2 JP 3925503B2 JP 2004072265 A JP2004072265 A JP 2004072265A JP 2004072265 A JP2004072265 A JP 2004072265A JP 3925503 B2 JP3925503 B2 JP 3925503B2
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
上記実施形態では、半導体構成体2として、外部接続用電極としての柱状電極12を有するものとしたが、これに限らず、柱状電極12および封止膜13を有せず、配線11の接続パッド部以外を覆うソルダーレジスト等からなるオーバーコート膜を有し、配線11の接続パッド部上およびその近傍のオーバーコート膜上に外部接続用電極としての下地金属層を含む上層接続パッドが設けられたものであってもよい。また、半導体構成体2のシリコン基板4およびベース板1は長方形状であってもよい。
2 半導体構成体
3 接着層
4 シリコン基板
5 接続パッド
6 絶縁膜
8 保護膜
11 配線
12 柱状電極
13 封止膜
14 絶縁層
15 上層絶縁膜
18 上層配線
19 上層オーバーコート膜
21 半田ボール
Claims (15)
- 上面に複数の接続パッドが設けられた平面方形状の半導体基板と、前記半導体基板上において前記接続パッドを除く部分に設けられた絶縁膜と、前記絶縁膜上に前記接続パッドに接続されて設けられた複数の外部接続用電極とを備えた半導体装置において、前記各外部接続用電極は前記半導体基板の対角線に沿って複数列に配列され、対角線寄りに配列された前記各外部接続用電極には、前記対角線寄りに配列された外部接続用電極よりも外側に配列された前記外部接続用電極間に形成された配線が接続されていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記対角線寄りに配列された外部接続用電極と、その外側に配列された外部接続用電極とは、前記対角線に対して垂直となる位置に配列されていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記対角線寄りに配列された外部接続用電極よりも外側に配列された前記外部接続用電極間に形成された配線は、前記対角線に対して垂直な直線部を有することを特徴とする半導体装置。
- 請求項1に記載の発明において、前記対角線寄りに配列された外部接続用電極に接続された配線および前記対角線寄りに配列された外部接続用電極よりも外側に配列された前記外部接続用電極に接続された配線は、前記対角線寄りに配列された外部接続用電極よりも外側に配列された前記外部接続用電極の外側において、前記半導体基板の各側辺に対して垂直に延出されていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記複数の外部接続用電極は、前記半導体基板上においてその2つの対角線の各両側にそれぞれ一定の配置ピッチで2列ずつ最大限に配置されていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記半導体基板は平面正方形状であることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記外部接続用電極は、前記絶縁膜上に前記接続パッドに接続されて設けられた下部配線の接続パッド部上に設けられた柱状電極であることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記外部接続用電極は、前記絶縁膜上に前記接続パッドに接続されて設けられた下部配線の接続パッド部上に設けられた上層接続パッドであることを特徴とする半導体装置。
- ベース板と、前記ベース板上に設けられ、且つ、平面方形状の半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に前記半導体構成体の外部接続用電極に接続されて設けられた配線とを備えた半導体装置において、前記各外部接続用電極は前記半導体基板の対角線に沿って複数列に配列され、対角線寄りに配列された前記各外部接続用電極には、前記対角線寄りに配列された外部接続用電極よりも外側に配列された前記外部接続用電極間に形成された配線が接続されていることを特徴とする半導体装置。
- 請求項9に記載の発明において、前記複数の外部接続用電極は、前記半導体基板上においてその2つの対角線の各両側にそれぞれ一定の配置ピッチで2列ずつ最大限に配置されていることを特徴とする半導体装置。
- 請求項9に記載の発明において、前記配線のうち、前記対角線側に配置された前記外部接続用電極に接続された配線は、前記対角線側とは反対側に配置された前記外部接続用電極間において前記対角線に対して垂直となるように配置されていることを特徴とする半導体装置。
- 請求項9に記載の発明において、前記ベース板および前記半導体基板は平面正方形状であることを特徴とする半導体装置。
- 請求項9に記載の発明において、前記配線の接続パッド部以外を覆うオーバーコート膜を有することを特徴とする半導体装置。
- 請求項13に記載の発明において、前記配線の接続パッド部上に半田ボールが設けられていることを特徴とする半導体装置。
- 請求項14に記載の発明において、前記半田ボールは前記絶縁層に対応する領域上のみに配置されていることを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004072265A JP3925503B2 (ja) | 2004-03-15 | 2004-03-15 | 半導体装置 |
US11/078,175 US7427812B2 (en) | 2004-03-15 | 2005-03-11 | Semiconductor device with increased number of external connection electrodes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004072265A JP3925503B2 (ja) | 2004-03-15 | 2004-03-15 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2005260120A JP2005260120A (ja) | 2005-09-22 |
JP3925503B2 true JP3925503B2 (ja) | 2007-06-06 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2004072265A Expired - Fee Related JP3925503B2 (ja) | 2004-03-15 | 2004-03-15 | 半導体装置 |
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US (1) | US7427812B2 (ja) |
JP (1) | JP3925503B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4093186B2 (ja) * | 2004-01-27 | 2008-06-04 | カシオ計算機株式会社 | 半導体装置の製造方法 |
JP4458010B2 (ja) * | 2005-09-26 | 2010-04-28 | カシオ計算機株式会社 | 半導体装置 |
JP4395775B2 (ja) * | 2005-10-05 | 2010-01-13 | ソニー株式会社 | 半導体装置及びその製造方法 |
JP2008060298A (ja) * | 2006-08-31 | 2008-03-13 | Casio Comput Co Ltd | 半導体構成体およびその製造方法並びに半導体装置およびその製造方法 |
US7619901B2 (en) * | 2007-06-25 | 2009-11-17 | Epic Technologies, Inc. | Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system |
EP2176883A2 (en) * | 2007-08-08 | 2010-04-21 | Casio Computer Co., Ltd. | Semiconductor device and method for manufacturing the same |
US8169065B2 (en) * | 2009-12-22 | 2012-05-01 | Epic Technologies, Inc. | Stackable circuit structures and methods of fabrication thereof |
JP2012074581A (ja) * | 2010-09-29 | 2012-04-12 | Teramikros Inc | 半導体装置及びその製造方法 |
JP2012134270A (ja) * | 2010-12-21 | 2012-07-12 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4495377A (en) | 1982-12-30 | 1985-01-22 | International Business Machines Corporation | Substrate wiring patterns for connecting to integrated-circuit chips |
JPH0653272A (ja) | 1992-07-28 | 1994-02-25 | Nippon Steel Corp | 半導体チップ及びtab方式半導体装置 |
JPH0774203A (ja) | 1993-09-01 | 1995-03-17 | Fujitsu Ltd | 半導体集積回路装置及びその製造方法 |
JP3334816B2 (ja) | 1993-09-10 | 2002-10-15 | ソニー株式会社 | 半導体装置及び半導体装置の実装方法 |
JP2570628B2 (ja) * | 1994-09-21 | 1997-01-08 | 日本電気株式会社 | 半導体パッケージおよびその製造方法 |
JPH08279535A (ja) | 1995-04-07 | 1996-10-22 | Citizen Watch Co Ltd | 半導体装置 |
JP2935356B2 (ja) | 1997-02-20 | 1999-08-16 | 日本電気株式会社 | 半導体装置および基板ならびに半導体装置の実装構造 |
JP3287310B2 (ja) | 1998-06-30 | 2002-06-04 | カシオ計算機株式会社 | 半導体装置及びその製造方法 |
JP2003298005A (ja) | 2002-02-04 | 2003-10-17 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP4082220B2 (ja) * | 2003-01-16 | 2008-04-30 | セイコーエプソン株式会社 | 配線基板、半導体モジュールおよび半導体モジュールの製造方法 |
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2004
- 2004-03-15 JP JP2004072265A patent/JP3925503B2/ja not_active Expired - Fee Related
-
2005
- 2005-03-11 US US11/078,175 patent/US7427812B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7427812B2 (en) | 2008-09-23 |
JP2005260120A (ja) | 2005-09-22 |
US20050200018A1 (en) | 2005-09-15 |
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