JP4458010B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4458010B2 JP4458010B2 JP2005277046A JP2005277046A JP4458010B2 JP 4458010 B2 JP4458010 B2 JP 4458010B2 JP 2005277046 A JP2005277046 A JP 2005277046A JP 2005277046 A JP2005277046 A JP 2005277046A JP 4458010 B2 JP4458010 B2 JP 4458010B2
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- 239000004065 semiconductor Substances 0.000 title claims description 123
- 239000000758 substrate Substances 0.000 claims description 29
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 230000001681 protective effect Effects 0.000 claims description 12
- 238000007789 sealing Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 75
- 239000010408 film Substances 0.000 description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 239000010953 base metal Substances 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 239000003822 epoxy resin Substances 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
2 第1の半導体構成体
3 接着層
4 シリコン基板
5 接続パッド
11 配線
12 柱状電極
13 封止膜
21 絶縁層
22 第1の上層絶縁膜
25 第1の上層配線
26 第2の上層絶縁膜
28 第2の上層配線
32 下層配線
33 下層絶縁膜
35 半田ボール
36 貫通孔
37 上下導通部
41 第2の半導体構成体
42 シリコン基板
44 半田ボール
51 第2の半導体構成体
52 シリコン基板
57 半田ボール
Claims (6)
- ベース板と、前記ベース板上に設けられ、且つ、半導体基板および該半導体基板上に設けられた複数の外部接続用電極を有する第1の半導体構成体と、前記第1の半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記第1の半導体構成体および前記絶縁層上に設けられた上層絶縁膜と、前記上層絶縁膜上に前記第1の半導体構成体の外部接続用電極に電気的に接続して設けられた上層配線と、前記上層配線の接続パッド部に接合されて搭載された複数の第2の半導体構成体とを具備し、上面から見て、前記第2の半導体構成体の前記上層配線の接続パッド部に対する接合部分はすべて前記第1の半導体構成体に対応する領域内に配置されていることを特徴とする半導体装置。
- 請求項1に記載の発明において、前記第2の半導体構成体は前記第1の半導体構成体に対応する領域内に搭載されていることを特徴とする半導体装置。
- 請求項1に記載の発明において、さらに、前記ベース板下に設けられた下層配線と、前記ベース板、前記絶縁層および前記上層絶縁膜に設けられた貫通孔内に前記上層配線と前記下層配線とを接続するように設けられた上下導通部とを具備することを特徴とする半導体装置。
- 請求項1に記載の発明において、前記半導体基板は複数の接続パッドを有し、前記第1の半導体構成体は前記各接続パッドに対応する開口部を有する保護膜と、前記保護膜上に前記各接続パッドに接続されて設けられた配線と、前記配線の接続バッド部に設けられた前記外部接続用電極と、前記保護膜上における前記外部接続用電極間に設けられた封止膜とを具備し、前記外部接続用電極は柱状であることを特徴とする半導体装置。
- 請求項4に記載の発明において、前記第2の半導体構成体は複数の接続パッドを有する半導体基板と、前記各接続パッドに対応する開口部を有する保護膜と、前記保護膜上に前記各接続パッドに接続されて設けられた配線と、前記配線の接続バッド部に設けられた外部接続用電極と、前記保護膜上における前記外部接続用電極間に設けられた封止膜とを具備することを特徴とする半導体装置。
- 請求項3に記載の発明において、前記下層配線の接続パッド部下に半田ボールが設けられていることを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005277046A JP4458010B2 (ja) | 2005-09-26 | 2005-09-26 | 半導体装置 |
US11/524,481 US7247947B2 (en) | 2005-09-26 | 2006-09-20 | Semiconductor device comprising a plurality of semiconductor constructs |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005277046A JP4458010B2 (ja) | 2005-09-26 | 2005-09-26 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007088313A JP2007088313A (ja) | 2007-04-05 |
JP4458010B2 true JP4458010B2 (ja) | 2010-04-28 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005277046A Active JP4458010B2 (ja) | 2005-09-26 | 2005-09-26 | 半導体装置 |
Country Status (2)
Country | Link |
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US (1) | US7247947B2 (ja) |
JP (1) | JP4458010B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101269903B1 (ko) | 2011-06-27 | 2013-05-31 | 주식회사 심텍 | 다이스택 패키지 및 제조 방법 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2464078C (en) * | 2002-08-09 | 2010-01-26 | Casio Computer Co., Ltd. | Semiconductor device and method of manufacturing the same |
DE102004029584A1 (de) * | 2004-06-18 | 2006-01-12 | Infineon Technologies Ag | Anordnung zur Erhöhung der Zuverlässigkeit von substratbasierten BGA-Packages |
JP2006173232A (ja) * | 2004-12-14 | 2006-06-29 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
KR100688857B1 (ko) * | 2004-12-17 | 2007-03-02 | 삼성전기주식회사 | 윈도우를 구비한 볼 그리드 어레이 기판 및 그 제조방법 |
JP4289335B2 (ja) * | 2005-08-10 | 2009-07-01 | セイコーエプソン株式会社 | 電子部品、回路基板及び電子機器 |
JP2010073771A (ja) * | 2008-09-17 | 2010-04-02 | Casio Computer Co Ltd | 半導体装置の実装構造 |
US8987896B2 (en) * | 2009-12-16 | 2015-03-24 | Intel Corporation | High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same |
US20110156240A1 (en) * | 2009-12-31 | 2011-06-30 | Stmicroelectronics Asia Pacific Pte. Ltd. | Reliable large die fan-out wafer level package and method of manufacture |
US8884422B2 (en) * | 2009-12-31 | 2014-11-11 | Stmicroelectronics Pte Ltd. | Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture |
US8343810B2 (en) * | 2010-08-16 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers |
US9013037B2 (en) | 2011-09-14 | 2015-04-21 | Stmicroelectronics Pte Ltd. | Semiconductor package with improved pillar bump process and structure |
US8916481B2 (en) | 2011-11-02 | 2014-12-23 | Stmicroelectronics Pte Ltd. | Embedded wafer level package for 3D and package-on-package applications, and method of manufacture |
WO2013084384A1 (ja) * | 2011-12-08 | 2013-06-13 | パナソニック株式会社 | 半導体装置及びその製造方法 |
KR102549402B1 (ko) * | 2016-08-04 | 2023-06-28 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW577160B (en) * | 2002-02-04 | 2004-02-21 | Casio Computer Co Ltd | Semiconductor device and manufacturing method thereof |
JP3888302B2 (ja) * | 2002-12-24 | 2007-02-28 | カシオ計算機株式会社 | 半導体装置 |
WO2004064153A1 (en) * | 2003-01-16 | 2004-07-29 | Casio Computer Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2004349361A (ja) * | 2003-05-21 | 2004-12-09 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP4269806B2 (ja) * | 2003-06-30 | 2009-05-27 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP4379693B2 (ja) | 2003-11-10 | 2009-12-09 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP4055717B2 (ja) * | 2004-01-27 | 2008-03-05 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP3925503B2 (ja) * | 2004-03-15 | 2007-06-06 | カシオ計算機株式会社 | 半導体装置 |
JP4398305B2 (ja) * | 2004-06-02 | 2010-01-13 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
-
2005
- 2005-09-26 JP JP2005277046A patent/JP4458010B2/ja active Active
-
2006
- 2006-09-20 US US11/524,481 patent/US7247947B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101269903B1 (ko) | 2011-06-27 | 2013-05-31 | 주식회사 심텍 | 다이스택 패키지 및 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
US20070069272A1 (en) | 2007-03-29 |
JP2007088313A (ja) | 2007-04-05 |
US7247947B2 (en) | 2007-07-24 |
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