CN1945816B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1945816B
CN1945816B CN2006101421427A CN200610142142A CN1945816B CN 1945816 B CN1945816 B CN 1945816B CN 2006101421427 A CN2006101421427 A CN 2006101421427A CN 200610142142 A CN200610142142 A CN 200610142142A CN 1945816 B CN1945816 B CN 1945816B
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semiconductor
insulating barrier
semiconductor chip
semiconductor device
electrode
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CN1945816A (zh
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山形修
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Sony Corp
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Sony Corp
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Abstract

提供了一种半导体器件以及其制造方法。一种半导体器件，将其封装成包括设置了电子电路的半导体，该半导体器件包括：基板；半导体芯片，其具有形成有电子电路的半导体主体、形成于半导体主体上的衬垫电极、以及连接到衬垫电极并从半导体主体表面突起的突起电极，其中从表面的背面侧将半导体芯片安装在基板上以在其上形成突起电极；和绝缘层，该绝缘层被形成为其中埋入有半导体芯片并从该绝缘层的顶表面将其抛光至暴露出突起电极的顶部的高度。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请包含了涉及到2005年10月5日于日本专利局提出的日本专利申请JP2005-292417的主题，在此通过参考将其全部内容并入本文。
技术领域
本发明涉及一种半导体器件及其制造方法，尤其涉及一种以晶片级封装芯片的所谓系统封装(SiP)形式的半导体器件及其制造方法。
背景技术
对于实现小尺寸、薄型和轻重量的便携式电子器件应用如数字视频照相机、数字蜂窝电话、或笔记本个人计算机，存在日益增加的需要。为了响应于该需要，一方面，在小型化半导体器件如近来的VLSI中实现了70％的降低。另一方面，对于其中将这种半导体器件安装在印刷线路板上的电子电路器件中，作为重要挑战，已经对怎样提高在基板(印刷线路板)上的部件封装密度进行了研究和开发。
例如，对于半导体器件的封装形式，将该形式从导线插入型如DIP(双列直插式封装)切换到表面安装型。而且，开发出一种倒装芯片安装，其中，由于其面向下设置，因此由焊料或金形成的突起(突起电极)设置在半导体芯片的衬垫电极上，且芯片通过该突起连接到线路板。
而且，现在正在开发一种复杂形式的封装，称作系统封装(SiP)，其中，在绝缘形成于半导体衬底(芯片)上的重新布线层的绝缘层中，对于晶片级封装，掩埋了具有在其中包括了有源器件的电路和无源器件如电容器件和线圈的半导体芯片。
例如在专利参考文献1至3中公开了SiP的结构和制造方法。
例如，对于其中具有有源器件的半导体芯片掩埋在绝缘层中的晶片级SiP的制造方法，将半导体芯片安装到基板上，用光敏树脂通过旋涂或印刷来掩埋半导体芯片，以形成绝缘层，通过曝光和显影来图形化获得的绝缘层，以形成用于半导体芯片的衬垫电极的开口，通过电镀将导电层埋入开口中，并然后形成重新布线层。
在SiP的制造方法中，在形成由具有埋入其中的半导体芯片的树脂形成的绝缘层的工艺步骤中，为了形成具有50μm或更大厚度的绝缘层，必须使用高粘性树脂。由单次旋涂制成的膜厚度最大值限于100μm。例如，当形成厚度与具有几个100μm厚度的半导体芯片相关的绝缘层时，对于每个单次旋涂必须临时干燥该层，以防止第一次的涂层在用于第二次旋涂的工艺步骤中溶解，从而确保膜厚度。
在如上所述地用树脂绝缘层埋入厚半导体芯片的工艺步骤之后，在用于图形化以形成半导体芯片衬垫电极开口的曝光工艺步骤中，根据将被暴露的树脂绝缘膜的膜厚度，必须增加曝光量。因此，曝光量的增加引起图形变形，且难以进行稳定的图形化。
尤其，当在相同的树脂绝缘层中埋入厚度不同的多个半导体芯片时，半导体芯片的衬垫电极的深度不同。由此，由于将焦点调整为两个衬垫电极，因此存在曝光中聚焦深度不同以及不能以高精确度形成开口的问题。因此，通过之前的方法，仅可安装具有相同厚度的半导体芯片。
专利参考文献1：JP-A-2005-175402
专利参考文献2：JP-A-2005-175320
专利参考文献3：JP-A-2005-175319
发明内容
希望提供一种半导体器件及其制造方法，其中把将埋入到绝缘膜中的半导体芯片的衬垫电极连接到在SiP形式的半导体器件中精细布线上的上布线层，其中半导体芯片埋入绝缘膜中。
根据本发明实施例的半导体器件是一种由于其包括设置了电路的半导体而将其封装的半导体器件，该半导体器件包括：基板；半导体芯片，其具有形成有电子电路的半导体主体、形成于半导体主体上的衬垫电极和连接到衬垫电极并从半导体主体表面突起的突起电极，其中半导体芯片从表面的背面侧安装到基板上，以在其上形成突起电极；和绝缘层，该绝缘层被形成为其中埋入有半导体芯片且从绝缘层的顶面抛光至暴露出突起电极的顶部的高度。
根据本发明实施例的半导体器件是一种由于其包括设置了电路的半导体而封装的半导体器件，该器件中：具有其上形成了电子电路的半导体主体的半导体芯片，形成于半导体主体上的的衬垫电极和连接到衬垫电极并从半导体主体表面突起的突起电极，其中，半导体芯片从表面的背面侧安装在基板上，以于其上形成突起电极，且形成绝缘层，同时将半导体芯片埋入其中，并从绝缘层的顶表面抛光至暴露出突起电极顶部的高度。
此外，根据本发明实施例的半导体器件的制造方法是由于其包括设置了电路的半导体而封装的半导体器件的制造方法，该制造方法包括步骤：在基板上安装半导体芯片，该半导体芯片具有其上形成了电子电路的半导体主体，形成于半导体主体上的衬垫电极以及连接到衬垫电极并从半导体主体表面突出的突起电极，其中半导体芯片从表面的背面侧安装在基板上，以于其上形成突起电极；形成绝缘层，同时将半导体芯片埋入其中；以及从绝缘层的顶表面抛光绝缘层至暴露出突起电极的顶部的高度。
根据本发明实施例的半导体器件的制造方法是由于其包括设置了电子电路的半导体而封装的半导体器件的制造方法。首先，将半导体芯片安装到基板上。半导体芯片具有其上形成有电子电路的半导体主体，形成于半导体主体上的衬垫电极和连接到衬垫电极并从半导体主体表面突出的突起电极。该半导体芯片从表面的背面侧安装，以于其上形成突起电极。
随后，埋入半导体芯片以形成绝缘层。而且，从顶表面抛光绝缘层至暴露出突起电极的顶部的高度。
构成根据本发明实施例的半导体器件，其中抛光将半导体芯片埋入其中的绝缘层以暴露出SiP形式的半导体器件中的突起电极，其中半导体芯片埋入绝缘膜中。在该器件中，可不通过光刻工艺步骤来精细制作半导体芯片的衬垫电极，并将其连接到上布线层。
根据本发明实施例的半导体器件的制造方法是其中在SiP形式的半导体器件的制造方法中，抛光其中埋入半导体芯片的绝缘层以暴露出突起电极的方法。通过该方法，可不通过光刻工艺步骤来精细制作半导体芯片的衬垫电极，并将其连接到上布线层。
附图说明
图1示出了描述出根据本发明第一实施例的半导体器件的示意性截面图；
图2A至2C示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图3A至3C示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图4A至4C示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图5A至5C示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图6A至6C示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图7A至7C示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图8A和8B示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图9A和9B示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图10A和10B示出了描述出根据本发明第一实施例的半导体器件的制造方法的制造工艺步骤的截面图；
图11示出了描述出根据本发明第二实施例的半导体器件的示意性截面图；
图12A至12C示出了描述出根据本发明第二实施例的半导体器件的制造方法的制造工艺步骤的截面图；和
图13示出了描述出根据本发明第三实施例的半导体器件的示意性截面图。
具体实施方式
以下，将参考附图描述根据本发明实施例的半导体器件及其制造方法的实施例。
第一实施例
图1示出了描述出根据本实施例的半导体器件的示意性截面图。
例如，在由硅形成的半导体基板20上，形成氧化硅的绝缘膜21。在其上方，例如用管芯粘附膜17安装两个半导体芯片(1a和1b)，该半导体芯片由硅形成，其上形成有电路，包括有源器件如晶体管。
在半导体芯片(1a和1b)中，在例如其上形成有电子电路的半导体主体(10a和10b)的表面上形成衬垫电极(11a和11b)，并形成保护绝缘膜(12a和12b)以便制作用于衬垫电极(11a和11b)的开口。在保护绝缘膜(12a和12b)上方，形成树脂绝缘膜(13a和13b)，从而以与保护绝缘膜(12a和12b)的图形相同的图形制作用于衬垫电极(11a和11b)的开口。在形成于保护绝缘膜(12a和12b)和树脂绝缘膜(13a和13b)中的开口中，以预定高度形成连接到衬垫电极(11a和11b)的突起(突起电极16a和16b)。在此，事实上，在衬垫电极(11a和11b)和突起电极(16a和16b)之间的界面上，形成制作突起(16a和16b)的籽晶层。然而，在图中为了简单省略了籽晶层。
例如，两个半导体芯片(1a和1b)的半导体主体(10a和10b)的厚度(t1和t2)可以彼此不同。例如，t1和t2每一个是几个100μm，且差值例如在100μm内。
例如，形成由非光敏性绝缘树脂形成的第一绝缘层22，以便埋入半导体芯片(1a和1b)。从顶表面抛光第一绝缘层22至暴露出半导体芯片(1a和1b)的突起(16a和16b)顶部的高度。
在此，如上所述，两个半导体芯片(1a和1b)的半导体主体(10a和10b)的厚度(t1和t2)相互不同。以在具有不同厚度(t1和t2)的半导体主体(10a和10b)的多个半导体芯片(1a和1b)当中厚度(t1和t2)和突起(16a和16b)的高度总和近似相等的方式形成突起(16a和16b)。例如，形成突起(16a和16b)，以具有100μm的直径、最大100μm的高度且纵横比为1.0或者更小。
在其表面中暴露出突起(16a和16b)顶部的第一绝缘层22上方，形成由光敏树脂形成的第二绝缘层23，且在其中形成开口。穿过该开口暴露出突起(16a和16b)顶部。
在第二绝缘层23的开口中和第二绝缘层23的上方，形成第一布线，其连接到突起(16a和16b)，第一布线由籽晶层24和铜层26形成。
在第二绝缘层23上方，形成第三绝缘层27，其覆盖第一布线。在第三绝缘层27中，形成达到第一布线的开口。
在第三绝缘层27的开口中和第三绝缘层27的上方，形成连接到第一布线并由籽晶层28和铜层29形成的第二布线。
在具有叠置有第三绝缘层27的第二绝缘层23的绝缘层上方，形成连接到第二布线的导电柱30。
此外，在导电柱30周围，形成绝缘缓冲层31，其形成在具有叠置有第三绝缘层27的第二绝缘层23的绝缘层上，并松弛当将半导体器件安装到基板上时产生的应力。
而且，形成突起(突起电极)32，其连接到导电柱30，从缓冲层31的表面突起。
如上所述，第二绝缘层23叠置有第三绝缘层27和缓冲层31，以形成上绝缘层。形成埋入到上绝缘层中的上布线层如第一布线、第二布线和导电柱，以连接到半导体芯片(1a和1b)的突起(16a和16b)。
构造根据该实施例的半导体器件，其中抛光其中埋入半导体芯片的绝缘层，以暴露出SiP半导体器件中的突起(突起电极)，其中半导体芯片埋入在绝缘膜中，该半导体器件是不通过光刻工艺步骤来精细制作半导体芯片的衬垫电极且能够将该衬垫电极连接到上布线层的半导体器件。
第一和第二布线或进一步叠置的一部分布线可构造无源器件，如电容器件和电感。例如，组合这些无源器件以构造例如LPF(低通滤波器)、BPF(带通滤波器)或HPF(高通滤波器)。此外，可将这些与设置在电子电路上的有源器件相组合以构造所谓的SiP半导体器件。
接下来，将描述根据本实施例的半导体器件的制造方法。
首先，如图2A中所示，例如，在具有φ200mm直径和0.725mm厚度的半导体晶片10w上，形成包括有源器件如晶体管的电子电路。形成用于衬垫电极11的开口和连接到所述电子电路的衬垫电极11，并然后形成保护绝缘膜12，其覆盖所述电子电路。
随后，如图2B中所示，通过旋涂以约10μm的膜厚度涂敷光敏树脂如聚酰亚胺、苯酚、环氧树脂，以形成树脂绝缘层13。例如，当通过旋涂形成光敏性聚酰亚胺时，其以时间周期(30秒1000rpm)+(40秒2000rpm)+(10秒1000rpm)+(10秒1500rpm)形成，和作为预烘焙工艺以时间周期(120秒90℃)+(120秒100℃)进行热处理。
随后，如图2C中所示，例如，以该图形进行曝光和显影，以形成衬垫电极11的开口和在树脂绝缘层13中形成开口，穿过该开口暴露出衬垫电极11。例如，在125mJ/cm2的曝光量下进行该曝光。
在图形化树脂绝缘层13之后，固化树脂绝缘层13。
随后，如图3A中所示，通过溅射覆盖树脂绝缘层13中形成的开口的内壁表面。例如，以Ti为600nm膜厚度和然后Cu为600nm膜厚度的方式沉积膜，并对于随后处理步骤中的电解电镀工艺，形成籽晶层14。
随后，如图3B中所示，例如，通过光刻工艺步骤，将抗蚀剂膜15形成为打开用于在树脂绝缘层13中形成的开口和突起形成区域的开口的图形。
随后，如图3C中所示，例如，通过电解电镀工艺，其中籽晶层14是电极中的一个，在除了形成有抗蚀剂膜15的区域外的区域上方沉积铜，并形成突起16。例如该铜电镀工艺的条件为1.5ASD(A/dm2)。例如，形成突起16以具有100μm直径、最大为100μm的高度和1.0或者更小的纵横比。
随后，如图4A中所示，通过溶剂除去抗蚀剂膜15，并将突起16用作湿法蚀刻的掩模，以除去在突起16之间的籽晶层14。
随后，如图4B中所示，例如如果必要的话，通过#2000的转轮来研磨半导体晶片10的背侧，直到半导体晶片10w的厚度达到约几个100μm。
而且，例如，叠置管芯粘附膜17并将其粘附至半导体晶片10w的背侧。例如，叠置条件是1m/分钟的速度，10N/cm的压力和65℃的温度。
随后，如图4C中所示，切片半导体晶片10w，以形成预定形状的半导体芯片1。例如，切片条件是主轴旋转数目是4000rpm，进给速度是10mm/秒。
如上所述，形成在根据本实施例的半导体器件中建立的半导体芯片。获得的半导体芯片的厚度是约如上所述的几个100μm。
如上所述，制造多种类型的半导体芯片。
随后，如图5A中所示，在以表面上形成有绝缘膜21如氧化硅的晶片的形式的基板20w上，识别在基板20w上完成的对准标记，以通过使用管芯粘附膜17的热压接合来面朝上安装由此形成的具有不同厚度的两个半导体芯片(1a和1b)。例如，热压接合条件是1.6N的加载、160℃的温度和两秒的时间周期。
在两个半导体芯片(1a和1b)的结构中，在半导体主体(10a和10b)的表面上形成衬垫电极(11a和11b)。形成保护绝缘膜(12a和12b)以形成用于衬垫电极(11a和11b)的开口。在保护绝缘膜(12a和12b)上方，形成树脂绝缘膜(13a和13b)，其中以与保护绝缘膜(12a和12b)的图形相同的图形形成用于衬垫电极(11a和11b)的开口。在形成于保护绝缘膜(12a和12b)和树脂绝缘膜(13a和13b)中的开口中以预定高度形成突起(突起电极16a和16b)，该突起连接到衬垫电极(11a和11b)。此外，在图中省略了籽晶层，该籽晶层形成于衬垫电极(11a和11b)和突起电极(16a和16b)之间的界面上。
半导体芯片(1a和1b)的半导体主体(10a和10b)的厚度(t1和t2)是约400μm或约725μm，例如，t1和t2中每一个都设置成几个100μm，t1和t2彼此不同，但是差别例如在100μm以内。
随后，如图5B中所示，例如，遍及半导体芯片(1a和1b)的表面通过印刷或模塑来涂敷非光敏树脂材料如环氧树脂、丙烯酸、苯酚和聚酰亚胺，以形成第一绝缘层22。
随后，如图5C中所示，例如，从顶表面抛光第一绝缘层22直到暴露出突起(16a和16b)的顶部。
例如，抛光条件是用#600转轮的主轴3500rpm的旋转数目。
如上所述，即使变化半导体芯片(1a和1b)的厚度(t1和t2)，两个芯片也都具有其上100μm高度的突起。抛光第一绝缘层22以暴露出半导体芯片(1a和1b)的突起(16a和16b)，从而以在多个半导体芯片当中厚度和突起的总高度近似相等的方式来处理芯片。如上所述，利用突起的高度来减少半导体芯片(1a和1b)厚度之间的差别，并在突起的顶部处使得该高度相等。
如上所述，在半导体芯片的厚度是400μm或者以上的情况下，当通过如前述的旋涂用光敏材料埋入芯片时，不能在单次涂敷中形成光敏材料膜。然而，由于由此抛光第一绝缘膜以暴露出突起，因此不必使用光敏树脂材料。可选择能够通过单次涂敷形成绝缘层22的树脂并确保导电性。
随后，如图6A中所示，可通过旋涂来涂敷光敏树脂如聚酰亚胺、苯酚和环氧树脂，以形成第二绝缘层23。
例如，当通过旋涂形成膜厚为78μm的光敏性聚酰亚胺时，其在时间周期为(25秒7000rpm)+(125秒1000rpm)+(10秒1000rpm)+(10秒1500rpm)的涂敷条件下形成，和作为预烘焙进行时间周期为(240秒60℃)+(240秒90℃)+(120秒110℃)的热处理。
随后，如图6B中所示，例如，进行曝光和显影以在第二绝缘层23中形成用于半导体芯片(1a和1b)的突起(16a和16b)的开口。此外，可在形成了电感器和其它器件的区域中形成开口。例如，以300mJ/cm2的曝光量进行该曝光。
在图形化第二绝缘层23之后，固化第二绝缘层23。
随后，如图6C中所示，通过溅射来覆盖形成于第一绝缘层22中的开口的内壁表面，例如，以Ti为160nm膜厚且之后Cu为600nm膜厚的方式沉积膜，例如，对于随后的工艺步骤中的电解电镀工艺，形成籽晶层24。
随后，如图7A中所示，例如，通过光刻工艺步骤，以形成开口和形成在第一绝缘层23中的第一布线形成区域的图形来形成抗蚀剂膜25。
随后，如图7B中所示，例如，通过籽晶层24作为一个电极的电解电镀工艺，将铜沉积在除了形成抗蚀剂膜5的区域之外的区域上方，并以预定布线电路图形形成铜层26。例如，电镀条件是400mA/50分钟的电流密度。
随后，如图7C中所示，例如，通过溶剂除去抗蚀剂膜25。而且，将铜层26用作湿法蚀刻的掩模，以除去在铜层26之间的籽晶层24。
由此，形成了由籽晶层24和铜层26形成的第一布线。
随后，重复与上述那些相同的工艺步骤，如图8A中所示，叠置由第三绝缘层27、第二籽晶层28和铜层29形成的第二布线。
在此，首先，覆盖第一布线以在第二绝缘层23上方形成用于曝光和显影的第三绝缘层27，以形成到达第一布线的开口。而且，遍及该表面上方沉积Ti和Cu，以形成籽晶层28，从而图形化抗蚀剂膜用于第二布线形成区域的开口。通过籽晶层28为一个电极的电解电镀工艺，形成铜层29以除去抗蚀剂膜。由于籽晶层28也用在随后工艺步骤中的形成导电柱的电解电镀工艺步骤中，因此没有蚀刻它。
随后，如图8B中所示，例如，通过光刻工艺步骤，以形成用于导电柱形成区域的开口的图形来图形化抗蚀剂膜。而且，通过籽晶层28是一个电极的电解电镀工艺，形成由铜形成的导电柱30，以连接到第二布线。由铜形成的导电柱的直径是180μm，且高度是80μm。
之后，除去抗蚀剂膜，将导电柱30和铜层29用作湿法蚀刻的掩模，并除去在铜层29之间的籽晶层28。
如上所述，通过重复工艺步骤，形成叠置了第一绝缘层和第二绝缘层的或者叠置了更多树脂层的绝缘层。此外，可叠置具有第一布线和第二布线或更多叠置布线的布线，其埋入在绝缘层中。
随后，如图9A中所示，在导电柱30周围的第三绝缘层27上方，通过印刷或模塑形成绝缘缓冲层31，例如，其由树脂如环氧树脂、聚酰亚胺和硅形成，并松弛当将半导体器件安装到基板上时产生的应力。
在聚酰亚胺树脂的情况下，通过印刷形成缓冲层，其中将具有NV值为27.5的胶用于使用碾辊的印刷。对于固化，进行时间周期为(10分钟100℃)+(10分钟150℃)+(10分钟200℃)+(60分钟250℃)的加热处理。
随后，如图9B中所示，例如，从顶部表面抛光缓冲层31，以暴露出导电柱30的顶部。例如，条件是使用#600转轮、0.5mm/秒的3500rpm的时间周期。
如上所述，在如此抛光之后，缓冲层38的顶表面边缘的形状保持为如上所述的形状。
随后，如图10A中所示，例如，用焊球或焊胶在暴露出的导电柱上形成突起(突起电极)32。
随后，如图10B中所示，研磨晶片以从基板20w的背面侧减小厚度，并然后在切片线上切片，从而制造具有如图1中所示结构的半导体器件。
在半导体器件中，在减小了其中建立的半导体芯片厚度的情况下，当还降低基板厚度时，整个半导体器件的总厚度可降低到725μm厚。当进一步降低厚度时，研磨更多的所安装的半导体芯片。在LGA的情况下，其是厚度降低到250μm总厚度的结构。
根据该实施例的半导体器件的制造方法，在SiP形式的半导体器件的制造方法中，其中半导体芯片埋入绝缘膜中，抛光埋入半导体芯片的绝缘膜以暴露出突起电极。因此，可以不通过光刻工艺步骤来精细制造半导体芯片的衬垫电极，并将其连接到上布线层。
第二实施例
图11示出了描述出根据本实施例的半导体器件的示意性截面图。
其基本与根据第一实施例的半导体器件相同。与第一实施例相类似，在将埋入绝缘层中的半导体芯片(1c和1d)的结构中，在半导体主体(10c和10d)的表面上形成衬垫电极(11c和11d)。形成保护绝缘膜(12c和12d)，以形成用于衬垫电极(11c和11d)的开口。在保护绝缘膜(12c和12d)上方，以与保护绝缘膜(12c和12d)的图形相同的图形形成树脂绝缘膜(13c和13d)，以形成用于衬垫电极(11c和11d)的开口。在形成于保护绝缘膜(12c和12d)和树脂绝缘膜(13c和13d)中的开口中，以预定高度形成突起(突起电极16c和16d)，其连接到衬垫电极(11c和11d)。在图中省略了籽晶层，该籽晶层形成于衬垫电极(11c和11d)和突起电极(16c和16d)之间的界面上。
在此，将半导体芯片(1c和1d)的半导体主体(10c和10d)的厚度(t3和t4)降低到几个10μm厚。尽管t3和t4可以彼此不同，但是例如将其差值设置在10μm内。
根据本实施例的半导体器件具有抛光埋入半导体芯片的绝缘层以暴露出SiP形式的半导体器件的突起(突起电极)的结构，其中半导体芯片埋入到绝缘膜中。该半导体器件中，可不通过光刻工艺步骤来精细制造半导体芯片的衬垫电极，且其连接到上布线层。
接下来，将描述根据该实施例的半导体器件的制造方法。
可与第一实施例类似地形成埋入到绝缘层中的半导体芯片(1c和1d)。
然而，从晶片级的背面侧研磨该芯片，且将其厚度(t3和t4)的每一个都降低到几个10μm。
随后，如图12A中所示，在表面上形成有绝缘膜21如氧化硅的晶片中的基板20w上，识别在基板20w上完成的对准标记，以通过热压接合使用管芯粘附膜17面向上地安装由此形成的两个半导体芯片(1c和1d)。
随后，如图12B中所示，例如，遍及半导体芯片(1c和1d)表面上方通过印刷或模塑来涂敷非光敏树脂材料或者环氧树脂、丙烯酸、苯酚和聚酰亚胺的光敏树脂材料，并形成第一绝缘层22a。
随后，如图12C中所示，例如，从顶表面抛光第一绝缘层22a，直到暴露出突起(16c和16d)的顶部。
例如，抛光条件是使用#600的转轮的3500rpm的主轴旋转数目。
可与第一实施例的那些相似地进行在此之后的工艺步骤。
根据该实施例的半导体器件的制造方法，在半导体芯片埋入到绝缘膜中的SiP形式的半导体器件的制造方法中，抛光埋入了半导体芯片的绝缘层以暴露出突出电极。通过该方法，可不通过光刻工艺步骤来精细制造半导体芯片的衬垫电极，并将其连接到上布线层。
在此，由于将半导体芯片(1c和1d)的厚降低到约10μm，因此即使对于单次涂敷来涂敷光敏树脂材料，形成第一绝缘层也不会有问题。事实上，不将光线施加到第一绝缘层上，并通过抛光暴露出突起的顶部。因此，与第一实施例类似，可用非光敏树脂材料形成第一绝缘层。
第三实施例
图13示出了描述出根据本实施例的半导体器件的示意性截面图。
其基本上与根据第一实施例的半导体器件相同。与第一实施例不同在于将单个半导体芯片1e埋入到绝缘层中。与第一实施例相同，在半导体芯片1e的结构中，在半导体主体10e的表面上形成衬垫电极11e。形成保护绝缘膜12e，以形成用于衬垫电极11e的开口。在保护绝缘膜12e上方，以与保护绝缘膜12e的图形相同的图形形成树脂绝缘膜13e，以形成用于衬垫电极11e的开口。在形成于保护绝缘膜12e和树脂绝缘膜13e中的开口中，以预定高度形成突起(突起电极16e)，其连接到衬垫电极11e。在图中省略了籽晶层，其形成于在衬垫电极11e和突起16e之间的界面上。
根据该实施例的半导体器件除了上述内容之外与第一实施例的那些相同。
例如半导体芯片1e的半导体主体10e的厚度降低到约几个100μm或几个10μm。
根据该实施例的半导体器件具有在SiP形式的半导体器件中抛光埋入半导体芯片的绝缘层以暴露出突起(突起电极)的结构，其中半导体芯片埋入在绝缘膜中。该半导体器件中，可不通过光刻工艺步骤来精细制作半导体芯片的衬垫电极，且其连接到上布线层。
可与第一实施例相类似地通过建立将被安装的单个半导体芯片来实施根据该实施例的半导体器件的制造方法。
根据该实施例的半导体器件的制造方法，在SiP形式的半导体器件的制造方法中，半导体芯片埋入在绝缘膜中，抛光埋入了半导体芯片的绝缘膜以暴露出突出电极。通过该方法，可不通过光刻工艺步骤来精细制造半导体芯片的衬垫电极，并将其连接到上布线层。
根据该实施例的半导体器件及其制造方法，可发挥以下优点：
(1)可以不降低将被埋入的半导体芯片的厚度来执行芯片埋入的晶片级SiP。
(2)对于执行埋入的树脂不一定使用昂贵的光敏树脂，并可以采用廉价的非光敏树脂。
(3)即使将被埋入的半导体芯片的厚度很厚，该器件和方法也能够降低厚度而不增加SiP的总厚度。例如，根据电特性测试，在市场上提供400μm厚的晶片。一些半导体晶片和芯片具有约400μm的厚度，且其以晶片或芯片的形式分配到市场中。即使在从该半导体芯片或半导体晶片获得的芯片用于SiP的情况下，实际上也能使用该芯片。
本发明的实施例不限于上述内容。
例如，可在基板上形成电子电路。在这种情况下，形成将埋入到绝缘层中的布线，以连接到基板。
对于用于埋入半导体芯片的树脂绝缘层的材料，可如上所述地使用非光敏树脂材料，但是也可以使用光敏树脂材料。
除此之外，在不脱离本发明实施例的教导的范围内可作出各种修改。
根据本发明实施例的半导体器件适合于系统封装形式的半导体器件。
此外，根据本发明实施例的半导体器件的制造方法可适合于系统封装形式的半导体器件的制造方法。
本领域技术人员应当理解，根据在附属的权利要求或其等价物的范围之内的设计需要和其它因素，作出的各种修改组合、子组合和变化。

Claims (6)

1.一种半导体器件，将其封装成包括设置了电子电路的半导体，该半导体器件包括：
基板；
半导体芯片，其具有形成有电子电路的半导体主体、形成于半导体主体上的衬垫电极以及连接到衬垫电极并从半导体主体表面突出的突出电极，其中半导体芯片从表面的背面侧安装在基板上以在其上形成突起电极；和
绝缘层，该绝缘层被形成为其中埋入有半导体芯片并从该绝缘层的顶表面将其抛光至暴露出突起电极的顶部的高度，其中
作为半导体芯片，将多个半导体芯片埋入到绝缘层中，多个半导体芯片的厚度可以不同，并且其中以在具有不同厚度的多个半导体芯片当中，厚度和突起电极的高度的总高度近似相等的方式形成突起电极。
2.根据权利要求1的半导体器件，其中在绝缘层上方，形成连接到突起电极的上布线层，并形成在其中埋入上布线层的上绝缘层。
3.根据权利要求1的半导体器件，其中绝缘层由非光敏树脂形成。
4.一种半导体器件的制造方法，将该半导体器件封装成包括设置了电子电路的半导体，该制造方法包括步骤：
将半导体芯片安装在基板上，该半导体芯片具有形成有电子电路的半导体主体、形成于半导体主体上的衬垫电极以及连接到衬垫电极并从半导体主体表面突出的突起电极，其中从表面的背面侧将半导体芯片安装到基板上以在其上形成突起电极；
形成绝缘层，同时将半导体芯片埋入其中；以及
从该绝缘层的顶表面抛光该绝缘层至暴露出突起电极的顶部的高度，其中在安装半导体芯片的步骤中安装多个半导体芯片，在形成绝缘层的步骤中埋入多个半导体芯片，和在抛光绝缘层的步骤中抛光绝缘层至暴露出多个半导体芯片的突起电极的顶部的高度，并且其中将具有不同厚度的多个半导体芯片用作多个半导体芯片，并且其中作为多个半导体芯片，使用其中以在具有不同厚度的多个半导体芯片当中，厚度和突起电极的高度的总高度近似相等的方式形成突起电极的多个半导体芯片。
5.根据权利要求4的半导体器件的制造方法，其中在从绝缘层的顶表面抛光该绝缘层之后，该方法还包括形成连接到突起电极的上布线层和在绝缘层上方形成埋入有上布线层的上绝缘层的步骤。
6.根据权利要求4的半导体器件的制造方法，其中在形成绝缘层的步骤中，绝缘层由非光敏树脂形成。
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