JP4182189B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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JP4182189B2
JP4182189B2 JP2003550280A JP2003550280A JP4182189B2 JP 4182189 B2 JP4182189 B2 JP 4182189B2 JP 2003550280 A JP2003550280 A JP 2003550280A JP 2003550280 A JP2003550280 A JP 2003550280A JP 4182189 B2 JP4182189 B2 JP 4182189B2
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terminal
semiconductor device
semiconductor chip
semiconductor
insulating film
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JPWO2003049184A1 (ja
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浩久 松木
喜孝 愛場
光孝 佐藤
九弘 岡本
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Description

技術分野
本発明は、半導体装置及びその製造方法に関し、より詳しくは、複数の半導体チップを有する半導体装置及びその製造方法に関する。
背景技術
次世代の携帯電話やモバイルＰＣを含む携帯情報端末機については、小型・軽量・薄型化の向上がキーポイントとなっている。従って、今後高い成長が予想される携帯情報端末機の技術競争力を高めるためには、さらなる小型・軽量・薄型化を実現できる高密度実装技術の開発が重要である。
高密度実装技術としてはフリップ・チップ実装、マルチ・チップ・モジュールや積層基板など種々の技術が存在する。さらに、パッケージに複数の機能を盛り込みたいというニーズから半導体チップを積層化した構造のチップ・サイズ・パッケージ（ＣＳＰ）の技術開発が進み、さらに、インターポーザ基板を用いないウェハレベルＣＳＰが開発されている。
ウェハレベルＣＳＰは例えば図１に示すような構造を有している。
図１において、第１の半導体デバイスチップ１０１の上には配線１０２が形成され、その配線１０２の上には半田ボール１０３を介して第２の半導体デバイスチップ１０４が取り付けられている。その第２の半導体デバイスチップ１０４は、第１の半導体デバイスチップ１０１よりも小さい。
また、第１の半導体デバイスチップ１０４上の配線１０２のうち、第２の半導体デバイスチップ１０４の周辺領域には、ピン状の端子（ビア）１０５が接続されている。さらに、第１の半導体デバイスチップ１０１の上面では、第２の半導体デバイスチップを１０４封止するための封止樹脂１０６が端子１０５の上端が露出する程度の厚さに形成されている。その端子１０５の上端には半田ボール１０７が接続されている。
しかし、図１に示した端子１０５は配線１０２の上にメッキ法によって形成されるので、端子１０５の形成に時間がかかり、ＣＳＰ形成のスループットが悪くなる。
また、端子１０５の形成領域は第２の半導体デバイスチップ１０４の周辺に限定されるので、端子１０５の数の増加は望めない。
発明の開示
本発明の目的は、複数の半導体チップの積層構造において外部端子の形成領域を広げるとともに、外部端子を容易に形成できる半導体装置を提供することにある。
上記した課題は、一面に第１端子を有する第１半導体チップと、前記第１半導体チップより大きく、前記第１半導体チップが重ねられ且つ一面に第２端子を有する第２半導体チップと、前記第２半導体チップ上に形成されて前記第１半導体チップを覆う絶縁膜と、前記絶縁膜に形成される複数のホールと、前記ホールの内周面及び底面に膜状に形成され且つ前記第１端子と前記第２端子の少なくとも一方に電気的に接続される導電性のビアと、前記ホール内において、内周面に形成された前記導電性のビアよりさらに内面に形成された絶縁層と、前記絶縁膜の上面上に形成された第１配線パターンと、前記第１配線パターンの上に形成された外部端子とを有する半導体装置によって解決される。
本発明によれば、大きさの異なる第１及び第２半導体チップを積層した構造の半導体装置において、第２半導体チップの上に第１半導体チップを覆う絶縁膜を形成し、絶縁膜にホールを形成し、ホールの中に膜状のビアを形成し、絶縁膜上に配線パターンを形成している。
従って、ホールを完全に充填せずに膜状のビアを形成したので、ビアを短時間で形成することができ、しかも配線パターンとビアを同じ導電膜によって構成することができて膜の形成工程を減らすことができる。
また、絶縁膜上の配線パターンを第１半導体チップの上方に引き出してその上に外部端子を形成すると、絶縁膜上での複数の外部端子の狭ピッチ化を抑制でき、しかも外部端子の数を増やすことができる。
ホール内でビアを絶縁膜で覆うことによりビアの腐食が防止される。また、絶縁膜上の第１配線パターンのうち外部端子と接続する部分を除いて別の絶縁膜で覆うことにより、第１配線パターンのマイグレーションショートや腐食は防止される。
ところで、第１半導体チップの第１端子が形成される回路面を、第２半導体チップの第２端子が形成される回路面に対してフェースアップ、フェースダウンで配置するにかかわらず、同じ技術で積層ウェハレベルパッケージを作成でき、しかも、フェースアップ、フェースダウンの使い分けができて、種々の機能を持った半導体デバイスの重ね合わせが可能であるために有用である。
また、第１及び第２半導体チップの上方に第１配線パターンがあるために、外部端子を自由な位置に形成でき、多ピン構造に対応できる。
さらに、上記したような配線パターンとビアを有する絶縁膜を多層化することや、上記した構造を重ねることにより半導体チップの複数搭載が可能になる。
発明の実施をするための最良の形態
以下に本発明の実施形態を図面に基づいて説明する。
（第１の実施の形態）
図２〜図５は、本発明の第１実施形態に係るマルチップパッケージ（ＭＣＰ（ｍｕｌｔｉ ｃｈｉｐ ｐａｃｋａｇｅ））の形成工程を示す断面図である。
まず、図２（ａ）に示すように複数のデバイス領域Ａにそれぞれ第１の半導体回路（不図示）が形成された半導体ウェハ１を用意する。半導体ウェハ１は、図６（ａ）の部分拡大図に示すように、その上面に保護絶縁膜２を有し、その保護絶縁膜２には半導体デバイスの内部配線（不図示）に電気的に接続される第１の端子（導電性パッド）３を露出する開口２ａが形成されている。第１の端子３は、アルミニウム、銅などで形成されている。
なお、半導体ウェハ１は、例えばシリコンウェハであって、後の工程で第１の半導体回路毎に切断されてデバイス領域Ａ単位に分割される。
続いて、図２（ｂ）に示すように、保護絶縁膜２と第１の端子３の上にチタンとニッケルの二層構造の金属膜を０．５μｍ程度の厚さに形成し、さらに、その金属膜をフォトリソグラフィー法によりパターニングして第１の再配線パターン４を形成する。この第１の再配線パターン４は、第１の端子３の上から保護絶縁膜２上に引き出される導電パターンである。
その後に、図６（ｂ）に示すように、第２の半導体回路（不図示）が形成された第１の半導体デバイスチップ５を用意する。第１の半導体デバイスチップ５は、半導体ウェハ１のデバイス領域Ａよりも小さい例えばシリコンチップであり、その上面に保護絶縁膜６を有している。保護絶縁膜６には、第１の半導体デバイスチップ５内部の配線（不図示）に接続される第２の端子７を露出する開口６ａが形成されている。また、その保護絶縁膜６上には第２の端子７上から引き出される第２の再配線パターン８が形成されている。
そして、図２（ｃ）に示すように、第１の半導体デバイスチップ５の下面をダイボンディング剤（接着剤）９を介して半導体ウェハ１の半導体デバイス領域Ａの中央にボンディングする。
次に、図３（ａ）に示すように、エポキシ、ポリイミドのような樹脂絶縁層１０を半導体ウェハ１上面上で第１の半導体チップ５よりも１０〜２０μｍ程度高くなるように形成する。これにより、第１の半導体チップ５は樹脂絶縁膜１０により覆われる。
樹脂絶縁層１０は、半導体ウェハ１の上にスピン塗布、印刷、ラミネート法などにより形成される。例えば、ラミネート法を採用する場合には樹脂絶縁層の膜厚などを十分調整し、第１の半導体デバイスチップ５上とその周囲に気泡が入らないように工夫する必要がある。
また、樹脂絶縁層１０の材料の特性により樹脂絶縁層１０表面の平坦化が困難な場合には、樹脂絶縁層１０を半導体ウェハ１上に形成した後に、バックグラインド技術を用いた機械的な研磨、化学機械研磨（ＣＭＰ）又はポリッシングなどによって樹脂絶縁層１０の上面を平坦化することが望ましい。例えばエポキシレジンやポリイミドからなる樹脂絶縁層１０を半導体ウェハ１上に例えば１２０〜１５０μｍの厚さに形成した後に、樹脂絶縁層１０の上面を機械的研磨法又は化学機械研磨法により平坦化する。
次に、図３（ｂ）に示すように、樹脂絶縁層１０のうち、第１の再配線パターン４と第２の再配線パターン８の上にそれぞれ直径８０〜１００μｍのビアホール（貫通孔）１０ａを形成する。
樹脂膜絶縁層１０として感光性樹脂材料を選択する場合には、半導体ウェハ１上の樹脂絶縁層１０の形成を非感光光の環境下で行った後に、ビアホール形成用の露光マスクを用いて樹脂絶縁層１０を露光し、さらに炭酸ナトリウム（ＮａＣＯ３）などの無機アルカリ液を用いて現像することによりビアホール１０ａが容易に形成される。
このような露光、現像によってビアホール１０ａを形成すると、ビアホール１０ａは上部が広くなるようなテーパ形状になるので、後述するビアホール１０ａ内での各種の処理が容易になる。この場合、ビアホール１０ａの下の第１の端子３が第１の再配線パターン４に覆われているので、第１の端子３の無機アルカリ液による腐食が防止される。
一方、樹脂絶縁層１０の構成材料として非感光性材料を選択する場合には、レーザ等の高エネルギーを樹脂絶縁層１０の所定位置に照射することによりビアホール１０ａを形成することが適当である。ビアホール１０ａをレーザにより形成する場合には、ビアホール１０ａの下では第１の端子３や保護絶縁膜２が硬質金属の第１の再配線パターン４に覆われているので、アルミニウム、銅などの比較的軟質の導電材よりなる第１の端子３やその周辺の保護絶縁膜２がレーザ照射によって除去されたり劣化するおそれはなくなる。
なお、ビアホール１０ａはドリリングで形成されることもある。
次に、図３（ｃ）に示すように、樹脂絶縁層１０の表面を希釈溶剤により活性化し、その後に樹脂絶縁層１０の上面とビアホール１０ａの内周面及び底面の上に金属膜１１、例えば銅膜を無電解メッキによって０．５〜１．０μｍの厚さに形成する。その程度の厚さの金属膜１１は、図１に示した外部端子１０５をメッキにより形成する場合に比べて極めて短い時間で形成される。この場合、金属膜１１は、ビアホール１０ａ内で第１の再配線パターン４の上に接続される。なお、金属膜は、多層構造であってもよい。
なお、金属膜１１を３〜５μｍ程度の厚さに形成したい場合には、無電解メッキ法によって一旦薄く形成した後に、電解メッキ法によって厚く形成する方法を採用してもよい。また、樹脂絶縁層１０がエポキシレジンやポリイミドから構成される場合には、樹脂絶縁層１０の上面とビアホール１０ａ内面の上での無電解メッキ法による金属膜１１の成長は容易である。
この後に、図４（ａ）に示すように、金属膜１１をフォトリソグラフィー法によりパターニングすることにより、ビアホール１０ａ内の金属膜１１をビア１１ａとして残すとともに、樹脂絶縁層１０の上面の金属膜１１のパターンを第３の再配線パターン１１ｂとして適用する。これにより、樹脂絶縁層１０上の複数の第３の再配線パターン１１ｂは、それぞれビア１１ａ及び第２の再配線パターン８を介して第１の半導体デバイスチップ５の端子７に電気的に接続され、且つ、ビア１１ａ及び第１の再配線パターン４を介して半導体ウェハ１の端子３に電気的に接続される。また、第１の半導体デバイスチップ５の端子６は、ビア１１ａと第３の再配線パターン１１ｂを介して半導体ウェハ１の端子３に電気的に接続されている。なお、ビア１１ａは第３の再配線１１ｂに繋がっているが、繋がっていない部分もあってもよい。
次に、図４（ｂ）に示すように、非感光性のエポキシ樹脂を樹脂絶縁層１０の開口部１０ａ内にスキージを用いたり或いは印刷法により埋め込むことにより、埋込絶縁層１２を形成する。これにより、開口部１０ａ内でビア１１ａは埋込絶縁層１２により覆われる。
続いて、図５（ａ）に示すように、感光性エポキシ樹脂又は感光性ノボラック樹脂などからなる絶縁性の樹脂カバー膜１３を、樹脂絶縁層１０、第３の再配線パターン１１ｂ及び埋込絶縁層１２の上に形成する。樹脂カバー膜１３は、スキージを用いたり或いは印刷法により非感光光の雰囲気中で樹脂絶縁層１０上に塗布される。樹脂カバー膜１３は、第３の再配線パターン１１ｂの腐食を防止し、第３の再配線パターン１１ｂのマイグレーションショートを防止する。
さらに、樹脂カバー膜１３を露光、現像することによりパターニングして、第３の再配線パターン１１ｂのコンタクト部を露出する開口１３ａを形成する。
その後に、図５（ｂ）に示すように、半田バンプなどの外部端子１４を樹脂カバー膜１３の開口１３ａを通して第３の再配線パターン１１ｂに接続する。この場合、外部端子１４は、樹脂カバー膜１３の開口１３ａの中に形成されるので、位置ズレが防止され、或いは位置決めが容易となる。この場合、露光、現像によれば、開口１３ａは、上が広がるテーパー形状になるので、第３の再配線パターン１１ｂ上のボール状の外部端子１４の位置決めと接続は容易である。
この後に、図５（ｂ）に示した半導体ウェハ１の半導体回路領域Ａ同士の境界をダイシングすることにより半導体ウェハを複数の第２の半導体デバイスチップ１ａに分割することにより、図７に示すようなＭＣＰ型の半導体装置が複数形成される。この場合、第２の半導体デバイスチップ１ａの側面は樹脂絶縁層１０に覆われずに露出する。
なお、半導体ウェハ１を分割する前に、その下面を機械研磨法又は化学機械研磨法により研削してもよい。
以上のような半導体装置によれば、第２の半導体デバイスチップ１ａの上面に形成された樹脂絶縁層１０のうち、第１の半導体チップ５の周囲にビアホール１０ａを形成するととも、そのビアホール１０ａの内周面及び底面に形成された導電膜をビア１１ａとして用いるとともに、樹脂絶縁層１０の上面にその導電膜を再配線パターン１１ｂとして用いるようにしている。
従って、ビアホール１０ａ内に形成しようとするビア１１ａの形成が、金属膜１１の形成という工程によっているので、ビアホールを完全に埋め込むような従来の構造に比べて短時間で形成することができる。
また、ビア１１ａを構成する金属膜１１のうち樹脂絶縁層１０の上面上に形成された部分は、パターニングされて再配線パターン１１ｂとして使用されている。このため、第１の半導体デバイスチップ５の上方にも外部端子１４が形成され、外部端子１４の数を従来よりも増やすことができ、しかも、外部端子１４の狭ピッチ化が緩和される。
さらに、ビア１１ａと再配線パターン１１ｂを双方とも同じ金属膜１１から形成しているので、それぞれを別々に形成する場合に比べてスループットが改善される。
なお、上記した例では、半導体ウェハ１の上に第１の半導体デバイスチップ５を接着し、その後に、樹脂絶縁層１０、ビア１１ａ、第３の再配線パターン１１ｂ、保護カバー膜１３、外部端子１４を形成した後に半導体ウェハ１を分割している。しかし、半導体ウェハ１を複数の第２の半導体デバイスチップ１ａに分割した後に、第２の半導体チップ１ａの上に第２の半導体チップ５を接着し、その後に、樹脂絶縁層１０、ビア１１ａ、第３の再配線パターン１１ｂ、保護カバー膜１３、外部端子１４を形成してもよく、こによっても図７に示すと同じ構造の半導体装置が形成される。この場合には、第２の半導体デバイスチップ１ａの側面は樹脂膜１０で覆われる。
また、図８に示すように、樹脂絶縁層１０とビア１１ａと再配線パターン１１ｂを有する配線構造層を２層以上の多層構造としてもよく、この場合には、最上の樹脂絶縁層１０の上に保護カバー膜１３と外部端子１４が形成される。この場合、上下の再配線パターン１１ｂ同士は、高速信号処理に対応させて互いに交差するように配置される。このような多層配線構造は、以下に示す実施形態において採用してもよい。
（第２の実施の形態）
第１実施形態では、ビア１１ａと再配線パターン１１ｂを形成した後に、ビアホール１０ａ内に埋込絶縁層１２を形成し、その後に樹脂絶縁層１０上に樹脂カバー膜１３を形成している。しかし、埋込絶縁層１２と樹脂カバー膜１３を同時に形成してもよい。
例えば、図９（ａ）に示すように、感光性の樹脂膜１５、例えばエポキシ樹脂をビアホール１０ａ内と樹脂絶縁層１０上に同時に塗布した後に、樹脂膜１５を露光、現像して第３の再配線パターン１１ｂのコンタクト部を露出する開口１５ａを形成する。
その後に、図９（ｂ）に示すように、外部端子１４を樹脂膜１５の開口１５ａを通して再配線パターン１１ｂに接合する。
これによれば、ビアホール１０ａ内のエポキシ樹脂は埋込絶縁層として使用され、樹脂絶縁層１０上のエポキシ樹脂は樹脂カバー膜として使用され、埋込絶縁膜層と樹脂カバー膜を同時に形成でき、第１実施形態に比べて絶縁膜形成工程が減ることになる。
その後に、半導体回路領域Ａ同士の境界を切断することにより、図１０に示すような半導体装置が形成される。この場合、第２の半導体デバイスチップ１ａの側面は樹脂絶縁層１０に覆われずに露出する。
（第３の実施の形態）
第１実施形態に示した半導体ウェハ１の上に第１の再配線パターン３を形成しない場合には、以下のような工程を採用する。
まず、図１１（ａ），（ｂ）に示すように、半導体ウェハ１の上の保護絶縁膜２の開口２ａ内の端子３上に選択的にニッケルリン（ＮｉＰ）、ニッケル、金等よりなる被覆導電層１６を無電解メッキ法により３〜５μｍの厚さに形成する。
その後に、図１１（ｃ）に示すように、第１実施形態と同様な方法により半導体ウェハ１上に第１の半導体デバイスチップ５を取り付ける。第１の半導体デバイスチップ５として、その上面の保護絶縁膜６の第２の端子７上に、再配線パターンではなく、ＮｉＰの被覆導電膜１７が形成された構造のものが使用される。
続いて、図１２（ａ）に示すように、第１の半導体デバイスチップ５を覆うように樹脂絶縁層１０を半導体ウェハ１の上に形成する。樹脂絶縁層１０の形成とその平坦化については、第１実施形態と同様な方法を採用する。
さらに、図１２（ｂ）に示すように、樹脂絶縁層１０のうち第１の半導体デバイスチップ５上と半導体ウェハ１のそれぞれの端子３，７上の被覆導電層１６，１７の上にビアホール１０ａを形成する。
ビアホール１０ａは、第１実施形態に示したと同様な方法を採用する。即ち、樹脂絶縁層１０を感光性材料で構成する場合には感光及び現像により形成し、または、非感光性材料で構成する場合にはレーザ照射により形成する。この場合、ビアホール１０ａの下方で銅やアルミニウムから形成された端子３，７はそれぞれ被覆導電層１６，１７により保護されて、現像液やレーザに直接曝されることがなく、現像やレーザによる劣化が防止される。なお、ビアホール１０ａはドリリングにより形成されてもよい。
この後に、図１３（ａ）に示すように、第１実施形態と同様な工程を経て、ビアホール１０ａ内にビア１１ａを、樹脂絶縁層１０上に再配線パターン１１ｂをそれぞれ形成する。さらに、図１３（ｂ）に示すように、埋込絶縁膜１２、カバー絶縁膜１３、外部端子１４を形成する。なお、埋込絶縁膜１２、カバー絶縁膜１３については、第２実施形態に示したように同じ樹脂膜１５から同時に形成してもよい。
その後に、デバイス領域Ａ毎に半導体ウェハ１を複数の第２の半導体デバイスチップ１ａに分割すると、図１４に示すような半導体装置が形成される。この場合、第２の半導体デバイスチップ１ａの側面は樹脂絶縁層１０に覆われずに露出する。
以上な工程によれば、樹脂絶縁層１０にビアホール１０ａを形成するために使用される無機アルカリの端子３，７への供給を被覆導電層１６，１７によって防止でき、又は、ビアホール１０ａ形成されるために使用されるレーザの端子３，７への照射を被覆導電層１６，１７によって防止することができ、端子３，７の劣化が防止される。
なお、第１の半導体チップ５と半導体ウェハ１のいずれか一方の上に再配線パターンを形成してもよいが、再配線パターンで覆われない端子３，７には被覆導電１６，１７で覆う必要がある。
（第４の実施の形態）
図６（ｂ）に示した第１の半導体デバイスチップ５は、樹脂絶縁層１０の上面の再配線パターン１１ｂを介さずに、ワイヤーや半田ボールを介して半導体ウェハ１の端子３に接続されるようにしてもよい。
例えば、図１５に示すように、第１の半導体デバイスチップ５の端子７上に再配線パターンを形成せずにニッケルリンの被覆導電層１７を形成し、その被覆導電層１７と半導体ウェハ（第２の半導体デバイスチップ１ａ）上の再配線パターン４とをワイヤボンディングにより金（導電性）ワイヤ２１によって接続する構造を採用してもよい。この場合には、第１の半導体デバイスチップ５の上で樹脂絶縁層１０にはビアホール１０ａが形成されない。
また、図１６に示すように、第１の半導体デバイスチップ５の端子７上に半田バンプ（外部端子）２２を接続し、その半田バンプ２２を半導体ウェハ１（第２の半導体デバイスチップ１ａ）の上の再配線パターン４上に接続するようにしてもよい。この場合にも、第１の半導体デバイスチップ５の上では樹脂絶縁層１０内にビアホール１０ａが形成されない。
図１５、図１６に示した樹脂絶縁層１０のうち第１の半導体デバイスチップ５の上方にはビアホール１０ａは形成されないが、樹脂絶縁層１０上には再配線パターン１１ｂが形成されてその上に外部端子１４が接合される。
従って、樹脂絶縁層１０上の外部端子１４の形成領域は従来よりも広くなり、外部端子１４の数を従来よりも増やすことができ、しかも、外部端子１４の狭ピッチ化が緩和される。
以上述べたように本発明によれば、大きさの異なる第１及び第２半導体チップを積層した構造の半導体装置において、第２半導体チップの上に第１半導体チップを覆う絶縁膜を形成し、絶縁膜にホールを形成し、ホールの中に膜状のビアを形成し、絶縁膜上に配線パターンを形成したので、ビアを短時間で形成することができ、しかも配線パターンとビアを同じ導電膜によって構成することができて膜の形成工程を減らすことができる。
また、絶縁膜上の配線パターンを第１半導体チップの上に引き出してその上に外部端子を形成したので、絶縁膜上での複数の外部端子の狭ピッチ化を抑制でき、しかも外部端子の数を増やすことができる。
さらに、ホール内のビアを絶縁膜で覆うことによりビアの腐食を防止でき、また、絶縁膜上の第１配線パターンのうち外部端子と接続する部分を除いて別の絶縁膜で覆うことにより、第１配線パターンのマイグレーションショート、腐食を防止することができる。
【図面の簡単な説明】
図１は、従来構造の半導体装置を示す断面図であり；
図２（ａ）〜（ｃ）は、本発明の第１実施形態に係る半導体装置の製造工程（その１）であり；
図３（ａ）〜（ｃ）は、本発明の第１実施形態に係る半導体装置の製造工程（その２）であり；
図４（ａ），（ｂ）は、本発明の第１実施形態に係る半導体装置の製造工程（その３）であり；
図５（ａ），（ｂ）は、本発明の第１実施形態に係る半導体装置の製造工程（その４）であり；
図６（ａ）は、本発明の第１実施形態に係る半導体装置を構成する半導体ウェハを示す断面図であり；
図６（ｂ）は、本発明の第１実施形態に係る半導体装置を構成する半導体デバイスチップを示す断面図であり；
図７は、本発明の第１実施形態に係る半導体装置を示す断面図であり；
図８は、本発明の第１実施形態に係る多層配線構造を有する半導体装置の断面図であり；
図９（ａ），（ｂ）は、本発明の第２実施形態に係る半導体装置の製造工程を示す断面図（その１）であり；
図１０は、本発明の第２実施形態に係る半導体装置を示す断面図であり；
図１１（ａ）〜（ｃ）は、本発明の第３実施形態に係る半導体装置の製造工程を示す断面図（その１）であり；
図１２（ａ），（ｂ）は、本発明の第３実施形態に係る半導体装置の製造工程を示す断面図（その２）であり；
図１３（ａ），（ｂ）は、本発明の第３実施形態に係る半導体装置の製造工程を示す断面図（その３）であり；
図１４は、本発明の第３実施形態に係る半導体装置を示す断面図であり；
図１５は、本発明の第４実施形態に係る第１半導体装置を示す断面図であり；
そして
図１６は、本発明の第４実施形態に係る第２半導体装置を示す断面図である。

Claims (19)

  1. 一面に第１端子を有する第１半導体チップと、
    前記第１半導体チップより大きく、前記第１半導体チップが重ねられ且つ一面に第２端子を有する第２半導体チップと、
    前記第２半導体チップ上に形成されて前記第１半導体チップを覆う絶縁膜と、
    前記絶縁膜に形成される複数のホールと、
    前記ホールの内周面及び底面に膜状に形成され且つ前記第１端子と前記第２端子の少なくとも一方に電気的に接続される導電性のビアと、
    前記ホール内において、内周面に形成された前記導電性のビアよりさらに内面に形成された絶縁層と、
    前記絶縁膜の上面上に形成された第１配線パターンと、
    前記第１配線パターンの上に形成された外部端子と
    を有することを特徴とする半導体装置。
  2. 前記第１端子と前記第２端子を同じ向きにして前記第１半導体チップが前記第２半導体チップ上に載置されることを特徴とする請求項１に記載の半導体装置。
  3. 前記第１半導体チップの前記第１端子は前記第２半導体チップの前記第２端子と導電性ワイヤを介して接続されていることを特徴とする請求項２に記載の半導体装置。
  4. 前記第１半導体チップの前記第１端子は、前記第１配線パターン、前記ビアを介して前記第２半導体チップの前記第２端子に電気的に接続されていることを特徴とする請求項２又は請求項３に記載の半導体装置。
  5. 前記第１半導体チップは接着剤を介して前記第２半導体チップに搭載されていることを特徴とする請求項２〜請求項４のいずれか１項に記載の半導体装置。
  6. 前記第１半導体チップと前記第２半導体チップは、前記第１端子を有する面と前記第２端子を有する面を互いに対向させて重なっていることを特徴とする請求項１に記載の半導体装置。
  7. 前記第２半導体チップ上では前記第２端子に電気的に接続される第３配線パターンが形成され、さらに該第３配線パターンには前記第１半導体チップの前記第１端子が導電材を介して接続されることを特徴とする請求項６に記載の半導体装置。
  8. 前記第１端子と前記第２端子の少なくとも一方の上には第２配線パターンが形成され、前記ビアは該第２配線パターンの上に形成されることを特徴とする請求項１に記載の半導体装置。
  9. 前記第１端子、前記第２端子の少なくとも一方は被覆導電層を介して前記ビアに接続されることを特徴とする請求項１〜請求項８のいずれか１項に記載の半導体装置。
  10. 前記ビアと前記第１配線パターンは接続されていることを特徴とする請求項１〜請求項９のいずれか１項に記載の半導体装置。
  11. 前記第１配線パターンは、前記外部端子との接続部分を除いて前記絶縁膜上でカバー絶縁膜により覆われていることを特徴とする請求項１〜請求項１０のいずれか１項に記載の半導体装置。
  12. 前記絶縁層は、前記ホール内において前記ビアの上と、さらに前記第１配線パターンのうちの前記外部端子との接続部分を除いた領域の上を覆うように形成されていることを特徴とする請求項１〜請求項１０のいずれか１項に記載の半導体装置。
  13. 前記第２半導体チップの側面は露出していることを特徴とする請求項１〜請求項１２のいずれか１項に記載の半導体装置。
  14. 第１端子を有する第１半導体チップをこれより大きく且つ第２端子を持つ半導体基板上に取り付ける工程と、
    前記第１半導体チップを覆う絶縁膜を前記半導体基板上に形成する工程と、
    前記絶縁膜にホールを形成する工程と、
    前記ホール内周面及び底面上、及び前記絶縁膜上に導電膜を形成する工程と、
    前記導電膜をパターニングして前記ホール内にはビアとして残し、前記絶縁膜上では配線を形成する工程と、
    前記ホール内において、内周面に形成された前記導電膜よりさらに内面に絶縁層を形成する工程と、
    前記第１配線の上に外部端子を接続する工程と
    を有することを特徴とする半導体装置の製造方法。
  15. 前記第１端子と前記第２端子の少なくとも一方の上に金属パターンを形成し、該金属パターンの上に前記ホールを形成することを特徴とする請求項１４に記載の半導体装置の製造方法。
  16. 前記金属パターンは、配線パターンであることを特徴とする請求項１５に記載の半導体装置の製造方法。
  17. 前記ホールの形成は、レーザ照射法、フォトリソグラフィー法、ドリリング法のいずれかで形成されることを特徴とする請求項１４〜請求項１６のいずれか１項に記載の半導体装置の製造方法。
  18. 前記導電膜は、メッキ法により形成された金属膜であることを特徴とする請求項１４〜請求項１７のいずれか１項に記載の半導体装置の製造方法。
  19. 前記絶縁膜はエポキシ樹脂又はポリイミド樹脂であることを特徴とする請求項１４〜請求項１８のいずれか１項に記載の半導体装置の製造方法。
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