TW201942984A - 形成半導體封裝的方法 - Google Patents
形成半導體封裝的方法 Download PDFInfo
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- TW201942984A TW201942984A TW107136331A TW107136331A TW201942984A TW 201942984 A TW201942984 A TW 201942984A TW 107136331 A TW107136331 A TW 107136331A TW 107136331 A TW107136331 A TW 107136331A TW 201942984 A TW201942984 A TW 201942984A
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- Prior art keywords
- dielectric layer
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- photoresist
- integrated circuit
- die
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Classifications
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Abstract
一種形成半導體封裝的方法。在實施例中,所述方法可包括:將積體電路晶粒及穿孔包封在模塑化合物中,所述積體電路晶粒具有晶粒連接件;在所述模塑化合物之上沉積第一介電層;圖案化出第一開口,所述第一開口穿過所述第一介電層且暴露出所述積體電路晶粒的晶粒連接件;將所述第一介電層平坦化;在所述第一介電層之上及所述第一開口中沉積第一晶種層;以及在所述第一晶種層上鍍覆延伸穿過所述第一介電層的第一導通孔。
Description
本發明的實施例是有關於一種形成半導體封裝的方法。
由於各種電子元件(例如,電晶體、二極體、電阻器、電容器等)的整合密度的持續改善,半導體行業已經歷快速增長。在很大程度上,整合密度的改善來自於最小特徵大小(feature size)的不斷地減小,這允許更多的元件能夠整合到給定區域內。隨著對縮小電子裝置的需求的增加,亟需更小且更具創造性的半導體晶粒的封裝技術。這種封裝系統的一個實例是疊層封裝(Package-on-Package,PoP)技術。在PoP裝置中,頂部半導體封裝被堆疊在底部半導體封裝的頂部上,以提供高整合水準及元件密度。PoP技術一般能夠生產功能性得到增強且在印刷電路板(printed circuit board,PCB)上佔用空間小的半導體裝置。
本發明的一實施例公開一種形成半導體封裝的方法,其特徵在於,包括:將積體電路晶粒及穿孔包封在模塑化合物中,所述積體電路晶粒具有晶粒連接件;將第一介電層沉積在所述模塑化合物之上;圖案化出第一開口,所述第一開口穿過所述第一介電層且暴露出所述積體電路晶粒的所述晶粒連接件;將所述第一介電層平坦化;將第一晶種層沉積在所述第一介電層之上及所述第一開口中;以及在所述第一晶種層上鍍覆延伸穿過所述第一介電層的第一導通孔。
本發明的一實施例公開一種形成半導體封裝的方法,其特徵在於,包括:將多個積體電路晶粒包封在模塑化合物中,所述多個積體電路晶粒中的每一者設置在晶圓上,所述多個積體電路晶粒中的每一者具有晶粒連接件;在所述模塑化合物及所述多個積體電路晶粒之上沉積第一介電層;將所述第一介電層的整個上表面同時曝光於第一經圖案化能量源;對所述第一介電層進行顯影以形成暴露出所述多個積體電路晶粒的第一多個開口;將所述第一介電層平坦化;以及穿過所述第一介電層形成第一金屬化圖案,所述第一金屬化圖案接觸所述晶粒連接件。
本發明的一實施例公開一種半導體封裝,其特徵在於,包括:模塑化合物;積體電路晶粒,包封在所述模塑化合物中;穿孔,鄰近所述積體電路晶粒,所述模塑化合物在所述穿孔與所述積體電路晶粒之間延伸;以及重佈線結構,位於所述積體電路晶粒、所述模塑化合物及所述穿孔之上,所述重佈線結構電連接到所述積體電路晶粒及所述穿孔,所述重佈線結構包括:第一介電層,設置在所述模塑化合物之上;以及第一導電特徵,延伸穿過所述第一介電層,所述第一導電特徵無縫合。
以下公開內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述元件及配置形式的具體實例以簡化本公開內容。當然,這些僅為實例且不旨在進行限制。例如,以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本公開內容可能在各種實例中重複使用參考編號和/或字母。這種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“在...之下”、“下方”、“下部的”、“上方”、“上部的”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或其他取向),且本文中所用的空間相對性描述語可同樣相應地進行解釋。
本文所論述的實施例涉及重佈線結構及形成重佈線結構以用於各種半導體封裝中的方法。在一些實施例中,重佈線結構可包括介電層、金屬化圖案及通孔。可通過以下方式來形成重佈線結構:在半導體晶圓之上形成介電層,將介電層平坦化,在介電層之上形成光阻劑,使用對準光刻機(aligner)對半導體晶圓的整個表面上的光阻劑進行曝光,對光阻劑進行顯影以在光阻劑中形成開口,在開口中形成金屬化圖案及通孔,以及移除光阻劑。可重複此製程,直到形成具有期望結構及厚度的重佈線結構。
使用對準光刻機對光阻劑進行曝光使得晶圓的整個表面能夠被同時曝光。因此無需執行多次曝光,且在各曝光之間無縫合(stitching)。此會進一步防止多次曝光之間的重疊移位(overlay shift)。減小重疊移位意味著可形成具有更精細節距的重佈線結構。此外,將每一介電層平坦化會改善每一層及總體重佈線結構的平坦化程度(degree of planarization,DoP)。
圖1到圖18示出根據一些實施例的在形成半導體封裝200(未示於圖1到圖17中,但示於圖18中)的製程期間的中間步驟的剖視圖(圖6B示出俯視圖)。也可將半導體封裝200稱作整合扇出型(integrated fan-out,InFO)封裝。圖1示出載體基底100及在載體基底100上形成的釋放層102。還示出用於形成半導體封裝200的第一封裝區600及第二封裝區602。
載體基底100可為玻璃載體基底、陶瓷載體基底等。載體基底100可為晶圓,進而使得可在載體基底100上同時形成多個封裝。載體基底100可為圓形,且可具有300 mm、約450 mm、約200 mm的直徑或任何其他合適的直徑。釋放層102可由聚合物系材料形成,所述聚合物系材料可與載體基底100一起從將在後續步驟中形成的重疊結構被移除。在一些實施例中,釋放層102是在受熱時失去粘合性質的環氧系熱釋放材料,例如光熱轉換(light-to-heat-conversion,LTHC)釋放塗層。在其他實施例中,釋放層102可為紫外(ultra-violet,UV)膠,所述紫外膠在被曝光于紫外光時喪失其粘合性質。釋放層102可作為液體進行分配並進行固化,釋放層102可為被疊層到載體基底100上的疊層膜(laminate film),或可為類似物。釋放層102的頂表面可以是等高(leveled)且可具有高平坦性程度(degree of planarity)。
在釋放層102之上形成介電層104及金屬化圖案106(有時被稱為重佈線層或重佈線)。如圖1所示,在釋放層102上形成介電層104。介電層104的底表面可接觸釋放層102的頂表面。在一些實施例中,介電層104是由例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)等聚合物形成。在其他實施例中,介電層104是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)等;或者類似材料。通過例如旋轉塗布(spin coating)、化學氣相沉積(chemical vapor deposition,CVD)、疊層(laminating)、類似製程或其組合等任何可接受的沉積製程來形成介電層104。
在介電層104上形成金屬化圖案106。作為實例,可通過在介電層104之上形成晶種層(圖中未單獨示出)來形成金屬化圖案106。在一些實施例中,晶種層為金屬層,所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層之上的銅層。可利用例如物理氣相沉積(physical vapor deposition,PVD)等來形成晶種層。
接著在晶種層上形成光阻劑並對所述光阻劑進行圖案化。可通過旋轉塗布等來形成光阻劑且可將所述光阻劑曝光於經圖案化能量源(例如,經圖案化光源)並進行顯影來圖案化。光阻劑的圖案對應於金屬化圖案106。所述圖案化形成穿過光阻劑的開口以暴露出晶種層。
接著在光阻劑的開口中且在晶種層的被暴露部分上形成導電材料。可通過例如電鍍、無電鍍覆等鍍覆製程來形成所述導電材料。導電材料可包含例如銅、鈦、鎢、鋁等金屬。接著,可移除光阻劑以及晶種層的上面未形成導電材料的部分。可通過任何可接受的製程(例如,通過灰化製程、剝除製程等)來移除光阻劑。在實施例中,可使用氧等離子體來移除光阻劑。一旦光阻劑被移除,便會移除晶種層的被暴露部分。可通過例如濕式蝕刻製程、幹式蝕刻製程等任何可接受的蝕刻製程來移除晶種層的所述部分。導電材料與晶種層的剩餘部分一起形成金屬化圖案106。
在金屬化圖案106及介電層104上形成介電層108。在一些實施例中,介電層108是由聚合物形成,所述聚合物可為例如PBO、聚醯亞胺、BCB等感光性材料。在其他實施例中,介電層108是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃;或類似物。可通過旋轉塗布、疊層、化學氣相沉積、類似製程或其組合來形成介電層108。接著對介電層108進行圖案化以形成開口從而暴露出金屬化圖案106的一些部分。可通過以下任何可接受的製程對介電層108進行圖案化:例如當介電層108是由感光性材料形成時曝光於經圖案化能量源(例如,經圖案化光源))及顯影;通過使用例如各向異性蝕刻進行蝕刻;或類似方式。如以下將更詳細論述,可使用對準光刻機將介電層108曝光於經圖案化能量源,以使得不存在形成在介電層108中的開口的縫合或重疊移位。
可將介電層104及介電層108以及金屬化圖案106稱作背側重佈線結構(back-side redistribution structure)110。在一些實施例中,背側重佈線結構110可包括任何數目的介電層、金屬化圖案及通孔。可通過重複進行用於形成金屬化圖案106及介電層108的製程而在背側重佈線結構110中形成一個或多個額外的金屬化圖案及介電層。可在形成金屬化圖案期間通過在下伏介電層中形成的開口中形成金屬化圖案的晶種層及導電材料來形成通孔。所述通孔可因此對各種金屬化圖案進行內連及電耦合。
在圖2中,在背側重佈線結構110之上形成穿孔112。可通過在背側重佈線結構110(例如,介電層108及金屬化圖案106的被暴露部分)之上形成晶種層來形成穿孔112。在一些實施例中,晶種層為金屬層,所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層之上的銅層。可利用例如物理氣相沉積等來形成晶種層。在晶種層上形成光阻劑並對所述光阻劑進行圖案化。可通過旋轉塗布等來形成光阻劑且可將所述光阻劑曝光於經圖案化能量源(例如,經圖案化光源)並進行顯影來圖案化。如以下將更詳細論述,可使用對準光刻機將光阻劑曝光於經圖案化能量源,以使得不存在穿孔112的縫合或重疊移位。光阻劑的圖案對應于將形成的穿孔112。所述圖案化形成穿過光阻劑的開口以暴露出晶種層的一些部分。在光阻劑的開口中且在晶種層的被暴露部分上形成導電材料。可通過例如電鍍、無電鍍覆等鍍覆製程來形成所述導電材料。導電材料可包含例如銅、鈦、鎢、鋁等金屬。移除光阻劑以及晶種層的上面未形成導電材料的部分。可通過例如灰化製程、剝除製程等任何可接受的製程來移除光阻劑。在一些實施例中,可使用氧電漿來移除光阻劑。一旦光阻劑被移除,便通過任何可接受的蝕刻製程(例如通過濕式蝕刻、幹式蝕刻等)移除晶種層的被暴露部分。晶種層的剩餘部分與導電材料形成穿孔112。
在圖3中,通過粘合劑116將積體電路晶粒114粘合到介電層108。如圖3所示,可在第一封裝區600及第二封裝區602中的每一者中粘合一個積體電路晶粒114。在其他實施例中,可在每一區中粘合更多積體電路晶粒。舉例來說,在實施例中,可在每一區中粘合兩個或更多個積體電路晶粒114。積體電路晶粒114可為邏輯晶粒(例如,中央處理單元(central processing unit)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)晶粒等)、電力管理晶粒(例如,電力管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(radio frequency,RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system,MEMS)晶粒、信號處理晶粒(例如,數位信號處理(digital signal processing,DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end,AFE)晶粒)、類似的晶粒或其組合。此外,在一些實施例中,積體電路晶粒114可為不同大小(例如,不同高度和/或表面積),且在其他實施例中,積體電路晶粒114可為相同大小(例如,相同高度和/或表面積)。
在粘合到介電層108之前,可根據適用于在積體電路晶粒114中形成積體電路的製造製程對積體電路晶粒114進行處理。例如,積體電路晶粒114各自分別包括半導體基底118,例如經摻雜的或未經摻雜的矽或絕緣體上半導體(semiconductor-on-insulator,SOI)基底的主動層。半導體基底118可包含:其他半導體材料,例如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或者其組合。也可使用例如多層式基底或梯度基底(gradient substrate)等其他基底。可在半導體基底118中和/或半導體基底118上形成例如電晶體、二極體、電容器、電阻器等裝置且可通過由例如位於半導體基底118上的一個或多個介電層中的金屬化圖案所形成的內連線結構120將各所述裝置進行內連以形成積體電路。
積體電路晶粒114還可包括進行外部連接的襯墊122(例如鋁襯墊)。襯墊122位於可被稱為積體電路晶粒114的主動側的部位上。鈍化膜(passivation film)124位於積體電路晶粒114上且位於襯墊122的一些部分上。開口穿過鈍化膜124延伸到襯墊122。在穿過鈍化膜124的開口中形成例如導電柱(例如,包含例如銅等金屬)等晶粒連接件126(示於圖3中且以虛線示於後續圖中),且晶粒連接件126機械耦合及電耦合到相應襯墊。可通過例如電鍍或類似方法來形成晶粒連接件126。晶粒連接件126電耦合積體電路晶粒114的相應積體電路。
介電材料128位於積體電路晶粒114的主動側上,例如位於鈍化膜124及晶粒連接件126上。介電材料128橫向地包封晶粒連接件126,且介電材料128在橫向與對應的積體電路晶粒114共邊界。介電材料128可為聚合物,例如PBO、聚醯亞胺、BCB等;氮化物,例如氮化矽等;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等;類似材料或其組合,且可例如通過旋轉塗布、疊層、化學氣相沉積等來形成介電材料128。
粘合劑116位於積體電路晶粒114的背側上並將積體電路晶粒114粘合到背側重佈線結構110(例如圖中的介電層108)。粘合劑116可為任何合適的粘合劑、環氧樹脂、晶粒貼合膜(die attach film,DAF)等。可將粘合劑116施加到積體電路晶粒114的背側,例如施加到相應半導體晶圓的背側或者可施加在載體基底100的表面之上。可例如通過鋸切(sawing)或切割(dicing)而將積體電路晶粒114單體化,並使用例如拾取及放置工具(pick-and-place tool)通過粘合劑116而將積體電路晶粒114粘合到介電層108。
在圖4中,在各種元件上形成包封體130。包封體130可為模塑化合物、環氧樹脂等,且可通過壓縮模塑(compression molding)、轉移模塑(transfer molding)等來施加包封體130。在固化之後,包封體130可經歷研磨製程(grinding process)以暴露出穿孔112及晶粒連接件126。在研磨製程之後,穿孔112的頂表面、晶粒連接件126的頂表面及包封體130的頂表面是共面的(coplanar)。在一些實施例中,可省略所述研磨,例如在已暴露出穿孔112及晶粒連接件126的情況下。
在圖5到圖15中,形成前側重佈線結構160(未示於圖5到圖14中,但示於圖15中)。如將在圖15中所示,前側重佈線結構160包括介電層132、介電層140、介電層148、介電層156、金屬化圖案138、金屬化圖案146及金屬化圖案154(有時可將金屬化圖案138、金屬化圖案146及金屬化圖案154稱為重佈線層或重佈線)。
在圖5到圖7中,在包封體130、穿孔112及積體電路晶粒114上形成介電層132,且接著對介電層132進行圖案化及平坦化。在圖5中,在包封體130、穿孔112及積體電路晶粒114之上形成介電層132。如圖5所示,介電層132的最上表面可為波狀的或其他不平坦形式。在一些實施例中,介電層132是由聚合物形成。所述聚合物可為例如PBO、聚醯亞胺、BCB等感光性材料,可使用光刻罩幕(lithography mask)進行圖案化並進行顯影。在其他實施例中,介電層132是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃;或類似物。在介電層132是由非感光性材料形成的實施例中,可通過以下方式對介電層132進行圖案化:在介電層132之上形成光阻劑(圖中未單獨示出),通過下述方法對光阻劑進行圖案化,且蝕刻穿過光阻劑以對介電層132進行圖案化。可通過旋轉塗布、疊層、化學氣相沉積、類似製程或其組合來沉積介電層132。
在沉積介電層132之後,對介電層132進行曝光及顯影以形成開口131,如圖6A及圖6B所示。可通過任何可接受的製程、例如當介電層132為感光性材料時通過將介電層132曝光於經圖案化能量源(例如,經圖案化光源)來進行曝光。在一些實施例中,使用對準光刻機將介電層132曝光於經圖案化能量源,以使得形成在載體基底100之上的介電層132的整個表面被同時曝光。對準光刻機可為接觸對準光刻機(contact aligner)、接近對準光刻機(proximity aligner)或任何其他合適類型的對準光刻機。在對準光刻機為接觸對準光刻機的實施例中,接觸光罩(圖中未單獨示出)可直接接觸介電層132的頂表面,且介電層132可通過接觸光罩曝光於經圖案化能量源。在對準光刻機為接近對準光刻機的實施例中,接近光罩(圖中未單獨示出)可與介電層132的頂表面分隔開一定間隙,且介電層132可通過接觸光罩曝光於經圖案化能量源。所述間隙可為介於約10 mm與約150 mm之間、例如為約55 mm的距離,且所述間隙可利用例如氮氣(N2
)等氣體來填充。
對準光刻機中的接觸光罩、接近光罩或任何其他光罩可覆蓋介電層132的整個表面,以使得介電層132的整個表面可通過對準光刻機被同時曝光。在一些實施例中,載體基底100具有介於約200 mm與約350 mm之間或介於約200 mm與約450 mm之間、例如為約300 mm的直徑,且光罩可具有介於約200 mm與約350 mm之間或介於約200 mm與約450 mm之間、例如為約350 mm的直徑。
可使用對準光刻機來代替步進光刻機(stepper)(有時被稱為步進重複照相機(step-and-repeat camera))。可通過使能量源穿過光罩使用步進光刻機將晶圓的頂表面一次一幀地曝光於經圖案化能量源,以在晶圓的所述表面上形成光罩圖案的圖像。然後將步進光刻機移動到下一幀,且在晶圓的整個表面上重複此製程。步進光刻機的幀大小可為約26 mm×約66 mm、約34 mm×約52 mm等。一次一幀地對晶圓的頂表面進行曝光的技術被稱為縫合技術(stitch technique)。步進光刻機在對每一幀進行曝光之前移動並對準,這可導致在縫合介面(例如,幀至幀介面)處的相鄰幀中的線端區域(line-end area)之間產生重疊(例如,交疊)或偏移(例如,未對準)。可將線端至線端重疊和/或偏移稱為縫合。縫合技術還可導致隨後在半導體封裝200的不同層中形成的通孔及線之間的重疊移位元(例如,局部搭接區(partial land))。由於對準光刻機將介電層132的整個頂表面同時曝光,因此可不存在介電層132或隨後在半導體封裝200中形成的介電層、通孔及線的縫合。此外,半導體封裝中的相鄰層中的通孔及線之間的重疊移位可介於約0.25 µm與約1.0 µm之間,例如為約0.5 µm,小於6 µm或小於2 µm。
在對介電層132進行曝光之後,可通過對介電層132施加顯影劑溶液而對介電層132進行顯影。可通過正性顯影製程或負性顯影製程對介電層132進行顯影。在通過正性顯影製程對介電層132進行顯影的實施例中,介電層132的已曝光於經圖案化能量源的部分變為可溶解在顯影劑溶液中且通過顯影劑溶液來移除。在通過負性顯影製程對介電層132進行顯影的實施例中,介電層132的已曝光於經圖案化能量源的部分變為無法溶解在顯影劑溶液中,且介電層132的未曝光於經圖案化能量源的部分通過顯影劑溶液而被移除。因此,在介電層132中形成開口131,如圖6A及圖6B所示。
圖6B示出包含開口131的介電層132的俯視圖。由於對準光刻機將介電層132的整個頂表面同時曝光於經圖案化能量源,因此多個幀之間不存在縫合。同樣地,隨後在相鄰幀中形成的金屬化圖案(例如分別在圖10、圖12及圖14中所示的金屬化圖案138、金屬化圖案146及金屬化圖案154)的任何重疊移位均會減小或消除。舉例來說,重疊移位可小於約2 µm、介於約0.3 µm與約1.0 µm微米之間或為約0 µm。因此,隨後形成的金屬化圖案可完全落在下伏金屬層上,且可形成具有更小臨界尺寸的金屬化圖案。在一些實施例中,可利用上述方法來形成節距介於約1.0 µm與約10 µm之間的金屬化圖案。
在對介電層132進行圖案化以形成開口131之後,將介電層132平坦化,如圖7所示。然而,在其他實施例中,可在對介電層132進行圖案化以形成開口131之前將介電層132平坦化。可使用例如化學機械平坦化(chemical mechanical planarization,CMP)製程、研磨、蝕刻平坦化製程等任何合適的製程來將介電層132平坦化。平坦化製程可將介電層132的平坦化程度(DoP)從小於約48.6%改善為大於約95%。在一些實施例中,可將介電層132平坦化到介於約48%與小於約100%之間或為約100%的DoP。在形成金屬化圖案138之前或在形成開口131之前將介電層132平坦化有助於擴大光刻製程裕度(lithographic processing window),以使得可使用對準光刻機將介電層132的整個表面同時曝光,而非使用步進光刻機在逐次拍攝過程中一次一個地將介電層132的表面上的幀曝光。如上所述,使用對準光刻機而非步進光刻機可消除幀之間的縫合,且減小隨後形成的金屬化圖案138的任何重疊移位。
在圖8到圖10中,在介電層132上形成具有通孔的金屬化圖案138。如圖8所示,可通過在介電層132之上以及在穿過介電層132的開口中形成晶種層133來形成金屬化圖案138。在一些實施例中,晶種層133為金屬層,所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層133包括鈦層及位於所述鈦層之上的銅層。可利用例如物理氣相沉積等來形成晶種層133。
接著在晶種層133上形成光阻劑134並對光阻劑134進行圖案化。可通過旋轉塗布等來形成光阻劑134且可將光阻劑134曝光於經圖案化能量源並進行顯影來圖案化。舉例來說,可使用對準光刻機將光阻劑134曝光於經圖案化能量源(例如,經圖案化光源),以使得在載體基底100之上形成的光阻劑134的整個表面被同時曝光。在載體基底100具有300 mm的直徑的實施例中,可使用具有約14英寸的直徑的罩幕,以使得載體基底100的整個表面可通過對準光刻機被同時曝光。光阻劑134的圖案對應於金屬化圖案138。所述圖案化形成穿過光阻劑134的開口以暴露出晶種層133。
在圖9中,在光阻劑134的開口中且在晶種層133的被暴露部分上形成導電材料136。可通過例如電鍍或無電鍍覆等鍍覆製程來形成導電材料136。導電材料136可包括金屬,如銅、鈦、鎢、鋁等。
在圖10中,移除光阻劑134以及晶種層133的上面未形成導電材料136的部分。可通過可接受的灰化製程或剝除製程(例如利用氧電漿等)來移除光阻劑134。一旦光阻劑134被移除,便使用例如濕式蝕刻製程或幹式蝕刻製程等可接受的蝕刻製程移除晶種層133的被暴露部分。晶種層133的剩餘部分與導電材料136形成金屬化圖案138及通孔。通孔形成在穿過介電層132的開口中,延伸到例如穿孔112和/或積體電路晶粒114的晶粒連接件126。由於通過對準光刻機而非步進光刻機等在介電層132中形成了開口131,因此金屬化圖案138無縫合,且任何重疊移位小於約2 µm、介於約0.3 µm與約0.1 µm之間或為約0 µm。
在圖11中,在金屬化圖案138及介電層132上沉積介電層140。可由與介電層132相同或相似的材料且通過與介電層132相同或相似的方法來形成介電層140。舉例來說,在一些實施例中,介電層140是由可使用光罩進行圖案化的聚合物形成,所述聚合物可為例如PBO、聚醯亞胺、BCB等感光性材料。在其他實施例中,介電層140是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃;或類似物。在介電層140是由非感光性材料形成的實施例中,可通過以下方式對介電層140進行圖案化:在介電層140之上形成光阻劑(圖中未單獨示出),通過下述方法對光阻劑進行圖案化,且蝕刻穿過光阻劑以對介電層140進行圖案化。可通過旋轉塗布、疊層、化學氣相沉積、類似製程或其組合來形成介電層140。可通過與介電層132相同或相似的方法對介電層140進行圖案化及平坦化。舉例來說,介電層140可使用對準光刻機進行曝光、進行顯影以形成延伸穿過介電層140並暴露出金屬化圖案138的一些部分的開口,且使用例如CMP製程、研磨或蝕刻平坦化製程等製程進行平坦化,如以上參照介電層132所述。在一些實施例中,可在形成暴露出金屬化圖案138的一些部分的開口之前將介電層140平坦化。
在圖12中,在介電層140上形成具有通孔的金屬化圖案146。可由與金屬化圖案138相同或相似的材料且通過與金屬化圖案138相同或相似的方法來形成金屬化圖案146。作為形成金屬化圖案146的實例,在介電層140之上以及在穿過介電層140的開口中形成晶種層(圖中未單獨示出)。在一些實施例中,晶種層為金屬層,所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層之上的銅層。可利用例如物理氣相沉積等來形成晶種層。
接著在晶種層上形成光阻劑(圖中未單獨示出)並對所述光阻劑進行圖案化。可通過旋轉塗布等來形成光阻劑且可將光阻劑曝光於經圖案化能量源並進行顯影來圖案化。舉例來說,可使用對準光刻機將光阻劑曝光於經圖案化能量源(例如,經圖案化光源),以使得在載體基底100之上形成的光阻劑的整個表面被同時曝光。光阻劑的圖案對應於金屬化圖案146。所述圖案化形成穿過光阻劑的開口以暴露出晶種層。
在光阻劑的開口中且在晶種層的被暴露部分上形成導電材料。可通過例如電鍍或無電鍍覆等鍍覆製程來形成所述導電材料。導電材料可包括金屬,如銅、鈦、鎢、鋁等。接著,移除光阻劑以及晶種層的上面未形成導電材料的部分。可例如使用氧電漿等、通過可接受的灰化製程或剝除製程來移除光阻劑。一旦光阻劑被移除,便使用例如濕式蝕刻製程或幹式蝕刻製程等可接受的蝕刻製程移除晶種層的被暴露部分。晶種層的剩餘部分與導電材料形成金屬化圖案146及通孔。通孔形成在開口中,穿過介電層140直到例如金屬化圖案138的一些部分。由於通過對準光刻機而非步進光刻機等在介電層140中形成了開口,因此金屬化圖案146無縫合,且任何重疊移位小於約2 µm、介於約0.3 µm與約0.1 µm之間或為約0 µm。
在圖13中,在金屬化圖案146及介電層140上沉積介電層148。可由與介電層132相同或相似的材料且通過與介電層132相同或相似的方法來形成介電層148。舉例來說,在一些實施例中,介電層148是由可使用光罩進行圖案化的聚合物形成,所述聚合物可為例如PBO、聚醯亞胺、BCB等感光性材料。在其他實施例中,介電層148是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃;或類似物。在介電層148是由非感光性材料形成的實施例中,可通過以下方式對介電層148進行圖案化:在介電層148之上形成光阻劑(圖中未單獨示出),通過下述方法對光阻劑進行圖案化,且蝕刻穿過光阻劑以對介電層148進行圖案化。可通過旋轉塗布、疊層、化學氣相沉積、類似製程或其組合來形成介電層148。可通過與介電層132相同或相似的方法對介電層148進行圖案化及平坦化。舉例來說,介電層148可使用對準光刻機進行曝光、進行顯影以形成延伸穿過介電層148並暴露出金屬化圖案146的一些部分的開口,且使用例如CMP製程、研磨或蝕刻平坦化製程等製程進行平坦化,如以上參照介電層132所述。在一些實施例中,可在形成暴露出金屬化圖案146的一些部分的開口之前將介電層148平坦化。
在圖14中,在介電層148上形成具有通孔的金屬化圖案154。可由與金屬化圖案138相同或相似的材料且通過與金屬化圖案138相同或相似的方法來形成金屬化圖案154。作為形成金屬化圖案154的實例,在介電層148之上以及在穿過介電層148的開口中形成晶種層(圖中未單獨示出)。在一些實施例中,晶種層為金屬層,所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層及位於所述鈦層之上的銅層。可利用例如物理氣相沉積等來形成晶種層。
接著在晶種層上形成光阻劑(圖中未單獨示出)並對所述光阻劑進行圖案化。可通過旋轉塗布等來形成光阻劑且可將光阻劑曝光於經圖案化能量源並進行顯影來圖案化。舉例來說,可使用對準光刻機將光阻劑曝光於經圖案化能量源(例如,經圖案化光源),以使得在載體基底100之上形成的光阻劑的整個表面被同時曝光。光阻劑的圖案對應於金屬化圖案154。所述圖案化形成穿過光阻劑的開口以暴露出晶種層。
在光阻劑的開口中且在晶種層的被暴露部分上形成導電材料。可通過例如電鍍或無電鍍覆等鍍覆製程來形成所述導電材料。導電材料可包括金屬,如銅、鈦、鎢、鋁等。接著,移除光阻劑以及晶種層的上面未形成導電材料的部分。可例如使用氧電漿等、通過可接受的灰化製程或剝除製程來移除光阻劑。一旦光阻劑被移除,便使用例如濕式蝕刻製程或幹式蝕刻製程等可接受的蝕刻製程移除晶種層的被暴露部分。晶種層的剩餘部分與導電材料形成金屬化圖案154及通孔。通孔形成在開口中,穿過介電層148直到達例如金屬化圖案146的一些部分。由於通過對準光刻機而非步進光刻機等在介電層148中形成了開口,因此金屬化圖案154無縫合,且任何重疊移位小於約2 µm、介於約0.3 µm與約0.1 µm之間或為約0 µm。
在圖15中,在金屬化圖案154及介電層148上形成介電層156。可由與介電層132相同或相似的材料且通過與介電層132相同或相似的方法來形成介電層156。舉例來說,在一些實施例中,介電層156是由可使用光罩進行圖案化的聚合物形成,所述聚合物可為例如PBO、聚醯亞胺、BCB等感光性材料。在其他實施例中,介電層156是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃;或類似物。在介電層156是由非感光性材料形成的實施例中,可通過以下方式對介電層156進行圖案化:在介電層156之上形成光阻劑(圖中未單獨示出),通過下述方法對光阻劑進行圖案化,且蝕刻穿過光阻劑以對介電層156進行圖案化。可通過旋轉塗布、疊層、化學氣相沉積、類似製程或其組合來形成介電層156。可通過與介電層132相同或相似的方法對介電層156進行圖案化及平坦化。舉例來說,介電層156可使用對準光刻機進行曝光、進行顯影以形成延伸穿過介電層156並暴露出金屬化圖案154的一些部分的開口,且使用例如CMP製程、研磨或蝕刻平坦化製程等製程進行平坦化,如以上參照介電層132所述。在一些實施例中,可在形成暴露出金屬化圖案154的一些部分的開口之前將介電層156平坦化。
圖15示出包括介電層132、介電層140、介電層148及介電層156以及金屬化圖案138、金屬化圖案146及金屬化圖案154的前側重佈線結構160,以作為實例。可在前側重佈線結構160中形成更多或更少的介電層及金屬化圖案。如果將形成更少介電層及金屬化圖案,則可省略以上論述的步驟及製程。如果將形成更多介電層及金屬化圖案,則可重複以上論述的步驟及製程。所屬領域中的一般技術人員將易於理解哪些步驟及製程將被省略或重複進行。
在圖16中,在前側重佈線結構160的外側上形成凸塊下金屬(underbump metallization,UBM)162。UBM 162用於將導電連接件166及積體被動裝置(integrated passive device,IPD)188耦合到前側重佈線結構160(參見,例如圖17)。在所示實施例中,將UBM 162形成穿過位於介電層156中的開口到金屬化圖案154。UBM 162可各自包括三個導電材料層,例如鈦層、銅層及鎳層。然而,所屬領域中的一般技術人員將知,存在適合用於形成UBM 162的許多合適的材料及層配置,例如鉻/鉻-銅合金/銅/金配置、鈦/鈦鎢/銅配置或銅/鎳/金配置。可用於UBM 162的任何合適的材料或材料層均旨在包含於實施例的範圍內。
在實施例中,通過在金屬化圖案154之上且沿著穿過介電層156的開口的內部形成每一各別層來形成UBM 162。可使用鍍覆製程(例如電化學鍍覆)來執行每一層的形成,然而也可依據期望的材料使用其他形成製程,例如濺鍍、蒸鍍或電漿增強型化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)製程。
在圖17中,在UBM 162上形成導電連接件166。導電連接件166可為球柵陣列(ball grid array,BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊等。導電連接件166可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合等導電材料。在一些實施例中,通過利用例如蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等常用方法初始地形成焊料層來形成導電連接件166。一旦已在結構上形成焊料層,則可執行回焊(reflow)以便將所述材料成型成期望的凸塊形狀。在另一實施例中,導電連接件166為通過濺鍍、印刷、電鍍、無電鍍覆、化學氣相沉積等而形成的金屬柱(例如銅柱)。所述金屬柱可不含有焊料且具有實質上垂直的側壁。在一些實施例中,在導電連接件166的頂部上形成金屬蓋層(metal cap layer)(圖中未示出)。金屬蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合,且可通過鍍覆製程來形成所述金屬蓋層。
還如圖17所示,積體被動裝置(IPD)188貼合到前側重佈線結構160。IPD 188電連接到前側重佈線結構160,且前側重佈線結構160可電連接到積體電路晶粒114。在實施例中,前側重佈線結構160的最底通孔(例如,金屬化圖案138)電連接及物理連接到每一積體電路晶粒114的晶粒連接件126中的一者,且UBM 162電連接及物理連接到IPD 188。
IPD 188在結合到前側重佈線結構160之前,可根據可適用的製造製程對IPD 188進行處理。舉例來說,IPD 188可包括位於IPD 188的主體結構中的一個或多個被動裝置。所述主體結構可包括基底和/或包封體。在包括基底的實施例中,所述基底可為半導體基底,例如經摻雜的或未經摻雜的矽或者SOI基底的主動層。半導體基底可包含:其他半導體材料,例如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或者其組合。也可使用例如多層式基底或梯度基底等其他基底。被動裝置可包括電容器、電阻器、電感器、類似元件或其組合。可在半導體基底中和/或半導體基底上和/或在包封體內形成所述被動裝置,且可通過由例如位於主體結構上的一個或多個介電層中的金屬化圖案形成的內連線結構將所述被動裝置進行內連以形成IPD 188。IPD 188可為表面安裝裝置(surface mount device,SMD)、2端子IPD(2-terminal IPD)、多端子IPD(multi-terminal IPD)或其他類型的被動裝置。IPD 188利用導電連接件189電連接及物理連接到UBM 162,由此將前側重佈線結構160耦合到IPD 188。導電連接件189可相似於導電連接件166,或可為不同的。
在圖18中,可執行載體剝離製程及切割製程以將在載體基底100之上形成的所述多個半導體裝置單體化成各別半導體封裝200。圖17所示裝置可被翻轉(圖中未單獨示出),且導電連接件166可貼合到由框架(圖中未單獨示出)支撐的膠帶(圖中未單獨示出)。所述膠帶可為用於將裝置在隨後的處理中保持在適當位置的切割膠帶,其可為粘合劑。接下來,通過剝離製程將載體基底100從裝置分離(剝離)。剝離製程可使用例如蝕刻、研磨及機械剝落等任何合適的製程來移除載體基底100。在一些實施例中,通過在載體基底100的表面之上照射鐳射或紫外光來剝離載體基底100。鐳射或紫外光破壞釋放層102的化學鍵,且接著可易於分離載體基底100。切割製程可在載體剝離製程之後執行以將在載體基底100之上形成的所述多個半導體裝置單體化成各別半導體封裝200。可通過例如鋸切、切割等製程沿著圖17所示第一封裝區600與第二封裝區602之間的虛線對各別半導體封裝200進行單體化。在一些實施例中,半導體封裝200可具有1 mm×1 mm、介於1 mm×1 mm與300 mm×300 mm或小於300 mm×300 mm的大小。
將介電層132、介電層140、介電層148及介電層156平坦化會改善介電層132、介電層140、介電層148及介電層156以及各別半導體封裝200的總體結構的平坦化程度。在形成金屬化圖案138、金屬化圖案146、金屬化圖案154及UBM 162之前將介電層132、介電層140、介電層148及介電層156平坦化有助於擴大光刻製程裕度,以使得可使用對準光刻機將介電層或光阻劑的整個表面同時曝光,而非使用步進光刻機在逐次拍攝過程中一次一個地將待圖案化的介電層或光阻劑的表面上的幀曝光。如上所述,使用對準光刻機而非步進光刻機使得在幀之間不存在縫合,且減小隨後形成的金屬化圖案或UBM的任何重疊移位。
根據實施例,一種方法包括:將積體電路晶粒及穿孔包封在模塑化合物中,所述積體電路晶粒具有晶粒連接件;在所述模塑化合物之上沉積第一介電層;圖案化出第一開口,所述第一開口穿過所述第一介電層且暴露出所述積體電路晶粒的所述晶粒連接件;將所述第一介電層平坦化;在所述第一介電層之上及所述第一開口中沉積第一晶種層;以及在所述第一晶種層上鍍敷延伸穿過所述第一介電層的第一導通孔。在實施例中,所述將所述第一介電層平坦化包括化學機械平坦化(CMP)製程。在實施例中,所述圖案化出所述第一開口包括:使用對準光刻機將所述第一介電層暴露於光。在實施例中,所述圖案化出第一開口包括:將所述第一介電層曝光於經圖案化能量源,且將所述第一介電層的整個頂表面同時曝光於所述經圖案化能量源。在實施例中,所述方法還包括:在所述第一晶種層之上沉積光阻劑且使用對準光刻機將所述光阻劑曝光於經圖案化能量源。在實施例中,所述將所述光阻劑曝光於所述經圖案化能量源包括:使光罩接觸所述第一介電層的頂表面,所述光罩覆蓋所述第一介電層的整個所述頂表面。在實施例中,所述方法還包括:在所述第一介電層及所述第一導通孔之上沉積第二介電層;圖案化出第二開口,所述第二開口穿過所述第二介電層且暴露出所述第一導通孔;將所述第一介電層平坦化;在所述第二介電層之上及所述第二開口中沉積第二晶種層;以及在所述第二晶種層上鍍覆延伸穿過所述第二介電層的第二導通孔。
根據另一實施例,一種方法包括:將多個積體電路晶粒包封在模塑化合物中,所述多個積體電路晶粒中的每一者設置在晶圓上,所述多個積體電路晶粒中的每一者具有晶粒連接件;在所述模塑化合物及所述多個積體電路晶粒之上沉積第一介電層;將所述第一介電層的整個上表面同時曝光於第一經圖案化能量源;對所述第一介電層進行顯影以形成暴露出所述多個積體電路晶粒的第一多個開口;將所述第一介電層平坦化;以及穿過所述第一介電層形成第一金屬化圖案,所述第一金屬化圖案接觸所述晶粒連接件。在實施例中,所述形成所述第一金屬化圖案包括:在所述第一介電層之上形成晶種層;在所述晶種層之上形成光阻劑;將所述光阻劑的整個上表面同時曝光於第二經圖案化能量源;對所述光阻劑進行顯影以形成暴露出所述晶種層的第二多個開口;以及在所述第二多個開口中鍍覆導電材料。在實施例中,所述方法還包括:在所述第一介電層及所述第一金屬化圖案之上沉積第二介電層;將所述第二介電層的整個上表面同時曝光於第二經圖案化能量源;對所述第二介電層進行顯影以形成暴露出所述第一金屬化圖案的第二多個開口;將所述第二介電層平坦化;以及穿過所述第二介電層形成第二金屬化圖案,所述第二金屬化圖案接觸所述第一金屬化圖案,所述第二金屬化圖案相對於所述第一金屬化圖案具有小於2 µm的重疊移位。在實施例中,所述第一介電層是在對所述第一介電層進行顯影之後被平坦化。在實施例中,所述第一介電層的所述整個上表面是通過經由罩幕投射能量源而被曝光,所述罩幕產生所述第一經圖案化能量源。在實施例中,所述罩幕的直徑實質上相同於所述晶圓的直徑。在實施例中,所述第一介電層是在對所述第一介電層的所述整個上表面同時進行曝光之前被平坦化。
根據再一實施例,一種半導體封裝包括:模塑化合物;積體電路晶粒,包封在所述模塑化合物中;穿孔,鄰近所述積體電路晶粒,所述模塑化合物在所述穿孔與所述積體電路晶粒之間延伸;以及重佈線結構,位於所述積體電路晶粒、所述模塑化合物及所述穿孔之上,所述重佈線結構電連接到所述積體電路晶粒及所述穿孔,所述重佈線結構包括:第一介電層,設置在所述模塑化合物之上;以及第一導電特徵,延伸穿過所述第一介電層,所述第一導電特徵無縫合。在實施例中,所述第一導電特徵包括延伸穿過第一介電層的第一導電通孔及在第一介電層的頂表面之上延伸的第一導電線;且重佈線結構還包括第二介電層,設置在第一介電層及第一導電特徵之上,所述第二介電層的頂表面具有介於48%與100%之間的第一平坦化程度;以及第二導電特徵,延伸穿過第二介電層以接觸第一導電特徵。在實施例中,所述裝置還包括:最頂介電層,設置在所述第一介電層及所述第一導電特徵之上,其中所述最頂介電層的頂表面具有介於48%與100%之間的第二平坦化程度;以及UBM,延伸穿過所述最頂介電層。在實施例中,所述裝置還包括貼合到所述UBM的積體被動裝置。在實施例中,所述第一介電層的頂表面具有介於48%與100%之間的第一平坦化程度。在實施例中,所述第一導電特徵的節距等於或小於2 µm。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解,其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
100‧‧‧載體基底
102‧‧‧釋放層
104、108、132、140、148、156‧‧‧介電層
106、138、146、154‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112‧‧‧穿孔
114‧‧‧積體電路晶粒
116‧‧‧粘合劑
118‧‧‧半導體基底
120‧‧‧內連線結構
122‧‧‧襯墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
131‧‧‧開口
133‧‧‧晶種層
134‧‧‧光阻劑
136‧‧‧導電材料
160‧‧‧前側重佈線結構
162‧‧‧凸塊下金屬
166、189‧‧‧導電連接件
188‧‧‧積體被動裝置
200‧‧‧半導體封裝
600‧‧‧第一封裝區
602‧‧‧第二封裝區
結合附圖閱讀以下詳細說明,會最好地理解本公開的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。 圖1示出根據一些實施例的在基底之上形成的重佈線結構。 圖2示出根據一些實施例的穿孔的形成。 圖3示出根據一些實施例的積體電路晶粒的放置。 圖4示出根據一些實施例的利用包封體進行的包封。 圖5示出根據一些實施例的介電層的形成。 圖6A示出根據一些實施例的介電層的圖案化。 圖6B示出根據一些實施例的經圖案化介電層的俯視圖。 圖7示出根據一些實施例的介電層的平坦化。 圖8示出根據一些實施例的晶種層及光阻劑的形成。 圖9示出根據一些實施例的導電材料的形成。 圖10示出根據一些實施例的光阻劑的移除及金屬化圖案的形成。 圖11示出根據一些實施例的介電層的形成。 圖12示出根據一些實施例的金屬化圖案的形成。 圖13示出根據一些實施例的介電層的形成。 圖14示出根據一些實施例的金屬化圖案的形成。 圖15示出根據一些實施例的介電層的形成。 圖16示出根據一些實施例的凸塊下金屬的形成。 圖17示出根據一些實施例的導電連接件的形成及積體被動裝置的放置。 圖18示出根據一些實施例的第一封裝的形成。
Claims (1)
- 一種形成半導體封裝的方法,其特徵在於,包括: 將積體電路晶粒及穿孔包封在模塑化合物中,所述積體電路晶粒具有晶粒連接件; 將第一介電層沉積在所述模塑化合物之上; 圖案化出第一開口,所述第一開口穿過所述第一介電層且暴露出所述積體電路晶粒的所述晶粒連接件; 將所述第一介電層平坦化; 將第一晶種層沉積在所述第一介電層之上及所述第一開口中;以及 在所述第一晶種層上鍍覆延伸穿過所述第一介電層的第一導通孔。
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