TWI753407B - 積體電路封裝及方法 - Google Patents

積體電路封裝及方法 Download PDF

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TWI753407B
TWI753407B TW109113240A TW109113240A TWI753407B TW I753407 B TWI753407 B TW I753407B TW 109113240 A TW109113240 A TW 109113240A TW 109113240 A TW109113240 A TW 109113240A TW I753407 B TWI753407 B TW I753407B
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Taiwan
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package
interposer
carrier
forming
redistribution
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TW109113240A
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TW202129849A (zh
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林士庭
吳集錫
丁國強
盧思維
侯上勇
陳偉銘
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台灣積體電路製造股份有限公司
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Abstract

一種方法包含：將半導體元件附接至中介層結構；將中介層結構附接至第一載板基底；將積體被動元件附接至第一載板基底；在半導體元件及積體被動元件上方形成包封體；剝離第一載板基底；將包封體及半導體元件附接至第二載板基底；在包封體、中介層結構以及積體被動元件上形成第一重佈線結構，其中第一重佈線結構接觸中介層結構及積體被動元件；以及在第一重佈線結構上形成外部連接件。

Description

積體電路封裝及方法
本發明的實施例是有關於一種封裝結構及其製造方法，且特別是關於一種積體電路封裝及製造方法。
由於積體電路(integrated circuit；IC)的發展，半導體行業已由於各種電子組件(亦即電晶體、二極體、電阻器、電容器等)的整合密度的連續改良而經歷持續快速增長。大部分情況下，整合密度的改良來自最小特徵尺寸的不斷減小，這使得更多組件可以整合到給定區域中。
這些整合改良在本質上為基本上二維(two-dimensional；2D)的，此係由於藉由整合式組件佔據的區域基本上在半導體晶圓的表面上。積體電路的區域中的密度增加及相應的面積減小通常已超過了將積體電路晶片直接接合到基底上的能力。中介層已用於將球的接觸區域自晶片的接觸區域重佈至中介層的較大區域。另外，中介層已實現包含多個晶片的三維封裝。亦已研發其他封裝以併入三維態樣。
根據一些實施例，一種封裝的製造方法包括形成元件結構及形成封裝結構。形成元件結構包括將第一晶粒連接至第一中介層；將第二晶粒連接至第二中介層；以及在第一中介層及第二中介層上方形成第一重佈線結構，其中第一重佈線結構將第一中介層電性連接至第二中介層。形成封裝結構包括將第一表面安裝元件(SMD)及元件結構附接至第一載板；用第一包封體包封第一SMD及元件結構，以形成具有頂表面及底表面的包封結構；將包封結構的頂表面附接至第二載板；以及在包封結構的底表面上方形成第二重佈線結構，其中第二重佈線結構電性連接第一SMD及元件結構。
根據一些實施例，一種封裝的製造方法包括將半導體元件附接至中介層結構；將中介層結構附接至第一載板基底；將積體被動元件附接至第一載板基底；在半導體元件及積體被動元件上方形成包封體；剝離第一載板基底；將包封體及半導體元件附接至第二載板基底；在包封體、中介層結構以及積體被動元件上形成第一重佈線結構，其中第一重佈線結構接觸中介層結構及積體被動元件；以及在第一重佈線結構上形成外部連接件。
根據一些實施例，一種封裝包含元件基底及附接至元件基底的第一側的元件結構，元件結構包含第一中介層、第二中介層、附接至第一中介層的第一半導體元件、附接至第二中介層的第二半導體元件以及連接至第一中介層及第二中介層的第一重佈線結構。在實施例中，元件基底包含積體電路。
50、50'、50A、50B、50C、50D、50E、50F:積體電路元件
51A、51B、51C、51D:功能組件
52、72:基底
54、76:內連線結構
70:中介層
74:穿孔
76'、120':部分
100、100'、100A、100B、100E、100F:元件封裝
102、104:導電凸塊
106:導電連接件
108:底膠材料
110:元件結構
111:載帶
112、113、214:包封體
114、115:載板
116、204、223:離型層
120、220:重佈線結構
122、226、228、230:介電層
124:重佈線層
138、236:凸塊下金屬(UBM)
200、300、400:封裝結構
202:第一載板
206:黏著劑
208:導電焊墊
210:電子元件
212、404:連接件
222:第二載板
224:外部連接件
232、234:金屬化圖案
402:IC基底
406:底膠
D:距離
LW1、LW2:長度或寬度
結根據合附圖閱讀的以下詳細描述會最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵並未按比例繪製。事實上，可出於論述清楚起見而任意地增大或減小各種特徵的尺寸。
圖1至圖2為根據一些實施例的在用於形成元件封裝的製程期間的中間步驟的剖面圖。
圖3A至圖3C為根據一些實施例的在用於形成元件封裝的製程期間的中間步驟的剖面圖及平面圖。
圖4至圖9為根據一些實施例的在用於形成元件封裝的製程期間的中間步驟的剖面圖。
圖10至圖13為根據一些實施例的在用於形成元件結構的製程期間的中間步驟的剖面圖。
圖14為根據一些實施例的在用於形成元件封裝的製程期間的中間步驟的平面圖。
圖15為根據一些實施例的元件封裝的示意圖。
圖16A至圖16C為根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的剖面圖。
圖17至圖22為根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的剖面圖。
圖23A至圖23C為根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的剖面圖。
圖24至圖28為根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的剖面圖。
圖29為根據一些實施例的封裝結構的剖面圖。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。以下描述組件及佈置的具體實例以簡化本揭露。當然，這些組件及佈置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含在第一特徵與第二特徵之間可形成額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不指示所論述的各種實施例及/或配置之間的關係。
另外，本文中為易於描述可使用諸如「在......之下」、「在......下方」、「下部」、「在......上方」、「上部」以及類似者的空間相對術語來描述如圖式中所說明的一個部件或特徵與另一(些)部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
根據一些實施例，描述含有積體電路元件的封裝。在一些實施例中，描述含有由重佈線結構電性連接的多個元件封裝的元件結構。重佈線結構的使用可允許較小特徵形成於每一元件封裝內，此可改良效能及改良微影圖案化。根據一些實施例，可形成包含電子元件(例如表面安裝元件(surface-mount device；SMD))、元件封裝及/或元件結構的封裝結構。藉由使用兩個單獨 載板形成封裝結構，可使用具有不同厚度的電子元件。另外，重佈線結構可用於形成電性互連，此可降低處理成本及減少處理步驟。
圖1為根據一些實施例的積體電路元件50的剖面圖。積體電路元件50可為邏輯晶粒(例如中央處理單元(central processing unit；CPU)、圖形處理單元(graphics processing unit；GPU)、系統單晶片(system-on-a-chip；SoC)、微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(dynamic random access memory；DRAM)晶粒、靜態隨機存取記憶體(static random access memory；SRAM)晶粒等)、電源管理晶粒(例如電源管理積體電路(power management integrated circuit；PMIC)晶粒)、射頻(radio frequency；RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system；MEMS)晶粒、訊號處理晶粒(例如數位訊號處理(digital signal processing；DSP)晶粒)、前端晶粒(例如類比前端(analog front-end；AFE)晶粒)、類似者或其組合。積體電路元件50可形成於晶圓中，所述晶圓可包含在後續步驟中經單體化以形成多個積體電路元件50的不同元件區。積體電路元件50包含基底52及內連線結構54。
基底52可包含塊狀半導體基底、絕緣體上半導體(semiconductor-on-insulator；SOI)基底、多層半導體基底或類似者。基底52的半導體材料可為矽、鍺、化合物半導體包含矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦、合金半導體包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP、或其組合。亦可使用其他基底，諸如多層基底或梯度基 底。基底52可經摻雜或未經摻雜。元件(如電晶體、電容器、電阻器、二極體以及類似者)可形成於基底52的主動表面(例如面朝上的表面)中及/或主動表面上。
具有一個或多個介電層以及相應金屬化圖案的內連線結構54形成於基底52的主動表面上。介電層可為金屬化間介電(inter-metallization dielectric；IMD)層。IMD層可由例如低K介電材料藉由本領域中已知的任何合適的方法形成，所述低K介電材料諸如未經摻雜的矽酸鹽玻璃(undoped silicate glass；USG)、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼磷矽玻璃(borophosphosilicate glass；BPSG)、氟矽酸鹽玻璃(fluorosilicate glass；FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、碳化矽材料、其化合物、其複合物、其組合或類似者，所述方法諸如旋轉塗佈、化學氣相沉積(chemical vapor deposition；CVD)、電漿增強型CVD(plasma-enhanced CVD；PECVD)、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition；HDP-CVD)或類似者。介電層中的金屬化圖案可諸如藉由使用通孔及/或跡線在元件之間傳送電訊號，亦可含有各種電性元件，諸如電容器、電阻器、電感器或類似者。各種元件及金屬化圖案可互連以執行一個或多個功能。功能可包含記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路系統或類似者。另外，晶粒連接件(諸如導電柱或接觸焊墊)形成於內連線結構54中及/或內連線結構54上，以向電路系統以及元件提供外部電性連接。所屬領域中具通常知識者應瞭解，出於說明的目的，提供以上實例。對於特定的應用，可以適當地使用其他電路。
在一些實施例中，積體電路元件50為包含多個基底52的堆疊元件。舉例而言，積體電路元件50可為記憶體元件(如混合記憶體立方體(hybrid memory cube；HMC)模組、高頻寬記憶體(high bandwidth memory；HBM)模組或類似者)並可包含多個記憶體晶粒。在此類實施例中，積體電路元件50包含藉由通孔互連的多個基底52。基底52中的每一者可(或可不)具有單獨內連線結構54。
圖2為根據一些實施例的中介層70的剖面圖。儘管僅繪示一個中介層70，但應瞭解，中介層70可形成於具有多個元件區的晶圓中，其中每一元件區用於形成一個中介層70。中介層70包含基底72、穿孔74及內連線結構76。
基底72可為塊狀半導體基底、SOI基底、多層半導體基底或類似者。基底72的半導體材料可為矽、鍺、化合物半導體包含矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦、合金半導體包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、其組合或類似者。亦可使用其他基底，諸如多層基底或梯度基底。基底72可經摻雜或未經摻雜。元件(如電晶體、電容器、電阻器、二極體以及類似者)可形成於基底72的表面中及/或表面上。在一些實施例中，基底72基於諸如玻璃纖維強化樹脂芯(fiberglass reinforced resin core)的絕緣芯。舉例而言，芯材料可為玻璃纖維樹脂，如FR-4、雙馬來亞醯胺-三嗪(bismaleimide-triazine；BT)樹脂、其他印刷電路板(printed circuit board；PCB)材料或膜、組合或類似者。增層膜(如味之素增層膜(Ajinomoto build-up film；ABF))或其他層壓物可用於基底72。
穿孔74經形成為自基底72的前表面延伸至基底72中。當基底72為矽基底時，穿孔74有時亦稱為基底穿孔或矽穿孔(through-substrate via/through-silicon via；TSV)。穿孔74可藉由在基底72中形成凹部以例如蝕刻、研磨(milling)、雷射技術、其組合或類似者方式而形成。薄介電材料可諸如藉由使用氧化技術而形成於凹部中。薄障壁層可如藉由CVD、原子層沉積(atomic layer deposition；ALD)、物理氣相沉積(PVD)、熱氧化、其組合及/或類似者共形地沉積於基底72的前側上方以及開口中。障壁層可由氮化物或氮氧化物(如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、其組合或類似者)形成。導電材料可沉積於薄障壁層上方以及開口中。可藉由電化學鍍覆製程、CVD、ALD、PVD、其組合或類似者形成導電材料。導電材料的實例為銅、鎢、鋁、銀、金、其組合或類似者。過量的導電材料及過量的障壁層可藉由例如化學機械研磨(chemical-mechanical polish；CMP)而自基底72的前側移除。因此，穿孔74可包含導電材料，其中薄障壁層在導電材料與基底72之間。
內連線結構76形成於基底72的前表面上方，並且用於在基底72的元件(若存在)、穿孔74及/或外部元件之間形成電性連接。內連線結構76可包含一個或多個介電層以及介電層中的相應金屬化圖案。金屬化圖案可為包含形成電性連接的通孔及/或跡線的重佈線層(Redistribution Layer；RDL)。在一些實施例中，內連線結構76可為重佈線結構或扇出型結構。
在一些實施例中，藉由在基底72上形成第一介電層(圖2中未單獨標記)來形成內連線結構76。在一些實施例中，第一 介電層由聚合物形成，所述聚合物可為可使用微影經圖案化的感光性材料，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene；BCB)或類似者。在其他實施例中，第一介電層由氮化物(諸如氮化矽)、氧化物(諸如氧化矽)、磷矽酸鹽玻璃(Phosphosilicate Glass；PSG)、硼矽酸鹽玻璃(Borosilicate Glass；BSG)、硼摻磷矽酸鹽玻璃(Boron-doped Phosphosilicate Glass；BPSG)或類似者形成。第一介電層可藉由旋轉塗佈、層壓、CVD、類似者或其組合而形成。第一介電層隨後經圖案化以形成暴露出穿孔74的開口。在第一介電層由感光性材料形成的實施例中，可藉由根據所需圖案暴露出第一介電層並執行顯影製程以移除不需要的材料從而暴露出穿孔74來執行圖案化。其他技術(如使用經圖案化光罩及蝕刻)亦可用於使第一介電層圖案化。
晶種層(圖2中未示出)形成於第一介電層上方以及第一介電層中形成的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者形成晶種層。光罩(圖2中未示出)隨後根據所要金屬化圖案而形成於晶種層上且在晶種層上圖案化。在一些實施例中，光罩是藉由旋轉塗佈或類似者形成的光阻，隨後使其暴露於光下以進行圖案化。圖案化形成穿過光罩的開口以暴露出晶種層。導電材料形成於光罩的開口中以及晶種層的暴露部分上。導電材料可藉由鍍覆(如電鍍或無電式鍍覆或類似者)形成。導電材料可包括金屬，諸如銅、鈦、鎢、鋁、其組合或類似 者。隨後，移除光阻以及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程(諸如使用氧電漿或類似者)移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料在內連線結構76內形成第一RDL。
額外的介電層以及額外的RDL可隨後形成於第一介電層上方以在內連線結構76內形成額外的電性連接。額外的介電層以及額外的RDL可使用與用於形成第一介電層及第一RDL類似的材料及製程形成。舉例而言，可利用與第一介電層類似的製程且用與第一介電層類似的材料形成額外的介電層。可使開口貫穿額外的介電層中的每一者，以暴露出下伏RDL的至少一部分。儘管可替代地使用任何合適的製程，但可使用合適的微影光罩及蝕刻製程(諸如上文針對第一介電層描述的那些蝕刻製程)形成開口。在一些實施例中，額外的介電層由感光聚合物形成且可使用微影光罩及蝕刻製程使開口直接在額外的介電層中圖案化。
額外的RDL可形成於每一額外的介電層中以在內連線結構76內提供額外的電性連接。在實施例中，可使用與第一RDL類似的材料及製程形成額外的RDL。舉例而言，可形成晶種層且光阻可針對額外的RDL以所需的圖案放置於晶種層的頂部並在晶種層的頂部經圖案化。導電材料可隨後使用例如鍍覆製程而形成於光阻的經圖案化開口中。可隨後移除光阻並蝕刻晶種層，從而形成額外的RDL。可以此方式自多個介電層以及多個RDL形成內連線結構76。
在一些實施例中，凸塊下金屬(under bump metallization；UBM)可形成於內連線結構76的最上部RDL上方且在最上部RDL上方經圖案化。UBM向內連線結構76提供電性連接，可將電連接件(例如焊球/凸塊、導電柱或類似者)放置於內連線結構76上。在一些實施例中，UBM包含擴散障壁層、晶種層或其組合。擴散障壁層可包含Ti、TiN、Ta、TaN或其組合。晶種層可包含銅或銅合金。然而，亦可包含其他金屬，諸如鎳、鈀、銀、金、鋁、其組合以及其多層。可使用濺鍍、電鍍或類似者形成UBM。
圖3A至圖15為根據一些實施例的在用於形成堆疊半導體元件的製程期間的中間步驟的剖面圖。在圖3A至圖9中，藉由將各種積體電路元件50接合至中介層70的前側形成元件封裝100。在一些實施例中，第一元件封裝100是晶圓上晶片(chip-on-wafer；CoW)封裝，但應瞭解，可將實施例應用於其他三維積體電路(three-dimensional integrated circuit；3DIC)封裝。元件結構100可用於形成封裝結構，諸如封裝結構200(參看圖22)或封裝結構300(參看圖28)。
在圖3A至圖3C中，一個或多個積體電路元件50附接至中介層70。圖3A繪示附接至中介層70的積體電路元件50A及積體電路元件50B的剖面圖，圖3B至圖3C繪示根據一些實施例的以不同佈置附接至中介層70的積體電路元件50A及積體電路元件50B的平面圖。內連線結構54及內連線結構76物理連接且電性連接積體電路元件50及中介層70。積體電路元件50可經由內連線結構76彼此電性連接。積體電路元件50可包含類似元件及/或不同元件。舉例而言，圖3A至圖3C中所示的實施例包含積體電 路元件50A及積體電路元件50B，其中元件50A可具有與元件50B不同的功能。積體電路元件50A或積體電路元件50B可各自具有單個功能(例如邏輯元件、記憶體晶粒等)或可具有多個功能(例如系統單晶片或類似者)。在實施例中，積體電路元件50A為邏輯元件(諸如CPU)且積體電路元件50B為記憶體元件(諸如HBM模組)。在一些實施例中，可將積體電路元件50與其他積體電路元件50相關聯。舉例而言，單個元件50A可具有與其相關聯的一個或多個元件50B，所述一個或多個元件(例如經由內連線結構76)電性連接至所述元件50A。
積體電路元件50A及積體電路元件50B可使用例如取放工具附接至內連線結構76。在中介層70形成於晶圓中的實施例中，積體電路元件50可附接於晶圓的不同元件區中。不同元件區可隨後在後續步驟中經單體化以形成多個第一元件封裝100(參看圖9)。積體電路元件50可以任何合適的配置佈置於內連線結構76上或佈置於元件區內。舉例而言，圖3B繪示其中元件50B與每一元件50A的一側相鄰的元件50A，圖3C繪示其中元件50B與每一元件50A的相對側相鄰的元件50A。在一些實施例(如圖3B的實施例)中，積體電路元件50B鄰近於積體電路元件50A不對稱佈置。在一些實施例(諸如圖3C的實施例)中，積體電路元件50B鄰近於積體電路元件50A對稱佈置。不對稱的佈局可使積體電路元件50B更接近積體電路元件50A的輸入/輸出(input/output；I/O)連接區定位。這些為實例，其他配置或佈置也是可能的。
在圖3A中所示的實施例中，積體電路元件50A及積體 電路元件元件50B經由包含導電凸塊102、導電凸塊104及導電連接件106的連接而附接至內連線結構76。導電凸塊102電性連接至且物理連接至內連線結構54，並且導電凸塊104電性連接且物理連接至內連線結構76。導電連接件106接合導電凸塊102及導電凸塊104。導電凸塊102可形成於內連線結構54或內連線結構76的UBM(若存在)上方。導電凸塊102或導電凸塊104可由導電材料(諸如銅、鋁、金、鎳、鈀、類似者或其組合)形成。導電凸塊102或導電凸塊104可藉由合適的製程(諸如濺鍍、印刷、電鍍、無電式鍍覆、CVD或類似者)形成。在一些實施例中，導電凸塊102或導電凸塊104亦可包括藉由濺鍍、印刷、電鍍、無電式鍍覆、CVD或類似者形成的金屬柱(諸如銅柱)。金屬柱可不含焊料且具有實質上豎直的側壁或傾斜的側壁。導電凸塊亦可稱為微凸塊(microbump)。
導電連接件106可由導電材料(如焊料)形成且可藉由以下方式而形成：經由諸如蒸鍍、電鍍、印刷、焊料轉移、植球或類似的方法在導電凸塊102或導電凸塊104上先形成焊料層。一旦形成焊料層，即可執行回焊製程以便將導電連接件106塑形為所需的凸塊形狀。
在其他實施例中，積體電路元件50藉由面對面接合附接至內連線結構76。舉例而言，混合接合、熔融接合、直接接合、介電接合、金屬接合或類似者可用於在不使用焊料的情況下附接內連線結構54及內連線結構76。另外，可使用接合技術的混合，例如，一些積體電路元件50A及積體電路元件50B可藉由導電連接件106接合至內連線結構76，其他積體電路元件50A及積體電 路元件50B可藉由面對面接合而接合至內連線結構76。
在圖4中，將底膠材料108點膠在積體電路元件50與內連線結構76之間。底膠材料108包圍導電凸塊102及導電凸塊104以及導電連接件106。底膠材料108可為任何可接受的材料，諸如聚合物、環氧樹脂、模塑底膠或類似者。底膠材料108可藉由毛細流動製程形成。
在圖5中，包封體112形成於所述結構的各種組件上。包封體112可為模塑化合物、環氧樹脂或類似者，並且可藉由壓縮模塑、轉移模塑或類似者而塗覆。包封體112可形成於內連線結構76上方，以使積體電路元件50及底膠材料110由包封體112包圍及覆蓋。可隨後固化包封體112。在一些實施例中，過量的包封體112材料(例如藉由CMP)經移除，此亦可平坦化所述結構，以使包封體112的頂表面與積體電路元件50的頂表面齊平。
在圖6中，所述結構翻轉且附接至載板114或其他合適的支撐結構以用於後續處理。載板114可為玻璃載板基底、陶瓷載板基底或類似者。載板114可為晶圓，以使多個封裝可同時形成於載板114上。所述結構可例如藉由離型層116附接至載板114。離型層116可由聚合物類材料形成，可將其連同載板114一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，離型層116為在加熱時損失其黏著特性的環氧類熱離型材料，諸如光-熱轉換(light-to-heat-conversion；LTHC)離型塗層。在其他實施例中，離型層116可為在暴露於UV光時損失其黏著特性的紫外線(ultra-violet；UV)黏膠。離型層116可以液體形式點膠且經固化，可為層壓於載板114上的層壓膜或可為類似者。可使離 型層116的頂表面齊平且所述頂表面可具有高度平面性。
在圖7中，使基底72薄化(例如藉由CMP)以暴露出穿孔74。在一些實施例中，基底72的暴露表面與穿孔74的暴露表面齊平。在一些實施例(未示出)中，可執行凹陷製程(recessing process)以使基底72凹陷，從而使穿孔74自基底72的背側突起。凹陷製程可為例如使用濕式蝕刻及/或乾式蝕刻的合適回蝕(etch-back)製程。在一些實施例中，絕緣層(未示出)可形成於包圍及保護穿孔74的突出部分的基底72的背側上。
在圖8中，所述結構自載板114剝離且經單體化，從而形成一個或多個元件封裝100。根據一些實施例，剝離包含將光(如雷射光或紫外(UV)光)照射於離型層116上，以使離型層116在光熱下分解且可移除載板114。移除離型層116或載板114的其他技術可用於其他實施例中。如圖8中所示，可隨後將所述結構放置於載帶111或類似者上，隨後所述結構經單體化以形成單獨元件封裝100。舉例而言，中介層70可沿著相鄰元件區之間的切割道區經單體化以形成元件封裝100。單體化製程可包含鋸切、切割或類似者。在單體化之後，中介層70的側壁與每一元件封裝100的包封體112的側壁可共面。在圖9中繪示單獨元件封裝100。在一些實施例中，單獨元件封裝100可具有在約20毫米與約50毫米之間的長度或寬度(例如圖9中所示的LW1)。元件封裝100亦可稱為晶圓上晶片(CoW)元件。
圖10至圖16為根據一些實施例的在用於形成元件結構110(參看圖12)的製程期間的中間步驟的剖面圖及平面圖。每一元件結構110包含藉由重佈線結構120彼此電性連接的多個元件 封裝100。類似於上文所描述的元件封裝100，元件結構110可用於形成封裝結構，如封裝結構300(參看圖28)。在元件結構110的一些實施例中，多組積體電路元件50形成於藉由重佈線結構120電性互連的單獨的較小中介層70上，而非將單個較大中介層70用於單組積體電路元件50(如在元件封裝100中)。在一些情況下，以此方式形成較小中介層70允許使用經配置以在內連線結構76的微影圖案化期間用於較大圖案縮小(例如縮小2X、3X、4X或大於4X)的倍縮光罩。使用較大圖案縮小可實現較小經圖案化的特徵尺寸，諸如RDL的較大密度、RDL的較小線寬或類似者。較大圖案縮小亦可在圖案化期間實現經圖案化特徵的經減小的線粗糙度(line roughness)及經減小的製程缺陷機率。此外，內連線結構76的較小的特徵尺寸可實現電訊號(尤其是針對高頻率(例如大於約2MHz，諸如約5MHz)下的訊號)的較少雜訊及更高效的傳輸。因此，藉由形成具有附接至多個中介層70的多個積體電路元件50的元件結構110，每一中介層70上的積體半導體元件50之間的電內連線可經形成為具有較小的特徵尺寸且具有經改良製程可靠性。在一些實施例中，單個積體電路元件(例如圖9中的元件50A)的功能性可經分離成兩個或大於兩個積體電路元件(例如圖15至圖16中的元件50C及元件50D)，所述兩個或大於兩個積體電路元件各自附接至單獨中介層70。
轉而參看圖10，根據一些實施例，多個元件封裝100附接至載板115。載板115可為例如如先前針對載板114(參看圖6)所描述的載板或材料。圖10繪示附接至載板115的兩個元件封裝100(經標示為100A及100B)，但在其他實施例中，多於兩個元 件封裝100可附接至載板且元件封裝100可以任何合適的配置或佈置進行附接。圖10中所示的實施例包含第一元件封裝100A(其包含積體電路元件50A及積體電路元件50B)及第二元件封裝100B(其包含積體電路元件50C及積體電路元件50D)。每一元件封裝內的積體電路元件50可為類似的或不同的。舉例而言，元件封裝100A中的積體電路元件50A可與元件封裝100B中的積體電路元件50C類似或不同，或者元件封裝100A中的積體電路元件50B可與元件封裝100B中的積體電路元件50D類似或不同。類似或不同的積體電路元件50的任何組合可存在於元件封裝100中，積體電路元件50的其他配置為可能的。
元件封裝100可使用例如取放工具附接至內連線結構76。在一些實施例中，黏著層(圖10中未示出)可形成於載板115上或形成於元件封裝100上以便於附接。在一些實施例中，單獨元件封裝100可具有在約20毫米與約50毫米之間的長度或寬度(例如圖10中所示的LW2)。在一些實施例中，元件封裝100可在放置於載板115上之前進行電性測試。以此方式，可僅附接已知良好的元件封裝100，從而提高隨後形成的元件結構110或封裝結構300的良率。
在圖11中，根據一些實施例，包封體113形成於元件封裝100及載板115上。包封體113可為模塑化合物、環氧樹脂或類似者，並且可藉由壓縮模塑、轉移模塑或類似者而塗覆。在一些實施例中，包封體113可與包封體112(參看圖5)類似。包封體113可經形成為使得元件封裝100由包封體113包圍及覆蓋。包封體113可隨後固化。在一些實施例中，移除(例如藉由CMP) 包封體113的過量材料，此亦可平坦化所述結構，以使包封體113的頂表面與元件封裝100的頂表面齊平。
重佈線結構120形成於元件封裝100上方且用於在元件封裝100及/或外部元件之間形成電性連接。重佈線結構120可包含一個或多個介電層以及RDL，所述RDL包含形成電性連接的通孔及/或跡線。圖12中所示的重佈線結構120為說明性實例，更多或更少介電層及/或RDL可形成於重佈線結構120中。
在一些實施例中，重佈線結構120以與內連線結構76(參看圖2)類似的方式形成。舉例而言，重佈線結構120可藉由首先在元件封裝100及包封體113上方形成介電層122而形成。在一些實施例中，介電層122由可使用微影技術經圖案化的聚合物形成，所述聚合物可為感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。介電層122可藉由旋轉塗佈、層壓、CVD、類似者或其組合而形成。介電層122隨後經圖案化以形成暴露出元件結構100的穿孔74的開口。可藉由例如根據所需的圖案暴露出介電層122並執行顯影製程以移除不合需要的材料從而暴露出穿孔74來執行圖案化。其他技術(諸如使用經圖案化光罩及蝕刻)亦可用於使介電層122圖案化。
晶種層(圖12中未示出)形成於介電層122上方及介電層122中形成的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者形成晶種層。光罩(圖12中未示出)隨後形成於晶種層上且在晶種層上經圖案化。在一些實施例中，光罩是 藉由旋轉塗佈或類似者形成的光阻，隨後使其暴露於光下以進行圖案化。圖案化形成穿過罩幕的開口以暴露出晶種層。導電材料隨後形成於光罩的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆(如電鍍或無電式鍍覆或類似者)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁、其組合或類似者。隨後，移除光阻以及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程(如使用氧電漿或類似者)移除光阻。一旦移除光阻，則諸如藉由使用可接受的蝕刻製程(諸如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料在重佈線結構120內形成RDL 124。
額外的介電層以及額外的RDL可隨後形成於介電層122及RDL 124上方，以在重佈線結構120內形成額外的電性連接。額外的介電層以及額外的RDL可使用與用於形成介電層122及/或RDL 124類似的材料及製程形成。舉例而言，可利用與介電層122類似的製程且用與介電層122類似的材料形成額外的介電層。可使開口貫穿額外的介電層中的每一者，以暴露出下伏RDL的至少一部分。儘管可替代地使用任何合適的製程，但可使用合適的微影光罩及蝕刻製程(諸如上文針對介電層122描述的那些蝕刻製程)形成開口。在一些實施例中，額外的介電層由感光聚合物形成，並且可使用微影光罩及蝕刻製程使開口直接圖案化於額外的介電層中。
額外的RDL可形成於每一額外的介電層中，以在重佈線結構120內提供額外的電性連接。在實施例中，可使用與RDL 124類似的材料及製程形成額外的RDL。舉例而言，可形成晶種層且 光阻可針對額外的RDL以所需的圖案經放置於晶種層的頂部且在晶種層的頂部經圖案化。導電材料可隨後使用例如鍍覆製程而形成於光阻的經圖案化開口中。可隨後移除光阻且蝕刻晶種層，從而形成額外的RDL。可以此方式自多個介電層以及多個RDL形成重佈線結構120。
轉而參看圖13，自所述結構剝離載板115，從而形成元件結構110。在一些實施例中，元件基底110亦可使用例如鋸切或切割製程經單體化。由於單體化製程，重佈線結構120的外側壁與包封體113的外側壁可共面。
轉而參看圖14，根據一些實施例，繪示元件結構110的平面圖。圖14中所示的元件結構110為代表性的且出於清楚起見未示出一些特徵。圖14的元件結構110繪示使用關於圖13所描述的構想的特定實施例。舉例而言，元件結構110包含元件封裝100A及元件封裝100B，所述元件封裝100A及元件封裝100B可與圖13中所描述的元件封裝100A或元件封裝100B相同或不同。圖14中所示的元件結構110包含兩個元件封裝100A及元件封裝100B，但在其他實施例中，元件結構110可包含三個或大於三個元件封裝100。元件封裝100可在元件結構110內具有任何合適的配置或佈置。
在一些實施例中，在元件結構110內，不同的元件封裝100可藉由重佈線結構120電性連接且每一元件封裝100內的積體電路元件50可藉由元件封裝100的內連線結構76電性連接。此在圖14中示出，其中元件封裝100A的積體電路元件50A藉由元件封裝100A的內連線結構76連接至積體電路元件50B，並且元 件封裝100B的積體電路元件50C藉由元件封裝100B的內連線結構76連接至積體電路元件50D。每一個元件封裝100內的積體電路元件50之間的連接藉由每一個內連線結構76的部分76'繪示於圖14中。實例的部分76'亦示於圖13中，但圖13至圖14中所示的部分76'是示例性的且可與所繪示的不同。如圖14中所示，元件封裝100A藉由重佈線結構120電性連接至元件封裝100B。在圖14中藉由重佈線結構120的部分120'繪示元件封裝100之間的連接。實例部分120'亦示於圖13中，但圖13至圖14中所示的部分120'是說明性的且可與所繪示的不同。
藉由在元件結構110中使用內連線結構76及重佈線結構120兩者，元件結構110可併入有具有多個積體電路元件50的多個元件封裝100。由於使用如上文所描述的多個較小中介層76，因此內連線結構76的導電跡線(例如RDL)可經形成為具有比重佈線結構120的導電跡線(例如RDL)小的特徵尺寸。舉例而言，可以比可用於在重佈線結構120上形成特徵的圖案縮小選項大的圖案縮小使用倍縮光罩形成中介層76上的特徵。舉例而言，內連線結構76的導電跡線可具有在約0.1微米與約3微米之間的線寬且重佈線結構120的導電跡線可具有在約1微米與約20微米之間的線寬。在一些情況下，由於內連線結構76的較小特徵尺寸，因此內連線結構76可具有比重佈線結構120更佳的高頻效能。因此，元件結構110可使用內連線結構76實現積體電路元件50之間的改良式高頻電性連通，對此可能需要更高頻的操作。此外，在較低頻率下的元件封裝100之間的電性連通可為滿足要求的，對此可在不會對效能產生不利影響的情況下使用重佈線結構120。
轉而參看圖15至圖16，在一些實施例中，單個積體電路元件50的功能性可經分離成藉由元件結構110的重佈線層120電性連接的多個積體電路元件50。作為說明性實例，圖15繪示元件封裝100'的示意圖，所述元件封裝100'包含具有多個功能組件51A至51D的單個積體電路元件50'。功能組件51A至51D可為例如模組、電路或類似者或其部分或其組合。所繪示的功能組件51A至51D為示例性的，積體電路元件50可具有比所描述的更多、更少或不同類型的功能組件。如圖15中所示，可在兩個單獨元件封裝100E及元件封裝100F上的兩個較小區域積體電路元件50E與較小區域積體電路元件50F之間劃分積體電路元件50'的功能組件51A至51D，而非在一個元件封裝100'上形成單個較大區域積體電路元件50'。以此方式，如上文所描述，較小區域元件封裝100E及較小區域元件封裝100F的特徵可經形成為具有比較大區域元件封裝100'的特徵小的尺寸。因此，較小的特徵尺寸的一些益處可藉由使用元件結構110內的多個元件封裝100上的多個積體電路元件50而非使用單個元件封裝100上的單個積體電路元件50來達成。在其他實施例中，可將單個積體電路元件50的功能性劃分成多於兩個較小積體電路元件50，因此，相關聯的元件結構110可具有多於兩個元件封裝100。
圖16A至圖22為根據一些實施例的在用於形成封裝結構200(參看圖22)的製程期間的中間步驟的剖面圖。封裝結構200包含電性連接至重佈線結構220的一側的一個或多個元件封裝100以及電性連接至重佈線結構220的同一側的一個或多個電子元件210。在圖16A至圖18中，元件封裝100附接至第一載板202， 電子元件210附接至形成於第一載板202上的導電焊墊208。在圖19至圖20中，所述結構自第一載板202移除且安裝至第二載板222。在圖21至圖22中，重佈線結構220及外部連接件224形成於元件封裝100及電子元件210上方，從而形成封裝結構200。
圖16A至圖16C繪示根據一些實施例的在將元件封裝100及電子元件210附接至第一載板202之前的元件封裝100、電子元件210以及第一載板202。圖16A繪示根據一些實施例的其中黏著劑206形成於元件封裝100的中介層70上方的元件封裝100。元件封裝100可與先前所描述(如圖9中所描述)的元件封裝100類似。黏著劑206可為任何合適的黏著劑、環氧樹脂、晶粒貼合膜(die attach film；DAF)或類似者。
圖16B繪示根據一些實施例的電子元件210。電子元件210可為例如包含一個或多個主動元件及/或一個或多個被動元件(如電容器、電阻器、電感器及類似者)的半導體元件或其他元件。電子元件210可為例如積體被動元件(integrated passive device；IPD)。在一些實施例中，電子元件210是包括電容器(如多層陶瓷電容器(multi-layer ceramic capacitor；MLCC))或類似的被動元件。在一些實施例中，電子元件210可為表面安裝元件(SMD)或類似者。在一些實施例中，電子元件210具有在約50微米與約600微米之間的厚度。電子元件210包含在外部組件與電子元件210之間提供電性連接的一個或多個連接件212。連接件212可為例如導電凸塊、焊墊、導線、焊球或類似者。
圖16C繪示第一載板202，所述第一載板202可為用於後續處理的合適支撐結構。第一載板202可為玻璃載板基底、陶 瓷載板基底、晶圓、面板或類似者。第一載板202可為晶圓，以使多個封裝可同時形成於載板202上。離型層204可形成於第一載板202上。離型層204可由聚合物類材料形成，所述離型層204可與第一載板202一起自將在後續步驟中形成的上覆結構移除。在一些實施例中，離型層204為在加熱時損失其黏著特性的環氧類熱離型材料，諸如光-熱轉換(LTHC)離型塗層。在其他實施例中，離型層204可為在暴露於UV光時損失其黏著特性的紫外線(UV)黏膠。離型層204可作為液體被點膠為且經固化，可為層壓於第一載板202上的層壓膜、DAF或類似者。可使離型層204的頂表面齊平且所述頂表面可具有高度平面性。
仍然參看圖16C，導電連接件208可形成於離型層204上方。導電連接件208可為導電焊墊、凸塊、柱或類似者，隨後連接至電子元件210的連接件212以向電子元件210提供電性連接。在一些實施例中，導電連接件208可藉由將晶種層(未示出)沉積於釋放層204上方來形成。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者形成晶種層。光阻形成於晶種層上且在晶種層上圖案化。光阻可藉由旋轉塗佈或類似者來形成，可使其暴露於光下以進行圖案化。光阻的圖案對應於導電通孔。圖案化形成穿過光阻的開口以暴露出晶種層。導電材料形成於光阻的開口中以及晶種層的暴露部分上。導電材料可藉由鍍覆(如電鍍或無電式鍍覆或類似者)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁、其組合或類似者。移除光阻以及晶種層上未形成導電材 料的部分。可藉由可接受的灰化或剝離製程(如使用氧電漿或類似者)移除光阻。一旦移除光阻，則如藉由使用可接受的蝕刻製程(如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成導電連接件208。
轉而參看圖17，根據一些實施例，元件封裝100及電子元件210附接至第一載板202。圖17繪示附接至第一載板202的單個元件封裝100以及兩個電子元件210，但在其他實施例中可附接多於一個元件封裝或更多或更少電子元件210。附接至第一載板202的電子元件210可為類似的電子元件或可為不同的電子元件。
可使用例如取放工具將元件封裝100及電子元件210放置於第一載板202上。元件封裝100可藉由黏著劑206附接至第一載板202上的離型層204。電子元件210可藉由導電連接件208附接至第一載板202。在一些實施例中，電子元件210可例如藉由按順序將電子元件210的連接件212浸於焊接材料及/或焊劑材料中，隨後使用取放工具以在物理上將連接件212與導電連接件208對準而附接至導電連接件208。在一些實施例中，在放置電子元件210之前可先將焊接材料(例如焊錫膏)塗覆於導電連接件208。在一些情況下，在放置電子元件210之後，可執行回焊以將連接件212接合至導電連接件208。
在一些情況下，藉由以此方式將電子元件210附接至第一載板202，電子元件210可更接近最終封裝結構200(參看圖22)中的元件封裝100定位。舉例而言，在一些實施例中，電子元件210可以在約300微米與約30,000微米之間的距離D與元件封裝100分離。藉由將電子元件定位為更接近元件封裝100，可減小電 阻且可改良元件效能，尤其是對於高頻下的操作。此外，藉由將電子元件210附接至第一載板，可在同一封裝結構200中使用具有多個厚度的多個電子元件210，而不增加封裝結構200的總厚度。電子元件210亦可藉由包封體214(參看圖18)保護，所述包封體214可提高元件可靠性。
在圖18中，包封體214形成於所述結構的各種組件上。包封體214可為模塑化合物、環氧樹脂或類似者，並且可藉由壓縮模塑、轉移模塑或類似者而塗覆。包封體214可形成於元件封裝100及電子元件210上方，以使元件封裝100及電子元件210由包封體214包圍及覆蓋。可隨後固化包封體214。在一些實施例中，移除(例如藉由CMP)包封體214的過量材料，此亦可平坦化所述結構的頂部，而使包封體214的頂表面與元件封裝100的頂表面齊平。
在圖19中，執行載板剝離以將第一載板202自所述結構脫離(剝離)，隨後將所述結構附接至第二載板222。根據一些實施例，剝離包含將光(如雷射光或紫外(UV)光)照射於離型層204上，以使得離型層204在光熱下分解且可移除第一載板202。所述結構隨後翻轉且附接至第二載板222。第二載板222可與諸如包括玻璃載板基底、陶瓷載板基底、晶圓、面板或類似者的第一載板202類似。離型層223可形成於第二載板222上，且所述結構可附接至離型層223。離型層223可為例如DAF或類似者，或可與上文所描述的離型層204類似。
在圖20中，根據一些實施例，對所述結構的底部執行平坦化製程。平坦化製程可為例如CMP。在一些實施例中，平坦化 製程可移除黏著劑206且可暴露出導電連接件208及元件封裝100的穿孔74。在一些情況下，平坦化製程亦可平坦化所述結構，以使包封體214的底部表面與元件封裝100的底部表面齊平。
在圖21中，根據一些實施例，重佈線結構220形成於所述結構的底部上方。重佈線結構220在電子元件210、元件封裝100與外部組件之間提供電性互連。重佈線結構220包含介電層226、介電層228及介電層230，並且包含金屬化圖案232及金屬化圖案234。金屬化圖案亦可稱為重佈線層(RDL)或重佈線。重佈線結構220繪示為具有兩個金屬化圖案層的實例。更多或更少的介電層及金屬化圖案可形成於重佈線結構220中。若將形成更少的介電層及金屬化圖案，則可省略下文所論述的步驟及製程。若將形成更多的介電層及金屬化圖案，則可重複下文所論述的步驟及製程。
在圖21中，介電層226沉積於包封體214、穿孔74及導電連接件208上。在一些實施例中，介電層226由感光性材料(如PBO、聚醯亞胺、BCB或類似者)形成，所述感光性材料可使用光罩經圖案化。介電層226可藉由旋轉塗佈、層壓、CVD、類似者或其組合而形成。介電層226隨後經圖案化。圖案化形成暴露出穿孔74及導電連接件208的部分的開口。可藉由可接受的製程(如藉由當介電層226為感光性材料時將介電層226暴露於光或藉由使用例如非等向性蝕刻來進行蝕刻)來進行圖案化。若介電層226為感光性材料，則介電層226可在曝光之後顯影。
根據一些實施例，隨後形成金屬化圖案232。金屬化圖案232包含在介電層226的主表面上且沿著所述主表面延伸的線部 分(亦稱為導電線)。金屬化圖案232更包含延伸穿過介電層226的通孔部分(亦稱為導電通孔)以物理耦接且電性耦接穿孔74以及導電連接件208。作為形成金屬化圖案232的實例，晶種層形成於介電層226上方以及延伸穿過介電層226的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及在鈦層上方的銅層。可使用例如PVD或類似者形成晶種層。光阻隨後形成於晶種層上且在晶種層上經圖案化。光阻可藉由旋轉塗佈或類似者來形成且可使其暴露於光下以進行圖案化。光阻的圖案對應於金屬化圖案232。圖案化形成穿過光阻的開口以暴露出晶種層。導電材料隨後形成於光阻的開口中及晶種層的暴露部分上。導電材料可藉由鍍覆(如電鍍或無電式鍍覆或類似者)形成。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。導電材料及晶種層的下伏部分的組合形成金屬化圖案232。移除光阻以及晶種層上未形成導電材料的部分。可藉由可接受的灰化或剝離製程(如使用氧電漿或類似者)移除光阻。一旦移除光阻，則如藉由使用可接受的蝕刻製程(如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露部分。
在形成金屬化圖案232之後，介電層228沉積於金屬化圖案232及介電層226上。介電層228可以與介電層226類似的方式形成及經圖案化，且可由與介電層226類似的材料形成。
根據一些實施例，隨後形成金屬化圖案234。金屬化圖案234包含在介電層228的主表面上且沿著所述主表面延伸的線部分。金屬化圖案234更包含延伸穿過介電層228以物理耦接且電 性耦接金屬化圖案232的通孔部分。金屬化圖案234可以與金屬化圖案232類似的方式且由與所述金屬化圖案232類似的材料形成。在一些實施例中，金屬化圖案234具有與金屬化圖案232不同的尺寸。舉例而言，金屬化圖案234的導電線及/或通孔可比金屬化圖案232的導電線及/或通孔更寬或更厚。另外，金屬化圖案234可形成為比金屬化圖案232更大的節距。
介電層230沉積於金屬化圖案234及介電層228上。介電層230可以與介電層228類似的方式形成，並且可由與介電層226相同的材料形成。介電層230為重佈線結構220的最頂部介電層。同樣，重佈線結構220的所有金屬化圖案(例如金屬化圖案232及金屬化圖案234)安置於介電層230與元件封裝100之間。另外，重佈線結構220的所有中間介電層(例如介電層226及介電層228)安置於介電層230與元件封裝100之間。
在一些實施例中，形成用於外部連接至重佈線結構220的UBM 236。UBM 236可包含在介電層230的主表面上且沿著所述主表面延伸的導電部分。UBM 236更包含延伸穿過介電層230以物理連接且電性連接至金屬化圖案234的導電通孔。UBM 236可由與金屬化圖案232相同的材料或由不同材料形成。舉例而言，UBM 236可包含銅或銅合金。然而，亦可包含其他金屬，如鈦、鎳、鈀、銀、金、鋁、其組合及其多層。可使用濺鍍、電鍍或類似者形成UBM 236。在一些實施例中，UBM 236具有與金屬化圖案232或金屬化圖案234不同的尺寸。
在一些情況下，藉由形成如所描述的重佈線結構220，多個電子元件210可在不使用單獨的中介層或基底的情況下連接至 至少一個元件封裝100。此外，使用重佈線結構220允許封裝在無額外的接合步驟(例如將元件封裝100摩擦接合至中介層)、底膠沉積或其他相關處理步驟的情況下包含組件(如元件封裝100或電子元件210)。以此方式，可降低用於形成封裝的製程步驟的成本且減少所述製程步驟的數目。此外，在處理期間使用兩個載板(例如載板202及載板222)可減少所述結構在處理期間的翹曲量。
在圖22中，外部連接件224形成於UBM 138上。外部連接件224可為球柵陣列封裝(ball grid array；BGA)連接件、焊球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微凸塊、無電鍍鎳-無電鈀-浸鍍金(electroless nickel-electroless palladium-immersion gold；ENEPIG)技術形成的凸塊或類似者。外部連接件224可包含導電材料，如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，外部連接件224藉由經由蒸鍍、電鍍、印刷、焊料轉移、植球或類似者先形成焊料層而形成。一旦焊料層形成於結構上，可執行回焊以將材料塑形成所需凸塊形狀。在另一實施例中，外部連接件224包括藉由濺鍍、印刷、電鍍、無電式鍍覆、CVD或類似者形成的金屬柱(如銅柱)。金屬柱可不含焊料且具有實質上豎直的側壁。在一些實施例中，金屬頂蓋層形成於金屬柱的頂部。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其組合且可藉由鍍覆製程形成。
仍然參看圖22，執行載板剝離以將第二載板222自所述結構脫離(剝離)，從而形成封裝結構200。根據一些實施例，剝離包含將光(如雷射光或紫外(UV)光)照射於離型層223上， 以使得離型層223在光熱下分解且可移除第二載板222。所述結構可隨後翻轉且經放置於載帶(未示出)上。所述結構可隨後經單體化以形成封裝結構200。單體化可藉由鋸切、切割或類似者來進行。由於單體化製程，重佈線結構220的邊緣與包封體214的邊緣可共面。
以此方式，可在不增加封裝結構200的總厚度的情況下形成具有帶不同厚度的電子元件210的封裝結構200。此外，藉由形成具有如本文中所描述的重佈線結構220的封裝結構200，可在不使用額外的中介層或基底的情況下形成封裝結構200，此可降低製造成本且減少處理步驟的數目。
圖23A至圖28為根據一些實施例的在用於形成封裝結構300(參看圖28)的製程期間的中間步驟的剖面圖。除了不使用黏著劑206及導電連接件208之外，封裝結構300與封裝結構200類似。以此方式，用於形成封裝結構300的處理步驟可少於用於形成封裝結構300的那些處理步驟。封裝結構300包含電性連接至重佈線結構220的一側的一個或多個元件結構110及電性連接至重佈線結構220的同一側的一個或多個電子元件210。雖然在圖23A至圖28中所描述的封裝結構300經繪示為使用元件結構110(參看圖14)，但在其他實施例中，替代元件結構110或除了元件結構110以外，封裝結構300可使用元件封裝100(參看圖9)。在圖23A至圖25中，元件結構110及電子元件210附接至第一載板202。在圖26中，所述結構自第一載板202移除且安裝至第二載板222。在圖27至圖28中，重佈線結構220及外部連接件224形成於元件結構110及電子元件210上方，從而形成封裝結構300。
圖23A至圖23C繪示根據一些實施例的在將元件結構110及電子元件210附接至第一載板202之前的元件結構110、電子元件210以及第一載板202。圖23A繪示可與先前所描述(如圖14中所描述)的元件結構110類似的元件結構110。圖16B繪示可與先前所描述的電子元件210類似的電子元件210。電子元件210包含在外部組件與電子元件210之間提供電性連接的一個或多個連接件212。圖16C繪示第一載板202，所述第一載板202可為用於後續處理的合適支撐結構。第一載板202可與先前所描述的第一載板202類似。離型層204可形成於第一載板202上，所述離型層204可與先前所描述的離型層204類似。
轉而參看圖24，根據一些實施例，元件結構110及電子元件210附接至第一載板202。圖24繪示附接至第一載板202的單個元件結構110及兩個電子元件210，但在其它實施例中可附接一個或多個元件結構110、一個或多個元件封裝100及/或一個或多個電子元件210。如圖24中所示，附接至第一載板202的電子元件210可為類似的電子元件或可為不同的電子元件且可具有不同厚度。可使用例如取放工具將元件結構110及電子元件210放置於第一載板202上。
在一些情況下，藉由以此方式將電子元件210附接至第一載板202，電子元件210可更接近最終封裝結構300(參看圖28)中的元件結構110定位。藉由將電子元件定位為更接近元件結構110，可減小電阻且可改良元件效能，尤其是對於高頻下的操作。此外，藉由將電子元件210附接至第一載板，可使用具有不同尺寸或不同高度的電子元件210，而不增加最終封裝結構300的總厚 度。電子元件210亦可藉由包封體214(參看圖25)保護，所述包封體214可提高元件可靠性。
在圖25中，包封體214形成於所述結構的各種組件上。包封體214可為模塑化合物、環氧樹脂或類似者，並且可藉由壓縮模塑、轉移模塑或類似者而塗覆。包封體214可形成於元件結構110及電子元件210上方，以使元件結構110及電子元件210由包封體214包圍及覆蓋。可隨後固化包封體214。在一些實施例中，移除(例如藉由CMP)包封體214的過量材料，亦可平坦化所述結構的頂部，而使包封體214的頂表面與元件結構110的頂表面齊平。
在圖26中，執行載板剝離以將第一載板202自所述結構脫離(剝離)，隨後將所述結構附接至第二載板222。根據一些實施例，剝離包含將光(如雷射光或紫外(UV)光)照射於離型層204上，以使離型層204在光熱下分解且可移除第一載板202。所述結構隨後翻轉且附接至第二載板222。第二載板222可與先前所描述的第一載板202或第二載板222類似。離型層223可形成於第二載板222上且所述結構可附接至離型層223。離型層223可為例如DAF或類似者，或可與上文所描述的離型層223類似。
在圖27中，根據一些實施例，重佈線結構220形成於所述結構的底部上方。重佈線結構220在電子元件210、元件結構110與外部組件之間提供電性互連。重佈線結構220可與先前在圖21中所描述的重佈線結構220類似且可以類似方式形成。舉例而言，圖27中所示的重佈線結構220包含介電層226、介電層228及介電層230，並且包含金屬化圖案23及金屬化圖案234。更多 或更少的介電層及金屬化圖案可形成於重佈線結構220中。在一些實施例中，形成用於外部連接至重佈線結構220的UBM 236，所述UBM 236可與先前所描述的UBM 236類似。
在一些情況下，藉由形成如所描述的重佈線結構220，多個電子元件210可在不使用單獨中介層或基底的情況下連接至至少一個元件結構110。此外，使用重佈線結構220允許封裝在無額外的接合步驟(例如將元件結構110或元件封裝100接合至中介層)、底膠沉積或其他相關處理步驟的情況下包含組件(例如元件結構110、元件封裝100及/或電子元件210)。以此方式，可降低用於形成封裝的製程步驟的成本且減少所述製程步驟。此外，在處理期間使用兩個載板(例如載板202及載板222)可減少所述結構在處理期間的翹曲量。
在圖28中，外部連接件224形成於UBM 236上。外部連接件224可與先前所描述的外部連接件224類似。仍然參看圖28，執行載板剝離以將第二載板222自所述結構脫離(剝離)，從而形成封裝結構300。根據一些實施例，剝離包含將光(如雷射光或紫外(UV)光)照射於離型層223上，以使得離型層223在光熱下分解且可移除第二載板222。所述結構可隨後翻轉且經放置於載帶(未示出)上。所述結構可隨後經單體化以形成封裝結構300。單體化可藉由鋸切、切割或類似者來進行。由於單體化製程，重佈線結構220的邊緣與包封體214的邊緣可共面。
以此方式，可在不增加封裝結構300的總厚度的情況下形成具有帶不同厚度的電子元件210的封裝結構300。此外，藉由形成具有如本文中所描述的重佈線結構220的封裝結構300，可在 不使用額外中介層或基底的情況下形成封裝結構300，此可降低製造成本且減少處理步驟。此外，可在不包含導電連接件208或黏著劑206的情況下形成封裝結構300，從而進一步降低處理成本且減少步驟。
轉而參看圖29，根據一些實施例，繪示封裝結構400。封裝結構400包含藉由連接件404接合至IC基底402的元件結構110。元件結構110可與先前所描述的元件結構(如圖13中所描述的元件結構)類似。IC基底402可為塊狀半導體基底、SOI基底、多層半導體基底或類似者。IC基底402的半導體材料可為矽、鍺、化合物半導體包含矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦、合金半導體包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、其組合或類似者。亦可使用其他基底，諸如多層基底或梯度基底。IC基底402可經摻雜或未經摻雜。元件(如電晶體、電容器、電阻器、二極體以及類似者)可形成於IC基底402的表面中及/或表面上。舉例而言，IC基底402可為其中已形成積體電路(IC)且所述積體電路藉由連接件404電性連接至元件結構110的半導體基底、晶片、晶粒或類似者。在一些實施例中，IC基底402基於諸如玻璃纖維強化樹脂芯的絕緣芯。舉例而言，芯材料可為玻璃纖維樹脂，諸如FR-4、BT樹脂、其他PCB材料或膜、組合或類似者。增層膜(如ABF)或其他層壓物可用於IC基底402。
在一些實施例中，連接件404形成於元件結構110的重佈線結構120上，隨後元件結構110經放置於IC基底402上，以使連接件404形成與IC基底402上的對應導電特徵的電性連接及 物理連接。連接件404可與先前所描述的連接件224類似且可以類似方式形成。在一些情況下，在放置元件結構110之後，可執行回焊以將連接件404接合至IC基底402上的對應導電特徵。在將元件結構110接合至IC基底402之後，可將底膠406沉積於元件結構110與IC基底402之間。
在一些實施例中，一個或多個電子元件(圖29中未示出)亦可連接至IC基底402。電子元件可與先前所描述的電子元件210類似。電子元件可連接至IC基底402的一側或兩側。舉例而言，電子元件可在與元件結構110相同的一側附接至IC基底402。
實施例可實現優點。藉由用由重佈線結構連接的多個元件封裝來形成元件結構，每一元件封裝的尺寸可減小，從而使得元件封裝可經形成為具有較精細特徵。舉例而言，每一元件封裝的中介層內的金屬化可經形成為具有較大密度及較小線寬，此可改良在高頻率下的效能。在一些情況下，可將單個積體電路元件的功能性分離成多個元件封裝，由於每一元件封裝的較小尺寸，此可實現如所描述的經改良的金屬化及經改良的效能。在一些情況下，可在形成元件結構之前單獨地電測試積體電路元件，此可提高良率。藉由使用雙載板製程形成封裝結構，具有不同厚度的電子組件(如SMD)可併入相同封裝結構內。此外，可使用重佈線結構，而非封裝結構內的中介層，此可降低成本及減少處理步驟。
在實施例中，一種方法包含：形成元件結構，此包含將第一晶粒連接至第一中介層；將第二晶粒連接至第二中介層；以及在第一中介層及第二中介層上方形成第一重佈線結構，其中第 一重佈線結構將第一中介層電性連接至第二中介層；及形成封裝結構，此包含將第一表面安裝元件(SMD)及元件結構附接至第一載板；用第一包封體包封第一SMD及元件結構，以形成具有頂表面及底表面的包封結構；將包封結構的頂表面附接至第二載板；以及在包封結構的底表面上方形成第二重佈線結構，其中第二重佈線結構電性連接第一SMD及元件結構。在實施例中，形成封裝結構更包含將第二SMD附接至第一載板，其中第二SMD具有與第一SMD不同的厚度。在實施例中，所述方法更包含平坦化包封結構，其中在平坦化包封結構之後，第一晶粒的頂表面與第一包封體的頂表面齊平。在實施例中，形成元件結構更包含用第二包封體包封第一中介層及第二中介層，其中第一重佈線結構在第二包封體上方延伸。在實施例中，第一SMD的厚度小於包封結構的厚度。在實施例中，所述方法更包含在將第一晶粒連接至第一中介層之後，在將第一重佈線結構形成於第一中介層上方之前電測試第一晶粒。在實施例中，第二重佈線結構的側壁與包封結構的側壁共面。在實施例中，所述方法更包含在第二重佈線結構上形成外部連接件。
在實施例中，一種方法包含：將半導體元件附接至中介層結構；將中介層結構附接至第一載板基底；將積體被動元件附接至第一載板基底；在半導體元件及積體被動元件上方形成包封體；剝離第一載板基底；將包封體及半導體元件附接至第二載板基底；在包封體、中介層結構以及積體被動元件上形成第一重佈線結構，其中第一重佈線結構接觸中介層結構及積體被動元件；以及在第一重佈線結構上形成外部連接件。在實施例中，所述方 法更包含在中介層結構上形成第二重佈線結構，其中第二重佈線結構附接至第一載板基底。在實施例中，所述方法更包含在中介層結構上形成內連線結構，其中半導體元件附接至內連線結構。在實施例中，所述方法更包含在將中介層結構附接至第一載板基底之前在半導體元件上方形成包封體。在實施例中，所述方法更包含在第一載板基底上形成導電連接件，其中積體被動元件附接至第一載板基底。在實施例中，將中介層結構附接至第一載板基底包含在中介層結構上形成黏著劑並使用黏著劑將中介層結構附接至第一載板基底。在實施例中，積體被動元件藉由包封體與中介層結構分離。
在實施例中，一種封裝包含元件基底及附接至元件基底的第一側的元件結構，元件結構包含第一中介層、第二中介層、附接至第一中介層的第一半導體元件、附接至第二中介層的第二半導體元件以及連接至第一中介層及第二中介層的第一重佈線結構。在實施例中，元件基底包含積體電路。在實施例中，元件基底是第二重佈線結構。在實施例中，元件結構更包含附接至元件基底的第一側的表面安裝元件(SMD)。在實施例中，所述封裝更包含覆蓋SMD且包圍元件結構的包封體材料。
前文概述若干實施例的特徵，使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離 本揭露的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
50A、50B:積體電路元件
100:元件封裝
200:封裝結構
210:電子元件
214:包封體
220:重佈線結構
224:外部連接件
236:凸塊下金屬(UBM)

Claims (10)

  1. 一種封裝的製造方法，包括：形成元件結構，包括：將第一晶粒連接至第一中介層；將第二晶粒連接至第二中介層；以及在所述第一中介層及所述第二中介層上方形成第一重佈線結構，其中所述第一重佈線結構將所述第一中介層電性連接至所述第二中介層；以及形成封裝結構，包括：將第一表面安裝元件及所述元件結構附接至第一載板；於所述第一載板上用第一包封體包封所述第一表面安裝元件及所述元件結構，以形成具有頂表面及底表面的包封結構；剝離所述第一載板以暴露出所述包封結構的所述底表面；在剝離所述第一載板之後，將所述包封結構的所述頂表面附接至第二載板；以及在所述包封結構的所述底表面上方形成第二重佈線結構，其中所述第二重佈線結構電性連接所述第一表面安裝元件及所述元件結構。
  2. 如申請專利範圍第1項所述封裝的製造方法，其中形成所述封裝結構更包括將第二表面安裝元件附接至所述第一載板，其中所述第二表面安裝元件具有與所述第一表面安裝元件不同的 厚度。
  3. 如申請專利範圍第1項所述封裝的製造方法，其中形成元件結構更包括用第二包封體包封所述第一中介層及所述第二中介層，其中所述第一重佈線結構在所述第二包封體上方延伸。
  4. 如申請專利範圍第1項所述封裝的製造方法，更包括在將所述第一晶粒連接至所述第一中介層之後，在將第一重佈線結構形成於所述第一中介層上方之前，電性測試所述第一晶粒。
  5. 如申請專利範圍第1項所述封裝的製造方法，其中所述第二重佈線結構的側壁與所述包封結構的側壁共面。
  6. 一種封裝的製造方法，包括：將多個半導體元件附接至中介層結構；將所述中介層結構附接至第一載板基底；將多個積體被動元件附接至所述第一載板基底；在所述第一載板基底上形成包封體以包封所述半導體元件及所述積體被動元件；在形成所述包封體之後，剝離所述第一載板基底；在剝離所述第一載板基底之後，將所述包封體及所述半導體元件附接至第二載板基底，其中所述包封體、所述半導體元件及包封所述半導體元件的內部包封體的附接至所述第二載板基底的表面彼此齊平的；在所述包封體、所述中介層結構及所述積體被動元件上形成第一重佈線結構，其中所述第一重佈線結構接觸所述中介層結構及所述積體被動元件；以及在所述第一重佈線結構上形成多個外部連接件。
  7. 如申請專利範圍第6項所述封裝的製造方法，更包括在所述中介層結構上形成第二重佈線結構，其中所述第二重佈線結構附接至所述第一載板基底。
  8. 如申請專利範圍第6項所述封裝的製造方法，更包括在所述中介層結構上形成內連線結構，其中所述半導體元件附接至所述內連線結構。
  9. 一種使用如申請專利範圍第1-5項中任一項所述之製造方法所製造的封裝。
  10. 一種使用如申請專利範圍第6-8項中任一項所述之製造方法所製造的封裝。
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