JP5703010B2 - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
- Publication number
- JP5703010B2 JP5703010B2 JP2010280951A JP2010280951A JP5703010B2 JP 5703010 B2 JP5703010 B2 JP 5703010B2 JP 2010280951 A JP2010280951 A JP 2010280951A JP 2010280951 A JP2010280951 A JP 2010280951A JP 5703010 B2 JP5703010 B2 JP 5703010B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor package
- layer
- semiconductor chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
- H01L2224/221—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
[第1の実施の形態に係る半導体パッケージの構造]
図1は、第1の実施の形態に係る半導体パッケージを例示する断面図である。図1を参照するに、半導体パッケージ10は、半導体チップ20と、樹脂部30と、配線構造40と、反り防止部材50とを有する。
続いて、第1の実施の形態に係る半導体パッケージの製造方法について説明する。図3〜図11は、第1の実施の形態に係る半導体パッケージの製造工程を例示する断面図である。図3〜図11において、図1と同一部分については、同一符号を付し、その説明は省略する場合がある。また、図3〜図11におけるEは、図11に示す工程の後、図11に示す構造体を切断する位置を示している。
第2の実施の形態では、反り防止部材として、電気的に機能するチップが設けられている例を示す。第2の実施の形態において、第1の実施の形態と共通する部分についてはその説明を省略し、第1の実施の形態と異なる部分を中心に説明する。
図15は、第2の実施の形態に係る半導体パッケージを例示する断面図である。図15を参照するに、半導体パッケージ10Aは、反り防止部材として電子部品が用いられ、具体的には、チップ50Aがフェイスダウンの状態で設けられている点が、図1に示す半導体パッケージ10と異なる。以下、半導体パッケージ10Aについて、半導体パッケージ10と同一構造部分については説明を省略し、半導体パッケージ10と異なる部分を中心に説明をする。
第2の実施の形態に係る半導体パッケージの製造方法は、図7〜図11を除き、図3〜図11を用いて説明した第1の実施の形態に係る半導体パッケージの製造方法と同様であり、同様の工程についての説明を省略する。
第3の実施の形態では、第2の実施の形態でフェイスダウンの状態で設けられていたチップが、フェイスアップの状態で設けられている例を示す。第3の実施の形態において、第1の実施の形態と共通する部分についてはその説明を省略し、第1の実施の形態と異なる部分を中心に説明する。
図21は、第3の実施の形態に係る半導体パッケージを例示する断面図である。図21を参照するに、半導体パッケージ10Bは、反り防止部材として、チップ50Bがフェイスアップの状態で設けられている点が、図1に示す半導体パッケージ10と異なる。以下、半導体パッケージ10Bについて、半導体パッケージ10と同一構造部分については説明を省略し、半導体パッケージ10と異なる部分を中心に説明をする。
第3の実施の形態に係る半導体パッケージの製造方法は、図9〜図11を除き、図3〜図11を用いて説明した第1の実施の形態に係る半導体パッケージの製造方法と同様であり、同様の工程についての説明を省略する。
第4の実施の形態では、第1の実施の形態に係る半導体パッケージにおいて、配線構造と反対側の面に、第1配線層と電気的に接続された電極端子が設けられている例を示す。第4の実施の形態において、第1の実施の形態と共通する部分についてはその説明を省略し、第1の実施の形態と異なる部分を中心に説明する。
図25は、第4の実施の形態に係る半導体パッケージを例示する断面図である。図25を参照するに、半導体パッケージ10Cは、第1配線層41と電気的に接続された電極端子31が設けられている点が、図1に示す半導体パッケージ10と異なる。以下、半導体パッケージ10Cについて、半導体パッケージ10と同一構造部分については説明を省略し、半導体パッケージ10と異なる部分を中心に説明をする。
続いて、第4の実施の形態に係る半導体パッケージの製造方法について説明する。図26〜図34は、第4の実施の形態に係る半導体パッケージの製造工程を例示する断面図である。図26〜図34において、図25と同一部分については、同一符号を付し、その説明は省略する場合がある。また、図26〜図34におけるEは、図34に示す工程の後、図34に示す構造体を切断する位置を示している。
第5の実施の形態では、第2の実施の形態に係る半導体パッケージにおいて、配線構造と反対側の面に、第1配線層と電気的に接続された電極端子が設けられている例を示す。第5の実施の形態において、第2の実施の形態と共通する部分についてはその説明を省略し、第2の実施の形態と異なる部分を中心に説明する。
第6の実施の形態では、第3の実施の形態に係る半導体パッケージにおいて、配線構造と反対側の面に、第1配線層と電気的に接続された電極端子が設けられている例を示す。第6の実施の形態において、第3の実施の形態と共通する部分についてはその説明を省略し、第3の実施の形態と異なる部分を中心に説明する。
20 半導体チップ
30 樹脂部
40 配線構造
41〜43 配線層
44、45 絶縁層
46 ソルダーレジスト層
50 反り防止部材
50A、50B チップ
60 支持体
Claims (6)
- 半導体チップと、
前記半導体チップを覆うように形成された樹脂部と、
前記半導体チップの回路形成面側の前記樹脂部上に形成されており、配線層と絶縁層とを積層した配線構造と、
前記配線構造の前記絶縁層内であって、かつ、前記半導体チップと対向する領域に設けられており、前記配線構造の熱膨張係数よりも前記半導体チップの熱膨張係数に近い熱膨張係数を有する反り防止部材と、
を有し、
前記配線層は前記半導体チップの電極パッドと直接接続され、
前記反り防止部材は、前記配線層から電気的に独立しており、
前記反り防止部材は、シリコン、ガラス、セラミック、化合物半導体の何れかよりなる半導体パッケージ。 - 前記配線構造は、複数の配線層と複数の絶縁層とを有し、前記配線層と、前記絶縁層とが交互に積層された構造を有し、
前記反り防止部材は前記半導体チップから最も離れた絶縁層内に配置されている請求項1に記載の半導体パッケージ。 - 前記反り防止部材は、前記配線構造のヤング率よりも高いヤング率を有する、請求項1または2に記載の半導体パッケージ。
- 支持体上に半導体チップを配置する第1工程と、
前記半導体チップが配置された前記支持体上に、前記半導体チップを覆うように樹脂部を形成する第2工程と、
前記半導体チップの回路形成面側の前記樹脂部上に、前記半導体チップの電極パッドと直接接続される配線層を形成する第3工程と、
前記樹脂部及び前記配線層上に、絶縁層及び配線層を所定の層数積層する第4工程と、
前記絶縁層上であって、前記半導体チップと対向する領域に反り防止部材を設ける第5工程と、
前記第4工程で形成した絶縁層及び配線層と、前記反り防止部材と、を覆うように、絶縁層及び配線層を所定の層数積層する第6工程と、
前記支持体を除去する第7工程と、を有し、
前記反り防止部材は、前記第3工程で形成した配線層と、前記第4工程及び前記第6工程で形成した絶縁層及び配線層と、を含む配線構造の熱膨張係数よりも、前記半導体チップの熱膨張係数に近い熱膨張係数を有し、
前記反り防止部材は、前記配線構造に含まれる配線層から電気的に独立しており、
前記反り防止部材は、シリコン、ガラス、セラミック、化合物半導体の何れかよりなる半導体パッケージの製造方法。 - 前記配線構造は、複数の配線層と複数の絶縁層とを有し、前記配線層と、前記絶縁層とが交互に積層された構造を有し、
前記反り防止部材は前記半導体チップから最も離れた絶縁層内に配置されている請求項4に記載の半導体パッケージの製造方法。 - 前記反り防止部材は、前記配線構造のヤング率よりも高いヤング率を有する、請求項4または5に記載の半導体パッケージの製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010280951A JP5703010B2 (ja) | 2010-12-16 | 2010-12-16 | 半導体パッケージ及びその製造方法 |
US13/326,502 US9299678B2 (en) | 2010-12-16 | 2011-12-15 | Semiconductor package and manufacturing method therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010280951A JP5703010B2 (ja) | 2010-12-16 | 2010-12-16 | 半導体パッケージ及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2012129419A JP2012129419A (ja) | 2012-07-05 |
JP2012129419A5 JP2012129419A5 (ja) | 2013-10-24 |
JP5703010B2 true JP5703010B2 (ja) | 2015-04-15 |
Family
ID=46233343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010280951A Active JP5703010B2 (ja) | 2010-12-16 | 2010-12-16 | 半導体パッケージ及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9299678B2 (ja) |
JP (1) | JP5703010B2 (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6295206B2 (ja) * | 2012-12-11 | 2018-03-14 | 三井金属鉱業株式会社 | 多層プリント配線板及びその製造方法 |
US9155191B2 (en) * | 2013-05-31 | 2015-10-06 | Qualcomm Incorporated | Substrate comprising inorganic material that lowers the coefficient of thermal expansion (CTE) and reduces warpage |
KR20150028031A (ko) * | 2013-09-05 | 2015-03-13 | 삼성전기주식회사 | 인쇄회로기판 |
KR20170121171A (ko) * | 2015-02-26 | 2017-11-01 | 히타치가세이가부시끼가이샤 | 봉지용 필름 및 이것을 사용한 전자 부품 장치 |
JP6593676B2 (ja) * | 2015-03-02 | 2019-10-23 | 日本電気硝子株式会社 | 積層体及び半導体パッケージの製造方法 |
US9613931B2 (en) * | 2015-04-30 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) having dummy dies and methods of making the same |
DE102015120745B4 (de) * | 2015-11-30 | 2021-12-09 | Infineon Technologies Austria Ag | Chip-Schutzumhüllung und -verfahren |
JP2017162989A (ja) * | 2016-03-09 | 2017-09-14 | イビデン株式会社 | 電子部品内蔵基板およびその製造方法 |
CN109844937B (zh) * | 2016-08-12 | 2023-06-27 | Qorvo美国公司 | 具有增强性能的晶片级封装 |
JP6735505B2 (ja) * | 2016-09-06 | 2020-08-05 | パナソニックIpマネジメント株式会社 | プリント配線板、プリント回路板、プリプレグ |
KR102397905B1 (ko) * | 2017-12-27 | 2022-05-13 | 삼성전자주식회사 | 인터포저 기판 및 반도체 패키지 |
JP2019121733A (ja) * | 2018-01-10 | 2019-07-22 | 東京応化工業株式会社 | 積層体の製造方法、積層体、及び電子装置の製造方法 |
US11152363B2 (en) | 2018-03-28 | 2021-10-19 | Qorvo Us, Inc. | Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process |
KR102609445B1 (ko) | 2018-10-22 | 2023-12-04 | 삼성전자주식회사 | 반도체 패키지 |
US11646242B2 (en) | 2018-11-29 | 2023-05-09 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US20200235040A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11387157B2 (en) | 2019-01-23 | 2022-07-12 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11923313B2 (en) | 2019-01-23 | 2024-03-05 | Qorvo Us, Inc. | RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same |
US20200235066A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
JP6864875B2 (ja) | 2019-08-30 | 2021-04-28 | 日亜化学工業株式会社 | 発光モジュール及びその製造方法 |
US11251100B2 (en) * | 2019-09-25 | 2022-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure |
US11362010B2 (en) * | 2019-10-16 | 2022-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of chip package with fan-out feature |
US11646289B2 (en) | 2019-12-02 | 2023-05-09 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
CN113140520A (zh) * | 2020-01-19 | 2021-07-20 | 江苏长电科技股份有限公司 | 封装结构及其成型方法 |
IT202200008891A1 (it) * | 2022-05-03 | 2023-11-03 | St Microelectronics Srl | Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003049184A1 (en) * | 2001-12-07 | 2003-06-12 | Fujitsu Limited | Semiconductor device and method for manufacturing the same |
US8704359B2 (en) * | 2003-04-01 | 2014-04-22 | Ge Embedded Electronics Oy | Method for manufacturing an electronic module and an electronic module |
JP4414712B2 (ja) * | 2003-09-29 | 2010-02-10 | 大日本印刷株式会社 | 電子装置の製造方法 |
TWI255518B (en) * | 2005-01-19 | 2006-05-21 | Via Tech Inc | Chip package |
JP4955259B2 (ja) * | 2005-11-24 | 2012-06-20 | 新光電気工業株式会社 | 配線基板、半導体装置、及び配線基板の製造方法 |
US20070126085A1 (en) * | 2005-12-02 | 2007-06-07 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
JP4559993B2 (ja) * | 2006-03-29 | 2010-10-13 | 株式会社東芝 | 半導体装置の製造方法 |
US20080197469A1 (en) * | 2007-02-21 | 2008-08-21 | Advanced Chip Engineering Technology Inc. | Multi-chips package with reduced structure and method for forming the same |
US20080217761A1 (en) * | 2007-03-08 | 2008-09-11 | Advanced Chip Engineering Technology Inc. | Structure of semiconductor device package and method of the same |
JP5496445B2 (ja) * | 2007-06-08 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US8710669B2 (en) * | 2009-05-20 | 2014-04-29 | Nec Corporation | Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer |
US8692364B2 (en) * | 2009-08-07 | 2014-04-08 | Nec Corporation | Semiconductor device and method for manufacturing the same |
US8455991B2 (en) * | 2010-09-24 | 2013-06-04 | Stats Chippac Ltd. | Integrated circuit packaging system with warpage control and method of manufacture thereof |
-
2010
- 2010-12-16 JP JP2010280951A patent/JP5703010B2/ja active Active
-
2011
- 2011-12-15 US US13/326,502 patent/US9299678B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20120153509A1 (en) | 2012-06-21 |
US9299678B2 (en) | 2016-03-29 |
JP2012129419A (ja) | 2012-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5703010B2 (ja) | 半導体パッケージ及びその製造方法 | |
JP5879030B2 (ja) | 電子部品パッケージ及びその製造方法 | |
TWI436717B (zh) | 可內設功能元件之電路板及其製造方法 | |
JP5864180B2 (ja) | 半導体パッケージ及びその製造方法 | |
JP5977051B2 (ja) | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 | |
JP6152254B2 (ja) | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 | |
JP5903337B2 (ja) | 半導体パッケージ及びその製造方法 | |
US9997441B2 (en) | Support member, wiring substrate, method for manufacturing wiring substrate, and method for manufacturing semiconductor package | |
US9136220B2 (en) | Semiconductor package and method for manufacturing the semiconductor package | |
JP6029958B2 (ja) | 配線基板の製造方法 | |
JP2009164592A (ja) | 組み合せ基板 | |
JPWO2008120755A1 (ja) | 機能素子内蔵回路基板及びその製造方法、並びに電子機器 | |
JP2012146963A (ja) | 半導体パッケージの製造方法及び半導体パッケージ | |
JP5406572B2 (ja) | 電子部品内蔵配線基板及びその製造方法 | |
JPWO2010052942A1 (ja) | 電子部品内蔵配線板及びその製造方法 | |
US20120126423A1 (en) | Semiconductor device manufacturing method and semiconductor device | |
JP2015225895A (ja) | プリント配線板および半導体パッケージ、ならびにプリント配線板の製造方法 | |
KR100639737B1 (ko) | 회로 장치의 제조 방법 | |
JP2015144157A (ja) | 回路基板、電子装置及び電子装置の製造方法 | |
JP2012186270A (ja) | 半導体パッケージの製造方法 | |
JP5479959B2 (ja) | はんだバンプを有する配線基板の製造方法、はんだボール搭載用マスク | |
JP5175823B2 (ja) | 半導体パッケージの製造方法 | |
JP2004193274A (ja) | 電子部品実装構造及びその製造方法 | |
JP2017201674A (ja) | プリント配線板およびその製造方法 | |
JP2012069556A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130910 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130910 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140715 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140729 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140925 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141125 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150107 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150210 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150223 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5703010 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |