JP6029958B2 - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
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- JP6029958B2 JP6029958B2 JP2012265471A JP2012265471A JP6029958B2 JP 6029958 B2 JP6029958 B2 JP 6029958B2 JP 2012265471 A JP2012265471 A JP 2012265471A JP 2012265471 A JP2012265471 A JP 2012265471A JP 6029958 B2 JP6029958 B2 JP 6029958B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
インターポーザは、一方の主面(例えば上面)に半導体素子と接続されるバンプが形成され、他方の主面(例えば下面)にパッケージの基板と接続されるバンプが形成される。インターポーザは、両主面に形成されたバンプを互いに電気的に接続する配線層を有している。
なお、添付図面は、特徴を分かりやすくするために便宜上特徴となる部分を拡大して示している場合があり、寸法,比率などは実際と異なる場合がある。また、断面図では、各部材の断面構造を分かりやすくするために、一部のハッチングを省略している。
中間基板12は、コア部31と配線部32を有している。
コア部31は、コア基板41と配線層42を有している。
パッケージ基板11と半導体素子13を接続する中間基板12は、コア基板41と配線部32を有している。コア基板41、配線部32に含まれる複数の絶縁層51〜54の材料は例えば有機樹脂である。従って、コア基板41の両面に配線層を形成することが可能である。一方、シリコンよりなる中間基板(シリコン・インターポーザ)は、シリコン基板を貫通する電極を形成するため、片面にしか配線層を形成することができない。従って、本実施形態の中間基板12は、配線層の数を多くすることで、半導体素子13に接続される実装用のパッド(配線層65)と、パッケージ基板11に接続されるパッド部42aとを中間基板12の内部にて互いに接続することができる。このため、半導体素子13に接続される実装用パッドを挟ピッチにて形成することが可能となる。
図2(a)に示すように、支持体101aを準備する。支持体101aの材料は例えば銅(Cu)である。支持体101aは、例えば、直径200mm(ミリメートル)の円盤状であり、厚さは0.6mmである。なお、支持体101aの形状を矩形状としてもよい。支持体101aは第1支持体の一例である。
図4(e)に示すように、絶縁層41及びビア42bの上面に、ビア42bと接続された配線層61を形成する。この配線層61の形成は、例えばセミアディティブ法により行われる。つまり、例えばスパッタにより絶縁層41及びビア42bを覆うシード層が形成され、シード層の上面所定位置にマスクが形成される。そして、シード層を電極とする電解めっきにより金属層が形成され、マスクが除去された後、露出するシード層がエッチング処理によって除去され、配線層61が形成される。
(1)パッケージ基板11と半導体素子13を接続する中間基板12は、コア基板41と配線部32を有している。コア基板41、配線部32に含まれる複数の絶縁層51〜54の材料は例えば有機樹脂である。コア基板41(絶縁層107)を支持体101aに接着して配線層42が形成され、配線層42を支持体101bに対向してコア基板41を支持体101bに接着して配線層61〜65が形成される。従って、コア基板41の両面に配線層42,61〜65が形成される。支持体101a,101bにコア基板41を固定することで、コア基板41の厚さを薄くすることができる。従って、中間基板12を薄く形成することができる。
・コア基板41を適宜変更してもよい。例えば、コア基板41の材料として、例えばシリカ等のフィラーを混入した樹脂材を用いることができる。これにより、コア基板41の撓みを適宜設定することができる。フィラーとしては、シリカ以外に、例えば酸化チタン、酸化アルミニウム、窒化アルミニウム、炭化珪素、チタン酸カルシウム、ゼオライト等の無機化合物、又は、有機化合物等を用いることができる。
・半導体素子13と中間基板12の間、中間基板12とパッケージ基板11の間に、アンダーフィル樹脂を充填し、硬化してもよい。
42 配線層
61〜65 配線層
101a,101b 支持体
104a,104b 接着層
105 積層板
106 金属層
107 絶縁層
Claims (7)
- 金属層と絶縁層を含む積層板を、前記金属層を第1の支持体に対向させて前記積層板を前記第1の支持体に接着する工程と、
前記絶縁層を貫通するビアと、前記絶縁層上に前記ビアと接続する第1配線層を形成する工程と、
前記第1の支持体を除去し、前記金属層と前記絶縁層と前記第1配線層とからなる構造体を得る工程と、
第2の支持体に対して前記第1配線層を対向させて前記構造体を前記第2の支持体に接着する工程と、
前記構造体から前記金属層を除去する工程と、
前記絶縁層の前記金属層を除去した面上に、前記ビアと接続する第2配線層を形成する工程と、
前記第2配線層を形成する工程の後に、前記構造体から前記第2の支持体を除去する工程と、
を有する配線基板の製造方法。 - 前記金属層と対向する前記第1の支持体の主面の端部に第1の接着層が形成され、前記第1の接着層を介して前記第1の支持体に前記積層板を接着すること、
を特徴とする請求項1記載の配線基板の製造方法。 - 前記第1配線層と対向する前記第2の支持体の主面の端部に第2の接着層が形成され、前記第2の接着層を介して前記第2の支持体に前記構造体を接着すること、
を特徴とする請求項1又は2に記載の配線基板の製造方法。 - 前記第1配線層と前記第2配線層は、セミアディティブ法により形成されてなること、を特徴とする請求項1〜3のうちの何れか一項に記載の配線基板の製造方法。
- 前記絶縁層は、有機樹脂からなること、
を特徴とする請求項1〜4のうちの何れか一項に記載の配線基板の製造方法。 - 前記絶縁層は、複数の絶縁層により形成されてなること、
を特徴とする請求項1〜5のうちの何れか一項に記載の配線基板の製造方法。 - 前記第2の支持体を除去する工程の前に、前記第2配線層上に、絶縁層と配線層とを積層してなる配線部を形成すること、
を特徴とする請求項1〜6のうちの何れか一項に記載の配線基板の製造方法。
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JP2012265471A JP6029958B2 (ja) | 2012-12-04 | 2012-12-04 | 配線基板の製造方法 |
US14/090,076 US9380707B2 (en) | 2012-12-04 | 2013-11-26 | Method of manufacturing wiring substrate |
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JP2012265471A JP6029958B2 (ja) | 2012-12-04 | 2012-12-04 | 配線基板の製造方法 |
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JP2014110390A JP2014110390A (ja) | 2014-06-12 |
JP2014110390A5 JP2014110390A5 (ja) | 2015-12-24 |
JP6029958B2 true JP6029958B2 (ja) | 2016-11-24 |
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Publication number | Priority date | Publication date | Assignee | Title |
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TWI566305B (zh) * | 2014-10-29 | 2017-01-11 | 巨擘科技股份有限公司 | 製造三維積體電路的方法 |
TWI613781B (zh) * | 2015-12-11 | 2018-02-01 | I-Shou University | 中介層結構及其製造方法 |
JP2017228647A (ja) * | 2016-06-22 | 2017-12-28 | 富士通株式会社 | 樹脂インターポーザ及びそれを用いた半導体装置及び樹脂インターポーザの製造方法 |
US10840180B2 (en) | 2016-10-06 | 2020-11-17 | Mitsui Mining & Smelting Co., Ltd. | Production method for multilayer wiring board |
CN107564880A (zh) * | 2017-08-24 | 2018-01-09 | 通富微电子股份有限公司 | 一种扇出型封装器件 |
CN107611042B (zh) * | 2017-08-24 | 2021-09-21 | 通富微电子股份有限公司 | 一种扇出型封装方法 |
JP7052464B2 (ja) * | 2018-03-22 | 2022-04-12 | 凸版印刷株式会社 | 微細配線層付きコアレス基板の製造方法、および半導体パッケージの製造方法 |
JP7202785B2 (ja) | 2018-04-27 | 2023-01-12 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
JP7321009B2 (ja) | 2019-07-01 | 2023-08-04 | 新光電気工業株式会社 | 配線基板、接合型配線基板及び配線基板の製造方法 |
JP7398561B2 (ja) * | 2019-11-18 | 2023-12-14 | 新光維医療科技(蘇州)股▲フン▼有限公司 | 一体化された小型溶接板構造およびその製造方法 |
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