JP7321009B2 - 配線基板、接合型配線基板及び配線基板の製造方法 - Google Patents
配線基板、接合型配線基板及び配線基板の製造方法 Download PDFInfo
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- JP7321009B2 JP7321009B2 JP2019123233A JP2019123233A JP7321009B2 JP 7321009 B2 JP7321009 B2 JP 7321009B2 JP 2019123233 A JP2019123233 A JP 2019123233A JP 2019123233 A JP2019123233 A JP 2019123233A JP 7321009 B2 JP7321009 B2 JP 7321009B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 238000007747 plating Methods 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims 2
- 238000010030 laminating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 85
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 239000012792 core layer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09427—Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0574—Stacked resist layers used for different processes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
Description
110 接合領域
121、121a、121b ダミーポスト
122 接続ポスト
130 コア層
131、142、152 ビア
140、150 ビルドアップ層
141、151 配線層
143、154 ソルダーレジスト層
153、210 電極パッド
160 シード層
170 DFR
200 中継基板
300 アンダーフィル材
300a フィレット
Claims (9)
- 積層された配線層及び絶縁層を備えた配線構造体と、
前記配線構造体の表面の所定の領域の周縁に沿って形成される複数の第1のポストであって、前記配線層に電気的に接続されない第1のシード層と、前記第1のシード層上に形成される第1の金属層とをそれぞれ有する複数の第1のポストと、
前記複数の第1のポストによって囲まれた位置で前記配線層に接続される第2のシード層と、前記第2のシード層上に形成され前記第1の金属層と同じ金属材料からなる第2の金属層とを有する第2のポストと、を有し、
前記複数の第1のポストは、
前記所定の領域の周縁を構成する辺の中央部に配置されている第1のポストが、前記辺の両端部に配置されている第1のポストよりも、前記配線構造体の表面からの高さが低い
ことを特徴とする配線基板。 - 前記配線構造体の表面を被覆しているソルダーレジスト層をさらに有し、
前記複数の第1のポストは、
前記ソルダーレジスト層上に形成されている
ことを特徴とする請求項1記載の配線基板。 - 前記複数の第1のポストは、
前記配線構造体の表面に露出する前記絶縁層上に形成されている
ことを特徴とする請求項1記載の配線基板。 - 前記複数の第1のポストは、
前記所定の領域の周縁を構成する辺の両端部に配置された第1のポストが、前記第2のポストよりも前記配線構造体の表面からの高さが高く、前記辺の中央部に配置された第1のポストが、前記第2のポストよりも前記配線構造体の表面からの高さが低い
ことを特徴とする請求項1記載の配線基板。 - 前記複数の第1のポストは、
前記配線構造体の表面からの高さに応じて径の大きさが異なる
ことを特徴とする請求項1記載の配線基板。 - 前記複数の第1のポストは、
前記所定の領域の周縁を構成する辺に沿って異なる疎密で配置されている
ことを特徴とする請求項1記載の配線基板。 - 第1の配線基板と第2の配線基板とが接合され、前記第1の配線基板と前記第2の配線基板とに挟まれた領域がアンダーフィル材で充填されている接合型配線基板であって、
前記第1の配線基板は、
積層された配線層及び絶縁層を備えた配線構造体と、
前記配線構造体の表面の前記第2の配線基板が接合された接合領域の周縁に沿って形成される複数の第1のポストであって、前記配線層に電気的に接続されない第1のシード層と、前記第1のシード層上に形成される第1の金属層とをそれぞれ有する複数の第1のポストと、
前記複数の第1のポストによって囲まれた位置で前記配線層に接続される第2のシード層と、前記第2のシード層上に形成され前記第1の金属層と同じ金属材料からなる第2の金属層とを有する第2のポストと、を有し、
前記複数の第1のポストは、
前記接合領域の周縁を構成する辺の中央部に配置されている第1のポストが、前記辺の両端部に配置されている第1のポストよりも、前記配線構造体の表面からの高さが低く、
前記第2の配線基板は、
前記第2のポストに電気的に接続されている、
ことを特徴とする接合型配線基板。 - 前記複数の第1のポストは、
前記接合領域の周縁を構成する辺の両端部に配置された第1のポストで前記第2の配線基板を支持していること、
を特徴とする請求項7記載の接合型配線基板。 - 配線層及び絶縁層を積層して配線構造体を形成する工程と、
前記配線層に電気的に接続されない第1の部分と前記配線層に接続される第2の部分とを有するシード層を形成する工程と、
前記配線構造体の表面の所定の領域の周縁に沿った前記第1の部分上の複数の第1のポストと、前記複数の第1のポストによって囲まれる前記第2の部分上の第2のポストとを金属のめっきにより形成する工程と、を有し、
前記複数の第1のポストと前記第2のポストとを形成する工程では、
前記所定の領域の周縁を構成する辺の両端部に形成される第1のポストよりも、当該辺の中央部に形成される第1のポストの前記配線構造体の表面からの高さを低くする
ことを特徴とする配線基板の製造方法。
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JP2019123233A JP7321009B2 (ja) | 2019-07-01 | 2019-07-01 | 配線基板、接合型配線基板及び配線基板の製造方法 |
US16/915,107 US10959328B2 (en) | 2019-07-01 | 2020-06-29 | Wiring substrate, stacked wiring substrate, and manufacturing method of wiring substrate |
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JP2019123233A JP7321009B2 (ja) | 2019-07-01 | 2019-07-01 | 配線基板、接合型配線基板及び配線基板の製造方法 |
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US11694984B2 (en) * | 2019-08-30 | 2023-07-04 | Advanced Semiconductor Engineering, Inc. | Package structure including pillars and method for manufacturing the same |
US11158572B2 (en) | 2019-08-30 | 2021-10-26 | Advanced Semiconductor Engineering, Inc. | Package structure including a first electronic device, a second electronic device and a plurality of dummy pillars |
JP2022120629A (ja) * | 2021-02-05 | 2022-08-18 | 凸版印刷株式会社 | 複合配線基板 |
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