JP2017163115A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2017163115A JP2017163115A JP2016048898A JP2016048898A JP2017163115A JP 2017163115 A JP2017163115 A JP 2017163115A JP 2016048898 A JP2016048898 A JP 2016048898A JP 2016048898 A JP2016048898 A JP 2016048898A JP 2017163115 A JP2017163115 A JP 2017163115A
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- semiconductor element
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- elastic modulus
- semiconductor device
- wiring board
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- H01L2924/3511—Warping
Abstract
【解決手段】実施形態によれば、半導体装置は、配線基板と、第1半導体素子と、第2半導体素子と、バンプと、接着部と、樹脂部と、を含む。第2半導体素子は、配線基板と第1半導体素子との間に設けられる。バンプは、第1、第2半導体素子の間に設けられ第1、第2半導体素子を電気的に接続する。接着部は、第1、第2半導体素子の間に設けられ第1、第2半導体素子を接着し、第1弾性率を有する。樹脂部は、第1弾性率よりも高い第2弾性率を有する。樹脂部の第1部分は、第1、第2半導体素子との間に設けられる。樹脂部の第2部分と配線基板との間に、第1、第2半導体素子が配置される。樹脂部の第3部分は、配線基板から第1半導体素子に向かう第1方向と交差する第2方向において第1、第2半導体素子と重なる。
【選択図】図1
Description
図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
図1(a)は、図1(b)のA1−A2線断面図である。図1(b)は、図1(a)のB1−B2線断面図である。
これらの図は、異なる構成を有する半導体装置における反りの特性の例を示している。
以下に説明する実験においては、2種類の材料が接着部25として用いられる。第1材料の室温(23℃)における弾性率D1は、0.2GPa〜10GPaである。第2材料の室温(23℃)における弾性率D1は、約15GPaである。これらの材料を用いて、接着部25の面積比率が変更される。例えば、複数の接着部25が設けられ、複数の接着部25の面積(X−Y平面内の面積)の合計の面積S25が得られる。一方、半導体素子10の1つの面積(X−Y平面内の面積)をS10とする。面積比率R1(%)は、(S25/S10)×100(%)である。さらに、樹脂部30として、4種類の材料が用いられる。これらの材料の室温(23℃)における弾性率D2は、12GPa、15GPa、30GPaまたは35GPaである。
図3(a)は、接着部25として。第1材料(弾性率D1=0.2GPa〜10GPaを用いたときの評価結果を示す。図3(b)は、接着部25として、第2材料(弾性率D1=15GPaを用いたときの評価結果を示す。図中(表中)において、接着部25の面積比率R1、及び、樹脂部30の弾性率D2が示されている。
これらの図中において、「+」マークが良好な結果であることに対応する。
図4(a)に示すように、実施形態に係る別の半導体装置111のように、第1半導体素子11及び第2半導体素子12の組みの位置は、複数の半導体素子10のうちで任意である。この例では、第1半導体素子11は、複数の半導体素子10のうちで、最上層である。
図5(a)〜図5(d)は、実施形態に係る半導体装置の製造方法を例示する工程順模式的断面図である。
図5(a)に示すように、複数の半導体素子10を積層して積層体15を形成する。それらの間に、バンプ21及び接着部25が設けられる。この例では、積層体15は、リードフレーム16の上に設けられている。
Claims (7)
- 配線基板と、
第1半導体素子と、
前記配線基板と前記第1半導体素子との間に設けられた第2半導体素子と、
前記第1半導体素子と前記第2半導体素子との間に設けられ前記第1半導体素子と前記第2半導体素子とを電気的に接続するバンプと、
前記第1半導体素子と前記第2半導体素子との間に設けられ前記第1半導体素子と前記第2半導体素子とを接着し第1弾性率を有する接着部と、
前記第1弾性率よりも高い第2弾性率を有する樹脂部と、
を備え、
前記樹脂部の第1部分は、前記第1半導体素子と前記第2半導体素子との間に設けられ、
前記樹脂部の第2部分と前記配線基板との間に、前記第1半導体素子及び前記第2半導体素子が配置され、
前記樹脂部の第3部分は、前記配線基板から前記第1半導体素子に向かう第1方向と交差する第2方向において前記第1半導体素子及び前記第2半導体素子と重なる、半導体装置。 - 前記樹脂部の第4部分は、前記配線基板と前記第2半導体素子との間に配置された、請求項1記載の半導体装置。
- 前記接着部の面積の前記第1半導体素子の面積に対する比は、11%以上78.5%未満である、請求項1または2に記載の半導体装置。
- 前記接着部の23℃における前記第1弾性率は、0.2GPa以上10GPa以下である、請求項1〜3のいずれか1つに記載の半導体装置。
- 前記樹脂部の23℃における前記第2弾性率は、15GPa以上30GPa以下である、請求項1〜4のいずれか1つに記載の半導体装置。
- 前記樹脂部の23℃における前記第2弾性率は、前記接着部の23℃における前記第1弾性率の1.5倍以上60倍以下である、請求項1〜3のいずれか1つに記載の半導体装置。
- 配線基板と、第1半導体素子と、前記配線基板と前記第1半導体素子との間に設けられた第2半導体素子と、前記第1半導体素子と前記第2半導体素子との間に設けられ前記第1半導体素子と前記第2半導体素子とを電気的に接続するバンプと、前記第1半導体素子と前記第2半導体素子との間に設けられ前記第1半導体素子と前記第2半導体素子とを接着し第1弾性率を有する接着部と、を含む加工体を準備する工程と、
前記第1半導体素子と前記第2半導体素子との間、及び、前記第1半導体素子と前記第2半導体素子の周りに、前記第1弾性率よりも高い第2弾性率を有する樹脂部を形成する工程と、
を備えた半導体装置の製造方法。
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