TWI677945B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI677945B
TWI677945B TW107102658A TW107102658A TWI677945B TW I677945 B TWI677945 B TW I677945B TW 107102658 A TW107102658 A TW 107102658A TW 107102658 A TW107102658 A TW 107102658A TW I677945 B TWI677945 B TW I677945B
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TW
Taiwan
Prior art keywords
wiring layer
package substrate
wiring
layer
semiconductor wafer
Prior art date
Application number
TW107102658A
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English (en)
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TW201913905A (zh
Inventor
谷本亮
Akira Tanimoto
向田秀子
Hideko Mukaida
沼田直子
Naoko Numata
宮脇健至
Kenji MIYAWAKI
Original Assignee
日商東芝記憶體股份有限公司
Toshiba Memory Corporation
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Application filed by 日商東芝記憶體股份有限公司, Toshiba Memory Corporation filed Critical 日商東芝記憶體股份有限公司
Publication of TW201913905A publication Critical patent/TW201913905A/zh
Application granted granted Critical
Publication of TWI677945B publication Critical patent/TWI677945B/zh

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Abstract

實施形態提供一種緩和施加於安裝基板與半導體封裝之間之凸塊之應力且可靠性較高之半導體裝置。 實施形態之半導體裝置具備封裝基板，上述封裝基板具有第1面及相對於上述第1面位於相反側之第2面。半導體晶片設置於封裝基板之第1面上，且具有半導體元件。接著劑設置於半導體晶片與封裝基板之間。金屬凸塊設置於第2面上。封裝基板係具備第1～第4配線層及第1～第3樹脂層之積層基板。若將半導體晶片、第1～第3樹脂層、第1～第4配線層、接著劑之熱膨脹係數分別設為CTE1～CTE4，則滿足CTE1＜CTE2＜CTE3＜CTE4。若將半導體晶片、第1～第3樹脂層、第1～第4配線層、接著劑之彈性模數分別設為EM1～EM4，則滿足EM1＞EM3＞EM2＞EM4。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
半導體裝置存在例如如eMMC(embedded Multimedia Card，嵌入式多媒體卡)般將複數個半導體封裝積層於安裝基板上而作為1個半導體模組構成之情形。複數個半導體封裝例如具有BGA(Ball Grid Array，球狀柵格陣列)，積層於安裝基板上並藉由BGA相互電性連接。 於將半導體封裝安裝於安裝基板上後，進行TCT(Thermal Cycle Test，熱循環測試)等試驗。例如，於用於車載之半導體製品中，要求對TCT之高耐受性。
實施形態提供一種緩和施加於安裝基板與半導體封裝之間之凸塊之應力且可靠性較高之半導體裝置。 實施形態之半導體裝置具備封裝基板，上述封裝基板具有第1面及相對於第1面位於相反側之第2面。半導體晶片設置於封裝基板之第1面上，且具有半導體元件。接著劑設置於半導體晶片與封裝基板之間。金屬凸塊設置於第2面上。封裝基板係具備以下各層之積層基板：第1～第4配線層；第1樹脂層，其設置於第1配線層與第2配線層之間；第2樹脂層，其設置於第2配線層與第3配線層之間；及第3樹脂層，其設置於第3配線層與第4配線層之間。若將半導體晶片之熱膨脹係數設為CTE1，將第1～第3樹脂層之熱膨脹係數設為CTE2，將第1～第4配線層之熱膨脹係數設為CTE3，及將接著劑之熱膨脹係數設為CTE4，則滿足式1。 CTE1＜CTE2＜CTE3＜CTE4 式1 若將半導體晶片之彈性模數設為EM1，將第1～第3樹脂層之彈性模數設為EM2，將第1～第4配線層之彈性模數設為EM3，及將接著劑之彈性模數設為EM4，則滿足式2。 EM1＞EM3＞EM2＞EM4 式2
以下，參照圖式對本發明之實施形態進行說明。本實施形態並不限定本發明。於以下之實施形態中，半導體基板之上下方向表示將接著於封裝基板之面設為下或者上時之相對方向，存在與依據重力加速度之上下方向不同之情形。圖式係模式圖或概念圖，各部分之比率等未必與實物相同。於說明書與圖式中，對於與關於已出現之圖式而於上文中記述之要素相同之要素標註相同之符號並適當省略詳細之說明。 圖1(A)及圖1(B)係表示本實施形態之半導體裝置之構成例之剖視圖。圖1(A)表示用於例如eMMC等之半導體裝置。圖1(B)表示用於例如UFS(Universal Flash Storage，通用閃存儲存器)等之半導體裝置。本實施形態應用於圖1(A)或圖1(B)中之任一半導體裝置均可。 本實施形態之半導體裝置具備封裝基板10、半導體晶片20、控制器30、接著劑40、焊料凸塊50、安裝基板60及密封樹脂70。 封裝基板10具有第1面F1及相對於第1面F1位於相反側之第2面F2。封裝基板10如參照圖2說明般，係複數個配線層與複數個樹脂層之積層基板。 半導體晶片20設置於封裝基板10之第1面F1上，例如具有設置於矽基板上之半導體元件。半導體晶片20例如亦可為NAND(Not AND，反及)型EEPROM(Electrically Erasable-Programmable Read Only Memory，電子可抹除可程式化唯讀記憶體)。半導體元件亦可為設置於矽基板上之電晶體、電阻、電容器等。於本實施形態中，複數個半導體晶片20積層於封裝基板10上。 接著劑40設置於半導體晶片20與封裝基板10之間，將半導體晶片20接著於封裝基板10上。接著劑40可為所謂之DAF(Die Attachment Film，晶片接合膜)。作為DAF，例如可使用環氧樹脂、丙烯酸系樹脂、酚樹脂等。 控制器30係控制複數個半導體晶片20之半導體晶片。控制器30與半導體晶片20同樣地，設置於封裝基板10之第1面F1上，例如具有設置於矽基板上之半導體元件。控制器30經由導線31連接於封裝基板10之配線層(於圖1中未作圖示)，而電性連接於複數個半導體晶片20。 焊料凸塊50設置於封裝基板10之第2面F2上，連接於封裝基板10之其他配線層。又，焊料凸塊50連接於安裝基板60，而將封裝基板10與安裝基板60電性連接。亦可使用由其他半導體材料構成之凸塊來代替焊料凸塊50。 安裝基板60係複數個配線層與複數個樹脂層之積層基板。安裝基板60經由焊料凸塊50電性連接於封裝基板10。安裝基板60亦可搭載複數個半導體封裝而構成1個模組。 密封樹脂70被覆半導體晶片20、控制器30、導線31等來保護其等。 圖2係更詳細地表示焊料凸塊50及其周邊之構成之剖視圖。封裝基板10係包含第1～第4配線層11～14及第1～第3樹脂層16～18之積層基板。第1樹脂層16設置於第1配線層11與第2配線層12之間，第2樹脂層17設置於第2配線層12與第3配線層13之間，第3樹脂層18設置於第3配線層13與第4配線層14之間。第1～第4配線層11～14例如使用銅、金、銀中之任一種導電材料。第1～第3樹脂層16～18例如使用玻璃環氧樹脂、酚樹脂、氟系樹脂(例如，聚四氟乙烯)、聚醯亞胺等中之任一種絕緣材料。 半導體晶片20例如包含矽基板，且於矽基板上形成有半導體元件。半導體晶片20係以接著劑40固定於封裝基板10上。 第4配線層14於封裝基板10之第2面F2被加工，而殘留於配線部分與焊料凸塊50之下之連接部分。第4配線層14中供焊料凸塊50連接之連接部分(圖14之15)經由焊料凸塊50而與安裝基板60上之配線層電性連接。 安裝基板係將複數個配線層61與複數個樹脂層62積層而成之積層體。配線層61例如使用銅、金、銀中之任一種導電材料。樹脂層62例如使用玻璃環氧樹脂、酚樹脂、氟系樹脂(例如，聚四氟乙烯)、聚醯亞胺等中之任一種絕緣材料。 此處，對封裝基板10之熱膨脹係數及彈性模數進行說明。若將半導體晶片20(例如矽基板)之熱膨脹係數設為CTE1，將第1～第3樹脂層16～18(例如玻璃環氧樹脂)之熱膨脹係數設為CTE2，將第1～第4配線層11～14(例如銅)之熱膨脹係數設為CTE3，及將接著劑40(例如環氧樹脂)之熱膨脹係數設為CTE4，則滿足式1。 CTE1＜CTE2＜CTE3＜CTE4 式1 又，若將半導體晶片20(例如矽基板)之彈性模數設為EM1，將第1～第3樹脂層16～18(例如玻璃環氧樹脂)之彈性模數設為EM2，將第1～第4配線層11～14(例如銅)之彈性模數設為EM3，及將接著劑(環氧樹脂)之彈性模數設為EM4，則滿足式2。 EM1＞EM3＞EM2＞EM4 式2 因此，封裝基板10之熱膨脹係數CTE2、CTE3及安裝基板60之熱膨脹係數CTE4大於半導體晶片20之熱膨脹係數CTE1。又，封裝基板10之彈性模數EM2、EM3及安裝基板60之彈性模數EM4小於半導體晶片20之彈性模數EM1。即，封裝基板10及安裝基板60比半導體晶片20更容易翹曲，而容易吸收應變應力。 圖3係表示相對於封裝基板10及接著劑40之厚度之焊料凸塊50之壽命之曲線圖。橫軸表示封裝基板10及接著劑40之厚度之總和。縱軸表示TCT試驗中之焊料凸塊50之壽命。再者，焊料凸塊50之壽命表示將樣品P1之壽命設為1時之其他樣品P2～P5之比率。 於該曲線圖中，樣品P1～P3與具有兩個配線層(例如11、14)之雙層配線構造之封裝基板10對應。另一方面，樣品P4、P5與具有4個配線層(例如11～14)之四層配線構造之封裝基板10對應。即，與樣品P4、P5對應之封裝基板10具有與圖2所示之本實施形態之封裝基板10相同之構成。又，與樣品P1、P2及P4對應之半導體裝置之接著劑40之厚度約為20 μm。另一方面，與樣品P3、P5對應之半導體裝置之接著劑40之厚度相對較厚，為100 μm～135 μm。以下，對根據此種構造之差異而獲得之本實施形態之半導體裝置之效果進行說明。再者，四層配線構造之封裝基板10之厚度例如約為190 μm。又，虛線L表示TCT試驗之理想位準。 與樣品P1對應之半導體裝置具有雙層配線構造之封裝基板10及具有20 μm之厚度之接著劑40。樣品P1成為P2～P5之基準，因此，將樣品P1中之焊料凸塊50之壽命設為1。如下所述，與樣品P1對應之封裝基板10之阻焊劑之構造和與其他樣品P2～P5對應之封裝基板10之阻焊劑之構造不同。因此，於圖3中，示出樣品P1作為基準，以下，對關於阻焊劑具有相同構成之樣品P2～P5進行比較。 與樣品P2對應之半導體裝置具有雙層配線構造之封裝基板10及具有20 μm之厚度之接著劑40。接著劑40之厚度固定為20 μm。另一方面，使封裝基板10之厚度(配線層或樹脂層之厚度)變化。即，樣品P2表示取決於封裝基板10之厚度之焊料凸塊50之壽命。若參照樣品P2，得知藉由將封裝基板10加厚，而緩和施加於焊料凸塊50之應力。 與樣品P3對應之半導體裝置具有雙層配線構造之封裝基板10及具有100 μm～135 μm之厚度之接著劑40。使封裝基板10之厚度(配線層或樹脂層之厚度)變化。即，樣品P3表示取決於接著劑40之厚度之焊料凸塊50之壽命。若將樣品P2與樣品P3進行比較，則會得知即便封裝基板10及接著劑40之厚度之總和大致相同，但藉由將接著劑40加厚，施加於焊料凸塊50之應力亦有所緩和。 與樣品P4對應之半導體裝置具有四層配線構造之封裝基板10及具有20 μm之厚度之接著劑40。接著劑40之厚度固定為20 μm。若於封裝基板10及接著劑40之厚度約為210 μm之點上將樣品P2與樣品P4進行比較，則會得知根據封裝基板10之構造而焊料凸塊50之壽命提高。例如，於封裝基板10及接著劑40之厚度約為210 μm之點上，將樣品P2與樣品P4進行比較。此時，四層配線構造之樣品P4與雙層配線構造之樣品P2相比，焊料凸塊50之壽命得到改善。即，即便封裝基板10及接著劑40之厚度大致相同，但藉由將封裝基板10設為四層配線構造，施加於焊料凸塊50之應力亦有所緩和。 與樣品P5對應之半導體裝置具有四層配線構造之封裝基板10及具有100 μm～135 μm之厚度之接著劑40。使封裝基板10之厚度(配線層或樹脂層之厚度)變化。即，樣品P5表示取決於封裝基板10之構造之焊料凸塊50之壽命以及取決於接著劑40之厚度之焊料凸塊50之壽命。若將樣品P3與樣品P5進行比較，則四層配線構造之樣品P5與雙層配線構造之樣品P3相比，焊料凸塊50之壽命被大幅改善。即，得知即便封裝基板10及接著劑40之厚度大致相同，但藉由將封裝基板10設為四層配線構造，施加於焊料凸塊50之應力亦有所緩和。 本實施形態之半導體裝置相當於樣品P5，具有四層配線構造之封裝基板10，且接著劑40之厚度相對較厚為100 μm～135 μm。因此，於TCT試驗時，可使焊料凸塊50所受之到應力相對較低，且可延長半導體裝置之壽命。 於TCT試驗中，包含樹脂層及配線層之安裝基板60會相對較為大幅地伸縮，但包含矽基板之半導體晶片20不太伸縮。因此，於假如封裝基板10或接著劑40之厚度較薄或者封裝基板10之構造為不易伸縮之構造(例如矽基板)之情形時，會將安裝基板60之伸縮與半導體晶片20之伸縮之差作為相對較大之應變應力施加至焊料凸塊50。該情況會導致焊料凸塊50與封裝基板10或安裝基板60之間之連接部之裂縫。 例如，由樹脂等構成之安裝基板60會因溫度差而相對較為大幅地伸縮，另一方面，封裝基板10之矽基板不易因溫度而伸縮。因此，安裝基板60與封裝基板10之間之凸塊會受到應變應力，而有於凸塊和與其連接之半導體封裝之金屬電極之間產生裂縫之顧慮。於此情形時，存在無法獲得對於TCT之充分之耐受性而有損半導體裝置之可靠性之問題。 相對於此，如圖3所示，半導體裝置具有相比於雙層配線構造而為四層配線構造之封裝基板10，且將接著劑40之厚度加厚，藉此可延長半導體裝置之壽命。因此，本實施形態之半導體裝置具備具有四層配線構造之封裝基板10，且將接著劑40之厚度設為較厚之100～135 μm。藉此，可使焊料凸塊50所受到之應力相對減低，從而可抑制於焊料凸塊50與封裝基板10或安裝基板60之間之連接部產生裂縫。結果，於TCT試驗時，可延長半導體裝置之壽命。再者，本實施形態之半導體裝置(例如樣品P5)可充分地超過虛線L之位準。 圖4(A)及圖4(B)係表示本實施形態之焊料凸塊50及其周邊部之構成之剖視圖及俯視圖。於封裝基板10之第2面F2上設置有連接部分15與阻焊劑80。連接部分15係第4配線層14中連接於焊料凸塊50之配線部分。或者，連接部分15亦可為與第4配線層14分開設置之導電層。阻焊劑80以於焊料凸塊50之位置具有開口OP之方式設置於焊料凸塊50之周邊。 此處，如圖4(B)所示，阻焊劑80之開口OP之徑W80大於連接部分15之徑W15。阻焊劑80未與連接部分15接觸，且未被覆連接部分15之側面F15_2或表面F15_1之一部分。焊料被阻焊劑80彈開而附著於未設置阻焊劑80之部分，因此焊料凸塊50以不僅與配線部分15之表面F15_1接觸且亦與側面F15_2接觸之方式形成。藉此，焊料凸塊50與配線部分15之接觸面積增大，焊料凸塊50與配線部分15之間之物理性接合強度提高。 假如為阻焊劑80與連接部分15接觸且被覆其側面F15_2或表面F15_1之一部分之情形，焊料凸塊50僅與配線部分15之表面F15_1接觸，而不與其側面F15_2接觸。因此，焊料凸塊50與配線部分15之間之接合強度降低，於TCT試驗等中，容易產生焊料凸塊50與配線部分15之間之裂縫。又，焊料凸塊50與配線部分15之間之接觸阻力會增大。 相對於此，根據本實施形態，焊料凸塊50不僅與配線部分15之表面F15_1接觸，且亦與側面F15_2接觸。藉此，可提高焊料凸塊50與配線部分15之間之物理性接合強度，從而抑制焊料凸塊50與配線部分15之間之裂縫。 例如，圖3之樣品P1具有阻焊劑80與連接部分15接觸並被覆其側面F15_2或表面F15_1之一部分之構成。樣品P2具有阻焊劑80未與連接部分15接觸且未被覆連接部分15之側面F15_2或表面F15_1之一部分之構成。樣品P1、P2之其他構成可為相同。若將樣品P1與樣品P2進行比較，得知焊料凸塊50之壽命變長。藉此，本實施形態之半導體裝置可緩和施加於安裝基板60與封裝基板10之間之焊料凸塊50之應力，從而提高可靠性。又，亦可降低焊料凸塊50與配線部分15之間之接觸阻力。 再者，於自上方觀察本實施形態之半導體裝置之情形時，其尺寸可依據JEDEC(Joint Electron Device Engineering Council，美國電子工程設計發展聯合協會)之MO-276K標準。例如，於自上方觀察本實施形態之半導體裝置之情形時，半導體裝置之尺寸可為MO-276K標準中所規定之11.5 mm×13 mm、12 mm×16 mm、14 mm×18 mm中之任一個。但是，無須限定為該等，半導體裝置之尺寸亦可為6 mm×7 mm、3 mm×7.5 mm、3 mm×8 mm、6 mm×8 mm、7 mm×9 mm、11 mm×11.5 mm、6 mm×12 mm、9 mm×12 mm、12 mm×15 mm、12 mm×18 mm、16 mm×20 mm、17 mm×22 mm中之任一個。 本實施形態之半導體裝置亦可依據其他標準，本實施形態之半導體裝置可適當應用於各種大小之構成。 已對本發明之若干實施形態進行了說明，但該等實施形態係作為例子而提出，並不意圖限定發明之範圍。該等實施形態可以其他各種方式加以實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，同樣包含於申請專利範圍所記載之發明與其均等之範圍內。 [相關申請案] 本申請案享有以日本專利申請案2017-164556號(申請日：2017年8月29日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
10‧‧‧封裝基板
11‧‧‧第1配線層
12‧‧‧第2配線層
13‧‧‧第3配線層
14‧‧‧第4配線層
16‧‧‧第1樹脂層
17‧‧‧第2樹脂層
18‧‧‧第3樹脂層
20‧‧‧半導體晶片
30‧‧‧控制器
31‧‧‧導線
40‧‧‧接著劑
50‧‧‧焊料凸塊
60‧‧‧安裝基板
61‧‧‧配線層
62‧‧‧樹脂層
70‧‧‧密封樹脂
F1‧‧‧第1面
F2‧‧‧第2面
圖1(A)及(B)係表示本實施形態之半導體裝置之構成例之剖視圖。 圖2係更詳細地表示焊料凸塊及其周邊之構成之剖視圖。 圖3係表示相對於封裝基板及接著劑之厚度而言之焊料凸塊之壽命之曲線圖。 圖4(A)及(B)係表示本實施形態之焊料凸塊及其周邊部之構成之剖視圖及俯視圖。

Claims (9)

  1. 一種半導體裝置，其具備：封裝基板，其具有第1面及相對於上述第1面位於相反側之第2面；半導體晶片，其設置於上述封裝基板之上述第1面上，且具有半導體元件；接著劑，其設置於上述半導體晶片與上述封裝基板之間；及金屬凸塊，其設置於上述第2面上；且上述封裝基板係具備以下各層之積層基板：第1~第4配線層；第1樹脂層，其設置於上述第1配線層與上述第2配線層之間；第2樹脂層，其設置於上述第2配線層與上述第3配線層之間；及第3樹脂層，其設置於上述第3配線層與上述第4配線層之間；若將上述半導體晶片之熱膨脹係數設為CTE1，將上述第1~第3樹脂層之熱膨脹係數設為CTE2，將上述第1~第4配線層之熱膨脹係數設為CTE3，及將上述接著劑之熱膨脹係數設為CTE4，則滿足式1：CTE1<CTE2<CTE3<CTE4 式1若將上述半導體晶片之彈性模數設為EM1，將上述第1~第3樹脂層之彈性模數設為EM2，將上述第1~第4配線層之彈性模數設為EM3，及將上述接著劑之彈性模數設為EM4，則滿足式2：EM1>EM3>EM2>EM4 式2進而具備安裝基板，上述安裝基板經由上述金屬凸塊電性連接於上述封裝基板，上述安裝基板係將複數個配線層與上述複數個樹脂層積層而成之積層基板。
  2. 一種半導體裝置，其具備：封裝基板，其具有第1面及相對於上述第1面位於相反側之第2面；半導體晶片，其設置於上述封裝基板之上述第1面上，且具有半導體元件；接著劑，其設置於上述半導體晶片與上述封裝基板之間；及金屬凸塊，其設置於上述第2面上；且上述封裝基板係具備以下各層之積層基板：第1~第4配線層；第1樹脂層，其設置於上述第1配線層與上述第2配線層之間；第2樹脂層，其設置於上述第2配線層與上述第3配線層之間；及第3樹脂層，其設置於上述第3配線層與上述第4配線層之間；若將上述半導體晶片之熱膨脹係數設為CTE1，將上述第1~第3樹脂層之熱膨脹係數設為CTE2，將上述第1~第4配線層之熱膨脹係數設為CTE3，及將上述接著劑之熱膨脹係數設為CTE4，則滿足式1：CTE1<CTE2<CTE3<CTE4 式1若將上述半導體晶片之彈性模數設為EM1，將上述第1~第3樹脂層之彈性模數設為EM2，將上述第1~第4配線層之彈性模數設為EM3，及將上述接著劑之彈性模數設為EM4，則滿足式2：EM1>EM3>EM2>EM4 式2上述第1~第4配線層使用銅、金、銀中之任一種導電材料，上述第1~第3樹脂層使用玻璃環氧樹脂、酚樹脂、聚四氟乙烯、聚醯亞胺中之任一種絕緣材料，上述半導體晶片具有矽基板，上述安裝基板之上述複數個配線層使用銅、金、銀中之任一種導電材料，上述安裝基板之上述樹脂層使用玻璃環氧樹脂、酚樹脂、聚四氟乙烯、聚醯亞胺中之任一種絕緣材料。
  3. 一種半導體裝置，其具備：封裝基板，其具有第1面及相對於上述第1面位於相反側之第2面；半導體晶片，其設置於上述封裝基板之上述第1面上，且具有半導體元件；接著劑，其設置於上述半導體晶片與上述封裝基板之間；及金屬凸塊，其設置於上述第2面上；且上述封裝基板係具備以下各層之積層基板：第1~第4配線層；第1樹脂層，其設置於上述第1配線層與上述第2配線層之間；第2樹脂層，其設置於上述第2配線層與上述第3配線層之間；及第3樹脂層，其設置於上述第3配線層與上述第4配線層之間；若將上述半導體晶片之熱膨脹係數設為CTE1，將上述第1~第3樹脂層之熱膨脹係數設為CTE2，將上述第1~第4配線層之熱膨脹係數設為CTE3，及將上述接著劑之熱膨脹係數設為CTE4，則滿足式1：CTE1<CTE2<CTE3<CTE4 式1若將上述半導體晶片之彈性模數設為EM1，將上述第1~第3樹脂層之彈性模數設為EM2，將上述第1~第4配線層之彈性模數設為EM3，及將上述接著劑之彈性模數設為EM4，則滿足式2：EM1>EM3>EM2>EM4 式2上述接著劑之厚度為100~135μm。
  4. 如請求項1至3任一項之半導體裝置，其中於上述封裝基板之上述第2面上進而具備阻焊劑，上述阻焊劑係以於上述凸塊之位置具有開口之方式設置於該凸塊之周邊，上述阻焊劑之上述開口之徑大於上述第4配線層中供上述凸塊連接之連接部分之徑。
  5. 如請求項4之半導體裝置，其中上述阻焊劑未與上述連接部分接觸，上述凸塊設置於未設置上述阻焊劑之區域。
  6. 如請求項1至3任一項之半導體裝置，其中自上方觀察該半導體裝置時之尺寸係依據JEDEC(Joint Electron Device Engineering Council，美國電子工程設計發展聯合協會)之MO-276K標準。
  7. 一種半導體裝置，其具備：封裝基板，其具有第1面及相對於上述第1面位於相反側之第2面；半導體晶片，其設置於上述封裝基板之上述第1面上，且具有半導體元件；接著劑，其設置於上述半導體晶片與上述封裝基板之間；及金屬凸塊，其設置於上述第2面上；且上述封裝基板係具備以下各層之積層基板：第1~第4配線層；第1樹脂層，其設置於上述第1配線層與上述第2配線層之間；第2樹脂層，其設置於上述第2配線層與上述第3配線層之間；及第3樹脂層，其設置於上述第3配線層與上述第4配線層之間；若將上述半導體晶片之熱膨脹係數設為CTE1，將上述第1~第3樹脂層之熱膨脹係數設為CTE2，將上述第1~第4配線層之熱膨脹係數設為CTE3，及將上述接著劑之熱膨脹係數設為CTE4，則滿足式1：CTE1<CTE2<CTE3<CTE4 式1若將上述半導體晶片之彈性模數設為EM1，將上述第1~第3樹脂層之彈性模數設為EM2，將上述第1~第4配線層之彈性模數設為EM3，及將上述接著劑之彈性模數設為EM4，則滿足式2：EM1>EM3>EM2>EM4 式2於上述封裝基板之上述第2面上進而具備阻焊劑，上述阻焊劑係以於上述凸塊之位置具有開口之方式設置於該凸塊之周邊，上述阻焊劑之上述開口之徑大於上述第4配線層中供上述凸塊連接之連接部分之徑；上述凸塊與上述配線部分之表面及側面接觸。
  8. 如請求項7之半導體裝置，其中自上方觀察該半導體裝置時之尺寸係依據JEDEC(Joint Electron Device Engineering Council，美國電子工程設計發展聯合協會)之MO-276K標準。
  9. 一種半導體裝置，其具備：封裝基板，其具有第1面及相對於上述第1面位於相反側之第2面；半導體晶片，其設置於上述封裝基板之上述第1面上，且具有半導體元件；接著劑，其設置於上述半導體晶片與上述封裝基板之間；及金屬凸塊，其設置於上述第2面上；且上述封裝基板係具備以下各層之積層基板：第1~第4配線層；第1樹脂層，其設置於上述第1配線層與上述第2配線層之間；第2樹脂層，其設置於上述第2配線層與上述第3配線層之間；及第3樹脂層，其設置於上述第3配線層與上述第4配線層之間；若將上述半導體晶片之熱膨脹係數設為CTE1，將上述第1~第3樹脂層之熱膨脹係數設為CTE2，將上述第1~第4配線層之熱膨脹係數設為CTE3，及將上述接著劑之熱膨脹係數設為CTE4，則滿足式1：CTE1<CTE2<CTE3<CTE4 式1若將上述半導體晶片之彈性模數設為EM1，將上述第1~第3樹脂層之彈性模數設為EM2，將上述第1~第4配線層之彈性模數設為EM3，及將上述接著劑之彈性模數設為EM4，則滿足式2：EM1>EM3>EM2>EM4 式2進而具備安裝基板，上述安裝基板經由上述金屬凸塊電性連接於上述封裝基板，上述安裝基板係將複數個配線層與上述複數個樹脂層積層而成之積層基板；上述第1~第4配線層使用銅、金、銀中之任一種導電材料，上述第1~第3樹脂層使用玻璃環氧樹脂、酚樹脂、聚四氟乙烯、聚醯亞胺中之任一種絕緣材料，上述半導體晶片具有矽基板，上述安裝基板之上述複數個配線層使用銅、金、銀中之任一種導電材料，上述安裝基板之上述樹脂層使用玻璃環氧樹脂、酚樹脂、聚四氟乙烯、聚醯亞胺中之任一種絕緣材料；於上述封裝基板之上述第2面上進而具備阻焊劑，上述阻焊劑係以於上述凸塊之位置具有開口之方式設置於該凸塊之周邊，上述阻焊劑之上述開口之徑大於上述第4配線層中供上述凸塊連接之連接部分之徑；上述凸塊與上述配線部分之表面及側面接觸；上述阻焊劑未與上述連接部分接觸，上述凸塊設置於未設置上述阻焊劑之區域。
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