JP5624578B2 - メモリシステム - Google Patents
メモリシステム Download PDFInfo
- Publication number
- JP5624578B2 JP5624578B2 JP2012067031A JP2012067031A JP5624578B2 JP 5624578 B2 JP5624578 B2 JP 5624578B2 JP 2012067031 A JP2012067031 A JP 2012067031A JP 2012067031 A JP2012067031 A JP 2012067031A JP 5624578 B2 JP5624578 B2 JP 5624578B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- memory
- address
- memory chips
- chip address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Memory System (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
図1は、本発明の第1の実施形態にかかるマルチチップパッケージのSSDへの実装例を示す図である。図示するように、SSD100は、パーソナルコンピュータなどのホスト装置200とATA(Advanced Technology Attachment)規格などの通信インタフェースで接続され、ホスト装置200の外部記憶装置として機能する。ここで、SSD100とホスト装置200とを接続する通信インタフェースには、SATA規格だけに限定されない。例えば、SAS(Serial Attached SCSI)、PCIe(PCI Express)など様々な通信インタフェース規格を採用することが可能である。
第2の実施形態によれば、初期状態のチップアドレスが書き換え可能な不揮発性メモリであるROMヒューズに予め設定されている。製造者は、マルチチップパッケージ10をSSD100に実装する際に、当該不揮発性メモリ内のチップアドレスを直接書き換えることができる。
Claims (4)
- 2以上の第1の数のメモリチップと、1以上でかつ第1の数よりも小さい第2の数のメモリチップ毎に前記複数のメモリチップのチップイネーブル信号を共通接続する内部配線と、前記内部配線が内部配線毎に接続される複数の端子と、を備えるマルチチップパッケージと、
前記第1の数のメモリチップのうちのアクセス先のメモリチップを選択し、前記選択したメモリチップとホスト装置との間のデータ転送を実行する転送コントローラと、
前記端子と前記転送コントローラとを端子毎に個別に接続する接続配線と、
を備え、
前記第1の数のメモリチップの夫々は、
書き換え可能なチップアドレス記憶部と、
外部からの操作により前記チップアドレス記憶部の記憶内容を書き換えるアドレス書き換え部と、
起動時に、前記第1の数のメモリチップを夫々識別可能な第1のチップアドレスを同一のメモリチップに属するチップアドレス記憶部に設定する初期値設定部と、
を備え、
前記転送コントローラは、
前記アドレス書き換え部を操作することによって前記チップアドレス記憶部に格納された第1のチップアドレスを前記第2の数のメモリチップを夫々識別可能な第2のチップアドレスに書き換えて、前記接続配線と前記端子と前記内部配線とを介して前記第2の数のメモリチップ毎にチップイネーブル信号を供給するとともに前記第2のチップアドレスを使用することによって、前記アクセス先のメモリチップを選択する、
ことを特徴とするメモリシステム。 - 2以上の第1の数のメモリチップと、1以上でかつ第1の数よりも小さい第2の数のメモリチップ毎に前記複数のメモリチップのチップイネーブル信号を共通接続する内部配線と、前記内部配線が内部配線毎に接続される複数の端子と、を備えるマルチチップパッケージと、
前記第1の数のメモリチップのうちのアクセス先のメモリチップを選択し、前記選択したメモリチップとホスト装置との間のデータ転送を実行する転送コントローラと、
一端を前記転送コントローラに接続し、他端を前記内部配線毎の複数の端子に共通接続する接続配線と、
を備え、
前記第1の数のメモリチップの夫々は、
書き換え可能なチップアドレス記憶部と、
起動時に、前記第1の数のメモリチップを夫々識別可能な初期状態のチップアドレスを自メモリチップのチップアドレス記憶部に設定する初期値設定部と、
を備え、
前記転送コントローラは、前記接続配線と前記端子と前記内部配線とを介して前記第1の数のメモリチップにチップイネーブル信号を供給するとともに前記初期状態のチップアドレスを使用することによって、前記アクセス先のメモリチップを選択する、
ことを特徴とするメモリシステム。 - 前記チップアドレス記憶部は、不揮発性メモリで構成され、前記アドレス書き換え部による書き換え前には、前記第1の数のメモリチップを夫々識別可能な初期状態のチップアドレスを記憶する、
ことを特徴とする請求項1に記載のメモリシステム。 - 前記第1の数のメモリチップの夫々は、外部からの操作により前記チップアドレス記憶部の記憶内容を書き換えるアドレス書き換え部をさらに備え、
前記チップアドレス記憶部は、不揮発性メモリで構成され、前記アドレス書き換え部による書き換え前には、前記第1の数のメモリチップを夫々識別可能な初期状態のチップアドレスを記憶する、
ことを特徴とする請求項2に記載のメモリシステム。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012067031A JP5624578B2 (ja) | 2012-03-23 | 2012-03-23 | メモリシステム |
US13/773,305 US8929117B2 (en) | 2012-03-23 | 2013-02-21 | Multi-chip package and memory system |
US14/590,626 US9355685B2 (en) | 2012-03-23 | 2015-01-06 | Multi-chip package and memory system |
US15/366,617 USRE48449E1 (en) | 2012-03-23 | 2016-12-01 | Multi-chip package and memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012067031A JP5624578B2 (ja) | 2012-03-23 | 2012-03-23 | メモリシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013200595A JP2013200595A (ja) | 2013-10-03 |
JP5624578B2 true JP5624578B2 (ja) | 2014-11-12 |
Family
ID=49211655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012067031A Active JP5624578B2 (ja) | 2012-03-23 | 2012-03-23 | メモリシステム |
Country Status (2)
Country | Link |
---|---|
US (3) | US8929117B2 (ja) |
JP (1) | JP5624578B2 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5624578B2 (ja) * | 2012-03-23 | 2014-11-12 | 株式会社東芝 | メモリシステム |
JP6067541B2 (ja) | 2013-11-08 | 2017-01-25 | 株式会社東芝 | メモリシステムおよびメモリシステムのアセンブリ方法 |
JP2015099890A (ja) | 2013-11-20 | 2015-05-28 | 株式会社東芝 | 半導体装置、及び半導体パッケージ |
JP6255282B2 (ja) * | 2014-02-28 | 2017-12-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US11012246B2 (en) * | 2016-09-08 | 2021-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | SRAM-based authentication circuit |
JP6765321B2 (ja) * | 2017-02-28 | 2020-10-07 | キオクシア株式会社 | メモリシステムおよび制御方法 |
JP6991014B2 (ja) | 2017-08-29 | 2022-01-12 | キオクシア株式会社 | 半導体装置 |
JP6462926B2 (ja) * | 2018-03-05 | 2019-01-30 | 東芝メモリ株式会社 | ストレージ装置、及び電子機器 |
KR101998026B1 (ko) * | 2018-06-08 | 2019-07-08 | 삼성물산 주식회사 | 멀티칩 패키지를 재활용하는 방법 및 이에 관한 메모리 장치 |
EP3837611A4 (en) | 2018-08-14 | 2022-05-11 | Rambus Inc. | PACKAGED INTEGRATED DEVICE |
CN109408442B (zh) * | 2018-12-28 | 2024-04-09 | 郑州云海信息技术有限公司 | 一种多芯片扩展装置及扩展方法 |
CN114730584A (zh) * | 2019-11-29 | 2022-07-08 | 铠侠股份有限公司 | 半导体存储装置以及存储系统 |
Family Cites Families (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09504654A (ja) * | 1993-08-13 | 1997-05-06 | イルビン センサーズ コーポレーション | 単一icチップに代わるicチップ積層体 |
JP3670041B2 (ja) | 1993-12-10 | 2005-07-13 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 不揮発性メモリチップイネーブル符号化方法、コンピュータシステム、およびメモリコントローラ |
JPH1097463A (ja) * | 1996-09-24 | 1998-04-14 | Hitachi Ltd | セレクトバス機能付き積層型半導体装置 |
US6055594A (en) * | 1998-08-24 | 2000-04-25 | 3Com Corporation | Byte accessible memory interface using reduced memory control pin count |
JP4570809B2 (ja) * | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | 積層型半導体装置及びその製造方法 |
JP5044868B2 (ja) * | 2000-11-17 | 2012-10-10 | 富士通セミコンダクター株式会社 | 半導体装置およびマルチチップモジュール |
KR20020044907A (ko) * | 2000-12-07 | 2002-06-19 | 윤종용 | 다중 플래쉬 메모리 시스템에서의 프로그램 운용 방법 |
JP4722305B2 (ja) | 2001-02-27 | 2011-07-13 | 富士通セミコンダクター株式会社 | メモリシステム |
JP2003007963A (ja) * | 2001-06-20 | 2003-01-10 | Hitachi Ltd | 半導体記憶装置および製造方法 |
US6657914B1 (en) * | 2001-07-19 | 2003-12-02 | Inapac Technology, Inc. | Configurable addressing for multiple chips in a package |
JP4419049B2 (ja) * | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
TW200504895A (en) * | 2003-06-04 | 2005-02-01 | Renesas Tech Corp | Semiconductor device |
US7030489B2 (en) * | 2003-07-31 | 2006-04-18 | Samsung Electronics Co., Ltd. | Multi-chip module having bonding wires and method of fabricating the same |
JP4381779B2 (ja) * | 2003-11-17 | 2009-12-09 | 株式会社ルネサステクノロジ | マルチチップモジュール |
JP4399777B2 (ja) * | 2004-01-21 | 2010-01-20 | セイコーエプソン株式会社 | 半導体記憶装置、半導体装置、及び電子機器 |
US7126873B2 (en) | 2004-06-29 | 2006-10-24 | Super Talent Electronics, Inc. | Method and system for expanding flash storage device capacity |
US20060069896A1 (en) * | 2004-09-27 | 2006-03-30 | Sigmatel, Inc. | System and method for storing data |
KR100621631B1 (ko) * | 2005-01-11 | 2006-09-13 | 삼성전자주식회사 | 반도체 디스크 제어 장치 |
KR100597787B1 (ko) * | 2005-03-21 | 2006-07-06 | 삼성전자주식회사 | 멀티 칩 패키지 디바이스 |
US7317630B2 (en) * | 2005-07-15 | 2008-01-08 | Atmel Corporation | Nonvolatile semiconductor memory apparatus |
KR100630761B1 (ko) * | 2005-08-23 | 2006-10-02 | 삼성전자주식회사 | 메모리 집적도가 다른 2개의 반도체 메모리 칩들을내장하는 반도체 멀티칩 패키지 |
JP4955990B2 (ja) * | 2005-12-14 | 2012-06-20 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US7592691B2 (en) * | 2006-09-01 | 2009-09-22 | Micron Technology, Inc. | High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies |
JP4791924B2 (ja) | 2006-09-22 | 2011-10-12 | 株式会社東芝 | 半導体記憶装置 |
US7477545B2 (en) * | 2007-06-14 | 2009-01-13 | Sandisk Corporation | Systems for programmable chip enable and chip address in semiconductor memory |
JP4999569B2 (ja) * | 2007-06-18 | 2012-08-15 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP2009129498A (ja) * | 2007-11-22 | 2009-06-11 | Toshiba Corp | 半導体記憶装置 |
JP5161560B2 (ja) * | 2007-12-28 | 2013-03-13 | 株式会社東芝 | 半導体記憶装置 |
US8131913B2 (en) * | 2008-02-04 | 2012-03-06 | Mosaid Technologies Incorporated | Selective broadcasting of data in series connected devices |
JP2009282678A (ja) * | 2008-05-21 | 2009-12-03 | Hitachi Ltd | フラッシュメモリモジュール及びストレージシステム |
US7970978B2 (en) * | 2008-05-27 | 2011-06-28 | Initio Corporation | SSD with SATA and USB interfaces |
JP5253901B2 (ja) | 2008-06-20 | 2013-07-31 | 株式会社東芝 | メモリシステム |
JP2010010407A (ja) * | 2008-06-27 | 2010-01-14 | Toshiba Corp | 半導体記憶装置 |
US8327066B2 (en) * | 2008-09-30 | 2012-12-04 | Samsung Electronics Co., Ltd. | Method of managing a solid state drive, associated systems and implementations |
JP2010157129A (ja) * | 2008-12-27 | 2010-07-15 | Toshiba Information Systems (Japan) Corp | 半導体記憶装置 |
JP2010176646A (ja) * | 2009-02-02 | 2010-08-12 | Toshiba Information Systems (Japan) Corp | メモリシステムおよびメモリシステムのインターリーブ制御方法 |
KR20100101959A (ko) * | 2009-03-10 | 2010-09-20 | 삼성전자주식회사 | 저장 장치 |
JP2010211734A (ja) * | 2009-03-12 | 2010-09-24 | Toshiba Storage Device Corp | 不揮発性メモリを用いた記憶装置 |
KR20100105147A (ko) * | 2009-03-20 | 2010-09-29 | 삼성전자주식회사 | 멀티 칩 패키지 및 관련된 장치 |
CN102379037B (zh) * | 2009-03-30 | 2015-08-19 | 高通股份有限公司 | 使用顶部后钝化技术和底部结构技术的集成电路芯片 |
US8149622B2 (en) * | 2009-06-30 | 2012-04-03 | Aplus Flash Technology, Inc. | Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage |
US8705281B2 (en) * | 2010-04-06 | 2014-04-22 | Intel Corporation | Method and system to isolate memory modules in a solid state drive |
JP2012018639A (ja) * | 2010-07-09 | 2012-01-26 | Toshiba Corp | メモリシステムおよび不揮発性半導体メモリ |
KR101115653B1 (ko) * | 2010-07-09 | 2012-02-15 | 주식회사 하이닉스반도체 | 멀티 칩 패키지 장치 및 그 동작 방법 |
JP5654855B2 (ja) * | 2010-11-30 | 2015-01-14 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
KR101893176B1 (ko) * | 2010-12-03 | 2018-08-29 | 삼성전자주식회사 | 멀티 칩 메모리 장치 및 그것의 구동 방법 |
US8513817B2 (en) * | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
US8436457B2 (en) * | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
JP5624578B2 (ja) * | 2012-03-23 | 2014-11-12 | 株式会社東芝 | メモリシステム |
-
2012
- 2012-03-23 JP JP2012067031A patent/JP5624578B2/ja active Active
-
2013
- 2013-02-21 US US13/773,305 patent/US8929117B2/en active Active
-
2015
- 2015-01-06 US US14/590,626 patent/US9355685B2/en not_active Ceased
-
2016
- 2016-12-01 US US15/366,617 patent/USRE48449E1/en active Active
Also Published As
Publication number | Publication date |
---|---|
USRE48449E1 (en) | 2021-02-23 |
US8929117B2 (en) | 2015-01-06 |
JP2013200595A (ja) | 2013-10-03 |
US9355685B2 (en) | 2016-05-31 |
US20130250643A1 (en) | 2013-09-26 |
US20150117080A1 (en) | 2015-04-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5624578B2 (ja) | メモリシステム | |
US9536609B2 (en) | Memory modules with multi-chip packaged integrated circuits having flash memory | |
US8131912B2 (en) | Memory system | |
KR102612003B1 (ko) | 솔리드 스테이트 드라이브 장치 및 이를 포함하는 저장 시스템 | |
US20070165457A1 (en) | Nonvolatile memory system | |
JP2015144006A (ja) | ディスクリートメモリデバイスをシステムに接続するためのブリッジデバイスを有する複合メモリ | |
US9620218B2 (en) | Memory system and assembling method of memory system | |
KR20150079492A (ko) | 멀티모드 핀아웃을 갖는 플래시 메모리 컨트롤러 | |
US20100218064A1 (en) | Semiconductor memory device incorporating controller | |
KR102417182B1 (ko) | 데이터 저장 장치와 이를 포함하는 데이터 처리 시스템 | |
US20130279253A1 (en) | Semiconductor memory device and writing method of id codes and upper addresses | |
KR20130092110A (ko) | 임베디드 솔리드 스테이트 디스크 및 솔리드 스테이트 디스크 | |
US11295794B2 (en) | Memory system, control method, and non-transitory computer readable medium | |
JP5364638B2 (ja) | メモリチップおよびマルチチップパッケージ | |
US20220284935A1 (en) | Semiconductor memory device and memory system | |
US11609710B2 (en) | Host, data storage device, data processing system and data processing method | |
TWI597728B (zh) | 指派半導體晶粒以致能高堆疊能力之技術 | |
US11824036B2 (en) | Semiconductor device | |
US11815938B2 (en) | Storage device and method of operating the same | |
US11749355B2 (en) | Semiconductor integrated circuits, multi-chip package, and operation method of semiconductor integrated circuits | |
KR100910944B1 (ko) | 제어 신호를 공유하는 플래시 메모리 제어 장치 및 방법 | |
JP2010097629A (ja) | 不揮発性半導体記憶装置 | |
JP2019049893A (ja) | メモリシステム |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140210 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140613 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140617 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140801 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140902 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140926 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5624578 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |