WO2018173764A1 - 積層デバイス、積層体および積層デバイスの製造方法 - Google Patents
積層デバイス、積層体および積層デバイスの製造方法 Download PDFInfo
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- WO2018173764A1 WO2018173764A1 PCT/JP2018/008902 JP2018008902W WO2018173764A1 WO 2018173764 A1 WO2018173764 A1 WO 2018173764A1 JP 2018008902 W JP2018008902 W JP 2018008902W WO 2018173764 A1 WO2018173764 A1 WO 2018173764A1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
Definitions
- the present invention relates to a laminated device in which a plurality of semiconductor elements and the like are laminated, a laminated body, and a method for manufacturing the laminated device, and more particularly, a laminated device having terminals that are not electrically connected to terminals to which semiconductor elements are electrically connected.
- the present invention relates to a method for manufacturing a laminated body and a laminated device.
- Patent Document 1 and Patent Document 2 disclose a stacked semiconductor package that reduces heat transfer from a lower chip to an upper chip.
- the stacked semiconductor package of Patent Document 1 includes a first circuit board, a first semiconductor package including a first semiconductor element mounted on the first circuit board, a second circuit board, and a second circuit board.
- a heat conducting material includes a first circuit board, a first semiconductor package in which a first semiconductor element is mounted on the first circuit board, a second circuit board, and a second circuit.
- a second semiconductor package mounted on a substrate and stacked on the first semiconductor package, a sealing resin for sealing the first semiconductor, and a conductive material disposed in contact with the sealing resin And a thermal via connected to the conductive layer and disposed on the first circuit board.
- Patent Document 3 discloses a wiring substrate having a conductor layer inside an insulating substrate, and a surface of the wiring substrate.
- a plurality of semiconductor devices each including a plurality of semiconductor elements, and a plurality of connection terminals that are electrically connected to the conductor layer of the wiring board are provided between the upper and lower semiconductor devices and the lower surface of the lowermost semiconductor device.
- a stacked semiconductor device having a configuration in which an auxiliary connection terminal that is not electrically connected to a conductor layer of a wiring board is provided on the outer periphery of the group is described.
- Patent Document 4 describes an electronic component built-in substrate that can efficiently dissipate heat generated in a semiconductor chip.
- the electronic component built-in substrate of Patent Document 4 is placed on the surface of the laminate so that a plurality of insulating layers and a plurality of wiring layers each including a wiring pattern are alternately laminated, and a back surface is in contact with the laminate. And a first via conductor that is in contact with the back surface of the semiconductor chip through the stacked body and that is in contact with the wiring pattern included in each of the wiring layers.
- a dummy through silicon via structure having an appropriate depth is positioned above or below a specified active circuit in a predetermined device layer in a three-dimensional stacked integrated circuit. Yes.
- An object of the present invention is to provide a multilayer device, a multilayer body, and a method for manufacturing the multilayer device that solve the above-described problems based on the conventional technology, ensure bonding strength, and have excellent heat dissipation.
- a first aspect of the present invention is a stacked device including a stacked body in which a plurality of semiconductors are electrically connected, and the semiconductor has a surface provided with a plurality of terminals.
- the plurality of terminals include a terminal that joins and electrically connects the semiconductors, and a terminal that joins and does not electrically connect the semiconductors, and a plurality of terminals on the surface provided with the semiconductor terminals.
- a laminated device in which the area ratio of terminals is 40% or more, and among the plurality of terminals, semiconductors are joined to each other and the area ratio of terminals that are electrically connected is less than 50%.
- the semiconductor has an insulating layer on the surface provided with a plurality of terminals, and the height from the surface provided with the plurality of terminals of the semiconductor to the surface of the terminal is from the surface provided with the semiconductor terminals to the surface of the insulating layer. It may be 200 nm or more and 1 ⁇ m or less with respect to the height to the surface.
- a plurality of terminals may be joined directly.
- the plurality of terminals are joined via an anisotropic conductive member having a conduction path that conducts in the stacking direction, and the conduction path preferably has a diameter of 100 nm or less.
- the anisotropic conductive member preferably has an insulating base material and a plurality of conduction paths that are provided in a state of being electrically insulated from each other and penetrating in the thickness direction of the insulating base material. Moreover, it is preferable to have an interposer.
- a second aspect of the present invention is a stacked body in which a plurality of semiconductors are electrically connected, and the semiconductor has a surface provided with a plurality of terminals, and the plurality of terminals join the semiconductors. And a terminal that is electrically connected and a terminal that joins the semiconductors and is not electrically connected, and the area ratio of the plurality of terminals on the semiconductor surface is 40% or more, and the semiconductor among the plurality of terminals
- the present invention provides a laminate in which the area ratio of terminals that join and electrically connect each other is less than 50%.
- the semiconductor has an insulating layer on the surface provided with a plurality of terminals, and the height from the surface provided with the plurality of terminals of the semiconductor to the surface of the terminal is from the surface provided with the semiconductor terminals to the surface of the insulating layer. It may be 200 nm or more and 1 ⁇ m or less with respect to the height to the surface.
- a plurality of terminals may be joined directly.
- the plurality of terminals are joined via an anisotropic conductive member having a conduction path that conducts in the stacking direction, and the conduction path preferably has a diameter of 100 nm or less.
- the anisotropic conductive member preferably has an insulating base material and a plurality of conduction paths that are provided in a state of being electrically insulated from each other and penetrating in the thickness direction of the insulating base material. Moreover, it is preferable to have an interposer.
- a third aspect of the present invention is a method for manufacturing a laminated device according to the first aspect, in which each semiconductor is temporarily bonded, and among the plurality of semiconductors, all the semiconductors are bonded together. A method is provided.
- FIG. 1 is a schematic diagram illustrating a first example of a multilayer device according to an embodiment of the present invention
- FIG. 2 is a schematic plan view illustrating an example of an arrangement of terminals of a semiconductor element of the multilayer device according to an embodiment of the present invention
- FIG. 3 is a schematic plan view showing another example of the arrangement of the terminals of the semiconductor element of the laminated device according to the embodiment of the present invention.
- a stacked device includes a stacked body in which a plurality of semiconductors are electrically connected.
- the laminated device is a device including the laminated body of the present invention as a part or all of the configuration. For example, the laminated device is completed by one, and exhibits a specific function by itself.
- the semiconductor of the present invention includes a semiconductor element, a circuit element, a sensor element, and the like, and the semiconductor element includes a passive element and an active element. Thus, the semiconductor of the present invention does not indicate a semiconductor as a substance.
- a stacked device 10 shown in FIG. 1 includes, for example, a semiconductor element 12 and a semiconductor element 14 stacked and bonded in a stacking direction Ds, and the semiconductor element 12 and the semiconductor element 14 are directly electrically connected.
- the semiconductor element 12 and the semiconductor element 14 have the same size.
- the stacked semiconductor element 12 and the semiconductor element 14 constitute a stacked body 15 in which a plurality of semiconductors are electrically connected.
- the laminated body 15 has the same effect as the laminated device 10.
- FIG. 2 is a schematic plan view of the semiconductor elements 12 and 14 and shows a state of the semiconductor elements 12 and 14 in plan view.
- Each of the semiconductor elements 12 and 14 has a surface on which a plurality of terminals 30 are provided.
- the plurality of terminals 30 are for joining the semiconductors facing each other.
- the terminal 30 includes a terminal 30a that joins and electrically connects the semiconductor elements 12 and 14, and a terminal 30b that joins and does not electrically connect the semiconductor elements 12 and 14 (joins but does not electrically connect). including.
- the terminal 30a takes out the signals of the semiconductor elements 12 and 14 to the outside.
- the terminal 30b is for radiating the heat generated in the semiconductor elements 12 and 14 to the outside and maintaining the bonding strength of the laminated device 10.
- the above-mentioned direct electrical connection means a state in which the terminal 30 of the semiconductor element 12 and the terminal 30 of the semiconductor element 14 are directly connected.
- the terminal 30a that electrically connects the semiconductor elements 12 and 14 and the terminal 30b that does not electrically connect the semiconductor elements 12 and 14 have the same shape and size.
- the terminal 30 has an area ratio of 40% or more in the surface 31 having the terminal 30 in plan view.
- the area ratio in the surface 31 having the terminals 30 in the above-described plan view is also simply referred to as an area ratio.
- the proportion of the area of the terminal 30 a in which the terminal 30 of the semiconductor element 12 is electrically connected to the terminal 30 of the other semiconductor element 14 among the plurality of terminals 30 is less than 50%. It is. Thereby, the laminated device 10 has a sufficient bonding strength and excellent heat dissipation.
- the bonding strength is the peel strength at the bonding interface between the semiconductor element 12 and the semiconductor element 14 and is evaluated by the shear strength.
- heat dissipation refers to how heat generated when stacked semiconductor elements are driven is dissipated from the surface of the stacked elements.
- heat dissipation in a narrow sense is mainly premised, and it mainly means heat transfer between semiconductor elements in the stacked portion, and is measured and evaluated using a unidirectional heat flow steady method.
- the area ratio of the plurality of terminals on the surface provided with the plurality of terminals is 40% or more, and among the plurality of terminals, the area ratio of the terminals that join and electrically connect the semiconductors. Is less than 50%.
- the area ratio of the terminals 30 on the surface 31 having the terminals 30 in plan view in the semiconductor elements 12 and 14 is less than 40%, it is difficult to ensure the bonding strength between the semiconductor elements 12 and 14.
- the ratio of the area of the terminal 30a that electrically connects the semiconductor elements 12 and 14 exceeds 50%, the heat dissipation performance decreases.
- the semiconductor element 12 and the semiconductor element 14 may be arranged in the same manner as long as the area ratio of the terminal 30a is satisfied.
- the area ratio of the plurality of terminals on the surface on which the plurality of semiconductor terminals are provided is the ratio of the total area Sm in the plan view of the terminal 30 to the area S of the surface 31 having the terminals 30 of the semiconductor elements 12 and 14. It is.
- Sr Sm / S.
- the upper limit value of the area ratio Sr is not particularly limited, but is appropriately determined according to the specifications of the semiconductor elements 12 and 14.
- the area S of the surface on which the plurality of terminals of the semiconductor elements 12 and 14 are provided (surface having electrodes) is parallel if the shape of the semiconductor elements 12 and 14 in a plan view is a square.
- W1 the length of one set of sides
- the lower limit value of the area ratio Sd of the terminal 30a is appropriately determined according to the specifications of the semiconductor elements 12 and 14, and is not particularly limited. However, the lower limit value of the area ratio Sd of the terminal 30a is 1 % Is preferred.
- the area of the terminal 30a and the area of the terminal 30b are obtained by acquiring images of the terminal 30a and the terminal 30b, obtaining an outline of the terminal 30a and an outline of the terminal 30b by image analysis, and obtaining an area in a range surrounded by the outline. Obtainable.
- the above-described area ratio Sr and the area ratio Sd of the terminal 30 a are defined at the junction interface between the semiconductor element 12 and the semiconductor element 14. Therefore, when the sizes of the semiconductor element 12 and the semiconductor element 14 are different, the area ratio Sr and the area ratio Sd of the terminal 30a are determined based on the area of the smaller semiconductor element in plan view. .
- the terminal 30a and the terminal 30b are not limited to the same shape and size. As long as the area ratio Sd of the terminal 30a is satisfied, the terminal 30b may be larger than the terminal 30a as shown in FIG. 3, the same components as those of the semiconductor elements 12 and 14 shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.
- the terminal 30 has a configuration shown in FIG. 4, for example.
- the semiconductor elements 12 and 14 include a semiconductor layer 32, a rewiring layer 34, and a passivation layer 36.
- the rewiring layer 34 and the passivation layer 36 are electrically insulating layers.
- On the surface 32a of the semiconductor layer 32 an element region (not shown) in which a circuit or the like that exhibits a specific function is formed. The element region will be described later.
- the surface 32a of the semiconductor layer 32 corresponds to the surface on which the semiconductor terminals 30 are provided.
- a rewiring layer 34 is provided on the surface 32 a of the semiconductor layer 32.
- wiring 37 that is electrically connected to the element region of the semiconductor layer 32 is provided.
- a pad 38 is provided on the wiring 37, and the wiring 37 and the pad 38 are electrically connected.
- the wiring 37 and the pad 38 can exchange signals with the element region, and supply voltage or the like to the element region.
- a passivation layer 36 is provided on the surface 34 a of the rewiring layer 34.
- a terminal 30 a is provided on a pad 38 provided on the wiring 37.
- the terminal 30a is electrically connected to the semiconductor layer 32.
- the rewiring layer 34 is not provided with the wiring 37, but only the pad 38 is provided.
- a terminal 30 b is provided on a pad 38 not provided on the wiring 37. The terminal 30b is not electrically connected to the semiconductor layer 32.
- the end face 30c of the terminal 30a and the end face 30c of the terminal 30b are both coincident with the surface 36a of the passivation layer 36 and are in a so-called flush state, and the terminal 30a and the terminal 30b protrude from the surface 36a of the passivation layer 36. Absent.
- the terminals 30a and 30b shown in FIG. 4 are made flush with the surface 36a of the passivation layer 36 by polishing, for example.
- a plurality of terminals may be directly joined, and the corresponding terminals 30a are directly connected as shown in FIG.
- the terminals 30b corresponding to each other are directly connected to each other.
- the semiconductor element 12 and the semiconductor element 14 are electrically connected to each other by the terminal 30a and physically connected without being electrically connected by the terminal 30b.
- the terminals 30a and 30b are not limited to being flush with the surface 36a of the passivation layer 36, and may protrude from the surface 36a of the passivation layer 36 as shown in FIG.
- the recess amount ⁇ that is the protruding amount of the terminal 30a and the terminal 30b with respect to the surface 36a of the passivation layer 36 is, for example, 200 nm or more and 1 ⁇ m or less.
- the recess amount ⁇ is less than 200 nm, it is substantially the same as the configuration in which the terminal 30a and the terminal 30b shown in FIG. 4 do not protrude, and it is necessary to polish with high accuracy.
- the recess amount ⁇ exceeds 1 ⁇ m, it is the same as a general configuration in which a pad electrode is provided, and it is necessary to join using a solder ball or the like.
- a resin layer 39 for protecting the terminals 30a and 30b is provided on the surface 36a of the passivation layer 36. May be.
- the above-mentioned recess amount ⁇ is obtained by obtaining an image of a cross section including the terminals 30a and 30b in the semiconductor elements 12 and 14, obtaining the outline of the terminal 30a and the outline of the terminal 30b by image analysis, and the end face 30c of the terminal 30a
- the end face 30c of the terminal 30b is detected. It can be obtained by determining the distance between the surface 36a of the passivation layer 36 and the end face 30c of the terminal 30a and the distance between the end face of the terminal 30b and 30c.
- the end surface 30c of the terminal 30a and the end surface 30c of the terminal 30b are both surfaces that are farthest from the surface 36a of the passivation layer 36, and are surfaces that are generally called upper surfaces.
- the semiconductor layer 32 is not particularly limited as long as it is a semiconductor, and is composed of silicon or the like, but is not limited thereto, and may be silicon carbide, germanium, gallium arsenide, gallium nitride, or the like. Good.
- the rewiring layer 34 is made of an electrically insulating material such as polyimide.
- the passivation layer 36 is also made of an electrically insulating material, for example, silicon nitride (SiN) or polyimide.
- the wiring 37 and the pad 38 are made of a conductive material, for example, copper, copper alloy, aluminum, aluminum alloy, or the like.
- the terminal 30a and the terminal 30b are made of a conductive material like the wiring 37 and the pad 38, and are made of, for example, a metal or an alloy. Specifically, the terminals 30a and 30b are made of, for example, copper, copper alloy, aluminum, aluminum alloy, or the like. The terminal 30a and the terminal 30b are not limited to being made of a metal or an alloy as long as they have conductivity, and are used for what are called terminals or electrode pads in the semiconductor element field. Materials can be used as appropriate.
- the laminated device 10 in FIG. 1 is obtained by laminating the semiconductor element 12 and the semiconductor element 14, but is not limited to this.
- stacked 12,14,16 in the lamination direction Ds, and joined may be sufficient.
- a stacked body 17 is constituted by the three semiconductor elements 12, 14, and 16.
- the structure which has one interposer 18 in the three semiconductor elements 12, 14, 16 like the laminated device 10 shown in FIG. 8 may be sufficient.
- the three semiconductor elements 12, 14, 16 and one interposer 18 constitute a stacked body 19.
- an interposer 18 is provided between the semiconductor element 12 and the semiconductor element 14 in the stacking direction Ds.
- the semiconductor element 14 and the semiconductor element 16 are directly joined.
- terminals 30 of the three semiconductor elements 12, 14, and 16 satisfy the above-described requirements for the terminals 30a and 30b.
- Both the laminated device 10 shown in FIG. 7 and the laminated device 10 shown in FIG. 8 have the same bonding strength and excellent heat dissipation as the laminated device 10 shown in FIG.
- the interposer 18 is responsible for electrical connection between the semiconductor elements. Also, it is responsible for electrical connection between the semiconductor element and the wiring board. By using the interposer 18, the wiring length and the wiring width can be reduced, the parasitic capacitance can be reduced, and the variation in the wiring length can be reduced.
- the configuration of the interposer 18 is not particularly limited as long as the above-described functions can be realized, and any configuration including known ones can be used as appropriate.
- the interposer 18 can be configured using, for example, an organic material such as polyimide, glass, ceramics, metal, silicon, and polycrystalline silicon.
- the plurality of terminals may be joined via an anisotropic conductive member having a conduction path that conducts in the stacking direction, and anisotropically exhibiting anisotropic conductivity as in the stacked device 10 shown in FIG.
- the semiconductor element 12 and the semiconductor element 14 may be joined in the stacking direction Ds via the conductive member 20 to electrically connect the semiconductor element 12 and the semiconductor element 14.
- the anisotropic conductive member 20 has a conduction path that conducts in the stacking direction Ds, and fulfills the function of TSV (Through Silicon Via).
- a stacked body 15 is constituted by the semiconductor element 12, the semiconductor element 14, and the anisotropic conductive member 20. Also in the laminated device 10 shown in FIG. 9, as in the laminated device 10 shown in FIG. 1, the bonding strength is ensured and the heat dissipation is excellent.
- the anisotropic conductive member 20 can also be used as an interposer.
- FIG. 10 is a plan view showing an example of the configuration of the anisotropic conductive member used in the laminated device of the embodiment of the present invention
- FIG. 11 shows the anisotropic conductive member used in the laminated device of the embodiment of the present invention. It is a typical sectional view showing an example of composition. 11 is a cross-sectional view taken along the line IB-IB in FIG.
- FIG. 12 is a schematic cross-sectional view showing an example of the configuration of the anisotropic conductive material.
- the anisotropic conductive member 20 penetrates in the insulating base 40 made of an inorganic material and the thickness direction Z (see FIG. 11) of the insulating base 40 and is electrically connected to each other. It is a member provided with the some conduction path 42 which consists of an electrically-conductive material provided in the insulated state.
- the anisotropic conductive member 20 further includes a resin layer 44 provided on the surfaces 40 a and 40 b of the insulating substrate 40.
- “the state of being electrically insulated from each other” means that each conduction path existing inside the insulating base material has a sufficiently low conductivity between each conduction path inside the insulating base material. It means a state.
- the anisotropic conductive member 20 has conductive paths 42 that are electrically insulated from each other, and has a sufficiently low conductivity in a direction x perpendicular to the thickness direction Z (see FIG. 11) of the insulating base material 40. Conductivity in direction Z. As described above, the anisotropic conductive member 20 is a member exhibiting anisotropic conductivity. The anisotropic conductive member 20 is arranged such that the thickness direction Z coincides with the lamination direction Ds of the laminated device 10.
- the conduction path 42 is provided through the insulating base material 40 in the thickness direction Z while being electrically insulated from each other.
- symbol Z1 shows the direction from the back of FIG. 10
- symbol Z2 shows the direction of the back from the front of FIG.
- the conduction path 42 may have a protruding portion 42 a and a protruding portion 42 b that protrude from the surfaces 40 a and 40 b of the insulating substrate 40.
- the anisotropic conductive member 20 may further include a resin layer 44 provided on the front surface 40 a and the back surface 40 b of the insulating base material 40.
- the resin layer 44 has adhesiveness and imparts bondability.
- the length of the protruding portion 42a and the protruding portion 42b is preferably 6 nm or more, and more preferably 30 nm to 500 nm.
- the resin layers 44 on the surfaces 40a and 40b of the insulating base material 40 show the resin layers 44 on the surfaces 40a and 40b of the insulating base material 40, but the present invention is not limited to this. At least one of the insulating base materials 40 is not limited thereto.
- the structure which has the resin layer 44 on the surface may be sufficient.
- the conductive path 42 in FIGS. 12 and 11 has a protruding portion 42a and a protruding portion 42b at both ends, but is not limited to this, and the surface of the insulating base 40 on the side having at least the resin layer 44.
- the structure which has a protrusion part in may be sufficient.
- the thickness h of the anisotropic conductive member 20 shown in FIG. 12 is, for example, 30 ⁇ m or less.
- the anisotropic conductive member 20 preferably has a total thickness variation (TTV) of 10 ⁇ m or less.
- TTV total thickness variation
- the thickness h of the anisotropic conductive member 20 is obtained by observing the anisotropic conductive member 20 with a magnification of 200,000 times with an electrolytic emission scanning electron microscope, and obtaining the contour shape of the anisotropic conductive member 20. And it is the average value which measured 10 points
- the TTV (Total Thickness Variation) of the anisotropic conductive member 20 is a value obtained by cutting the anisotropic conductive member 20 together with the support 46 by dicing and observing the cross-sectional shape of the anisotropic conductive member 20. is there.
- the anisotropic conductive member 20 is provided on the support 46 as shown in FIG. 12 for transfer, conveyance and transportation, storage, and the like.
- a release layer 47 is provided between the support 46 and the anisotropic conductive member 20.
- the support 46 and the anisotropic conductive member 20 are detachably bonded by a release layer 47.
- the anisotropic conductive member 20 provided on the support 46 via the release layer 47 is referred to as an anisotropic conductive material 50.
- the support body 46 supports the anisotropic conductive member 20 and is made of, for example, a silicon substrate.
- a ceramic substrate such as SiC, SiN, GaN, and alumina (Al 2 O 3 ), a glass substrate, a fiber reinforced plastic substrate, and a metal substrate can be used as the support 46.
- the fiber reinforced plastic substrate includes an FR-4 (Flame Retardant Type 4) substrate which is a printed circuit board.
- the support body 46 what has flexibility and is transparent can be used.
- the flexible and transparent support 46 include PET (polyethylene terephthalate), polycycloolefin, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), PE (polyethylene), PP (polypropylene), Examples thereof include plastic films such as polystyrene, polyvinyl chloride, polyvinylidene chloride, and TAC (triacetyl cellulose).
- transparent means that the transmittance is 80% or more with light having a wavelength used for alignment.
- the transmittance may be low over the entire visible light with a wavelength of 400 to 800 nm, but the transmittance is preferably 80% or more over the entire visible light with a wavelength of 400 to 800 nm.
- the transmittance is measured with a spectrophotometer.
- the release layer 47 is preferably a laminate of a support layer 48 and a release agent 49.
- the release agent 49 is in contact with the anisotropic conductive member 20, and the support 46 and the anisotropic conductive member 20 are separated from the release layer 47 as a starting point.
- the anisotropic conductive material 50 for example, by heating to a predetermined temperature, the adhesive force of the release agent 49 is weakened, and the support 46 is removed from the anisotropic conductive member 20.
- the release agent 49 for example, Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation, Somatack (registered trademark) manufactured by Somaru Corporation, and the like can be used.
- the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 are stacked in the stacking direction Ds via the anisotropic conductive member 20. It is good also as a structure joined and electrically connected.
- a laminated body 19 is constituted by the three semiconductor elements 12, 14, 16 and the two anisotropic conductive members 20. Further, as in the laminated device 10 shown in FIG. 14, the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 are laminated and bonded in the lamination direction Ds using the interposer 18 and the anisotropic conductive member 20, and An electrically connected configuration may be used.
- the three semiconductor elements 12, 14, 16, one interposer 18, and one anisotropic conductive member 20 constitute a laminated body 19.
- the bonding strength is ensured and the heat dissipation is excellent.
- the laminated device 10 shown in FIG. 15 may function as an optical sensor.
- the semiconductor element 52 and the sensor chip 54 are stacked in the stacking direction Ds via the anisotropic conductive member 20.
- the sensor chip 54 is provided with a lens 56.
- the semiconductor element 52, the sensor chip 54, and the anisotropic conductive member 20 constitute a stacked body 57.
- the optical sensor as well as the laminated device 10 shown in FIG. 1 has a bonding strength and excellent heat dissipation.
- the semiconductor element 52 is formed with a logic circuit, and its configuration is not particularly limited as long as signals obtained by the sensor chip 54 can be processed.
- the sensor chip 54 has an optical sensor that detects light.
- the optical sensor is not particularly limited as long as it can detect light.
- a CCD (Charge Coupled) Device) image sensor or CMOS (Complementary Metal Oxide Semiconductor) image sensor is used.
- the semiconductor element 52 and the sensor chip 54 are connected via the anisotropic conductive member 20, but the present invention is not limited to this, and the semiconductor element 52 and the sensor chip 54 are connected to each other.
- the structure which joins directly may be sufficient.
- the configuration of the lens 56 is not particularly limited as long as the light can be condensed on the sensor chip 54.
- a lens called a microlens is used.
- the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 described above have the semiconductor layer 32 described above and have an element region (not shown).
- the element region is a region where various element constituent circuits such as capacitors, resistors, and coils for functioning as electronic elements are formed.
- a memory circuit such as a flash memory
- a logic circuit such as a microprocessor and an FPGA (field-programmable gate array)
- a communication module such as a wireless tag, and wiring are formed.
- a transmission circuit or MEMS may be formed in the element region.
- the MEMS is, for example, a sensor, an actuator, an antenna, or the like. Examples of the sensor include various sensors such as acceleration, sound, and light.
- an element configuration circuit or the like is formed in the element region, and the rewiring layer 34 (see FIG. 4) is provided in the semiconductor element as described above.
- a combination of a semiconductor element having a logic circuit and a semiconductor element having a memory circuit can be used.
- all the semiconductor elements may have a memory circuit, and all the semiconductor elements may have a logic circuit.
- the combination of the semiconductor elements in the laminated device 10 may be a combination of a sensor, an actuator, an antenna, and the like, a memory circuit, and a logic circuit, and is appropriately determined according to the use of the laminated device 10 and the like.
- FIGS. 16 to 18 are schematic views showing a first example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps.
- the same components as those of the laminated device 10 shown in FIG. 1 and the semiconductor elements 12 and 14 shown in FIGS. Detailed description thereof will be omitted.
- a first example of a manufacturing method of a laminated device relates to a chip-on-wafer, and shows a manufacturing method of the laminated device 10 shown in FIG.
- a first semiconductor wafer 60 having a plurality of element regions is prepared.
- the plurality of element regions are provided on the surface 60 a of the first semiconductor wafer 60.
- alignment marks (not shown) for alignment and terminals 30a and 30b shown in FIG. 2 are provided.
- the first semiconductor wafer 60 is cut into units including one element region to become the semiconductor element 12.
- the semiconductor device 14 is joined to the element region to form the laminated device 10.
- a plurality of semiconductor elements 14 are prepared. Each semiconductor element 14 is also provided with an element region on the surface 14a. In the element region, alignment marks (not shown) for alignment and terminals 30a and 30b shown in FIG. 2 are provided. Each semiconductor element 14 is arranged with the surface 14 a provided with the terminals 30 a and 30 b facing the first semiconductor wafer 60. Next, the alignment of the first semiconductor wafer 60 and the semiconductor element 14 is performed using the alignment mark of the first semiconductor wafer 60 and the alignment mark of the semiconductor element 14. For the alignment using the alignment mark, for example, the alignment mark of the first semiconductor wafer 60 and the alignment mark of the semiconductor element 14 are simultaneously imaged, and the image of the alignment mark of the first semiconductor wafer 60 and the semiconductor element 14 are captured.
- the position information of the alignment mark of the first semiconductor wafer and the position information of the alignment mark of the semiconductor element 14 are obtained and aligned.
- the configuration is particularly limited as long as digital image data can be obtained for the alignment mark image or reflection image of the first semiconductor wafer 60 and the alignment mark image or reflection image of the semiconductor element 14.
- a known imaging device can be used as appropriate.
- Temporary bonding refers to fixing a semiconductor element or a semiconductor wafer on an object to be bonded in a state of being aligned with the object to be bonded.
- bonding is performed under predetermined conditions, and all the semiconductor elements 14 are bonded to the element region of the first semiconductor wafer 60.
- the terminals 30a and the terminals 30b of the semiconductor element 14 and the first semiconductor wafer 60 are joined. Bonding the objects so that the semiconductor element 14 is bonded to the first semiconductor wafer 60 is called main bonding.
- the bonding method is not particularly limited to the above-described method, and DBI (Direct Bond Interconnect) and SAB (Surface Activated Bond) can be used.
- DBI Direct Bond Interconnect
- SAB Surface Activated Bond
- a silicon oxide film is stacked on the semiconductor element 14 and the first semiconductor wafer 60, and chemical mechanical polishing is performed. Thereafter, the silicon oxide film interface is activated by plasma treatment, and the semiconductor element 14 and the first semiconductor wafer 60 are brought into contact with each other to join them.
- the above-described SAB is activated by subjecting the bonding surfaces of the semiconductor element 14 and the first semiconductor wafer 60 to a surface treatment in a vacuum. In this state, the semiconductor element 14 and the first semiconductor wafer 60 are bonded together by bringing them into contact with each other in a normal temperature environment.
- ion irradiation of an inert gas such as argon or neutral atom beam irradiation is used.
- the first semiconductor wafer 60 and the semiconductor element 14 are inspected so that the non-defective product and the defective product can be known in advance, and only the non-defective product of the semiconductor element 14 is bonded to the non-defective part in the first semiconductor wafer 60. Thus, manufacturing loss can be reduced.
- a non-defective semiconductor element whose quality is guaranteed is called KGD (Known Good Die).
- the first semiconductor wafer 60 to which the semiconductor element 14 is bonded is separated into individual element regions by, for example, dicing or laser scribing.
- the laminated device 10 in which the semiconductor element 12 and the semiconductor element 14 are joined can be obtained.
- the singulation is not limited to dicing, and laser scribing may be used.
- the plurality of semiconductor elements 14 are temporarily bonded and then bonded together, but the present invention is not limited to this. Some joining methods cannot be temporarily joined. In this case, temporary bonding of the semiconductor element 12 may be omitted.
- the semiconductor elements 14 may be bonded to the element region of the first semiconductor wafer 60 one by one. The transport and picking of the semiconductor element 14 and the first semiconductor wafer 60, and temporary bonding and main bonding can be realized by using a known semiconductor manufacturing apparatus.
- the atmosphere at the time of joining can be selected from the atmosphere, an inert atmosphere such as a nitrogen atmosphere, and a vacuum state.
- the heating temperature can be variously selected from a temperature of 100 ° C. to 400 ° C., and the heating rate can be selected from 10 ° C./min to 10 ° C./sec according to the performance of the heating stage or the heating method. The same applies to cooling. Further, it is possible to heat in steps, and it is possible to perform joining in several stages and sequentially increase the heating temperature. Regarding the pressure (load), it is possible to select rapid pressurization or stepwise pressurization according to the characteristics of the resin sealing agent.
- the atmosphere at the time of joining, the holding time for each of heating and pressing, and the changing time can be set as appropriate. Further, the order can be changed as appropriate. For example, after the vacuum state is reached, the first stage of pressurization is performed, and then the temperature is raised by heating, and then the second stage of pressurization is performed and held for a certain period of time. At this stage, a procedure can be set up such as returning to the atmosphere. Such a procedure can be modified in various ways. After pressurizing in the atmosphere, it may be heated in a vacuum state, or vacuuming, pressurizing, and heating may be performed all at once. Examples of these combinations are shown in FIGS.
- the yield of bonding can be improved.
- the temporary bonding can be similarly changed. For example, by performing the inert atmosphere, the oxidation of the electrode surface of the semiconductor element can be suppressed. Further, it is possible to perform bonding while applying ultrasonic waves.
- 19 to 25 are graphs showing first to seventh examples of the present bonding conditions.
- 19 to 25 show the atmosphere, the heating temperature, the applied pressure (load), and the processing time during bonding, and the symbol V indicates the degree of vacuum.
- a symbol L indicates a load
- a symbol T indicates a temperature.
- the high degree of vacuum means that the pressure is low.
- the atmosphere, the heating temperature, and the load at the time of bonding for example, as shown in FIGS. 19 to 21, the temperature may be increased after the load is applied with the pressure reduced.
- the timing of applying the load may be matched with the timing of raising the temperature.
- the load may be applied after the temperature is raised.
- the timing of pressure reduction and the timing of raising the temperature may be matched.
- the temperature may be raised stepwise, or may be heated in two stages as shown in FIG.
- the load may be applied stepwise as shown in FIGS.
- the pressure may be reduced by applying a load after reducing the pressure as shown in FIGS. 19, 21, 23, 24, and 25.
- the timing of applying the load may be combined. In this case, decompression and joining are performed in parallel.
- a second example of the manufacturing method of the laminated device will be described. 26 to 28 are schematic views showing a second example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps.
- a second example of the manufacturing method of the laminated device relates to a chip-on-wafer, and shows a manufacturing method of the laminated device 10 shown in FIG.
- the second example of the manufacturing method of the laminated device is the same as the first example of the manufacturing method of the laminated device except that the three semiconductor elements 12, 14, and 16 are laminated. This is the same as the first example. For this reason, the detailed description about the manufacturing method common to the 1st example of the manufacturing method of a laminated device is abbreviate
- the semiconductor element 14 is provided with an alignment mark (not shown) on the back surface 14b, and with a terminal 30a and a terminal 30b.
- the terminal 30a on the back surface 14b is electrically connected to the element region on the front surface 14a.
- the semiconductor element 16 has an element region (not shown) on the surface 16a, and an alignment mark (not shown) in the element region.
- the alignment mark on the back surface 14b of the semiconductor element 14 and the alignment mark on the semiconductor element 16 are used in a state where all the semiconductor elements 14 are temporarily bonded to the element region of the first semiconductor wafer 60.
- the semiconductor element 16 is aligned with the semiconductor element 14.
- the semiconductor element 16 is temporarily joined to the back surface 14 b of the semiconductor element 14.
- all the semiconductor elements 14 are temporarily bonded to the element region of the first semiconductor wafer 60, and the semiconductor elements 16 are temporarily bonded to all the semiconductor elements 14, and then the main bonding is performed under predetermined conditions.
- the semiconductor element 14 and the semiconductor element 16 are bonded, and the semiconductor element 14 is bonded to the element region of the first semiconductor wafer 60.
- the semiconductor element 14 the semiconductor element 16, and the first semiconductor wafer 60, the terminals 30a and the terminals 30b are joined.
- the first semiconductor wafer 60 to which the semiconductor element 14 and the semiconductor element 16 are bonded is separated into individual elements by, for example, dicing or laser scribing.
- the laminated device 10 in which the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 are joined can be obtained.
- the semiconductor elements 16 may be bonded in a state where all the semiconductor elements 14 are bonded to the element region of the first semiconductor wafer 60.
- a third example of the method for manufacturing a laminated device will be described. 29 to 30 are schematic views showing a third example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps.
- a third example of the manufacturing method of the laminated device relates to a wafer on wafer, and shows a manufacturing method of the laminated device 10 shown in FIG.
- the third example of the manufacturing method of the laminated device is different from the first example of the manufacturing method of the laminated device in that the second semiconductor wafer 62 is used in place of the semiconductor element 14 and the manufacturing method of the laminated device is the same. This is the same as the first example. For this reason, the detailed description about the manufacturing method common to the 1st example of the manufacturing method of a laminated device is abbreviate
- a first semiconductor wafer 60 and a second semiconductor wafer 62 having a plurality of element regions are prepared.
- the element region is provided on the surface 62 a of the second semiconductor wafer 62.
- the surface 60 a of the first semiconductor wafer 60 and the surface 62 a of the second semiconductor wafer 62 are opposed to each other.
- the alignment of the second semiconductor wafer 62 is performed with respect to the first semiconductor wafer 60 using the alignment marks of the first semiconductor wafer 60 and the alignment marks of the second semiconductor wafer 62.
- the front surface 60a of the first semiconductor wafer 60 and the front surface 62a of the second semiconductor wafer 62 are opposed to each other, and the first semiconductor wafer 60 and the second semiconductor wafer 60 are formed using the above-described method.
- the semiconductor wafer 62 is bonded.
- the main bonding may be performed or only the main bonding may be performed.
- each element region is separated into pieces by, for example, dicing or laser scribing.
- the laminated device 10 in which the semiconductor element 12 and the semiconductor element 14 are joined can be obtained.
- the laminated device 10 can be obtained even using a wafer-on-wafer.
- individualization is as above-mentioned, detailed description is abbreviate
- CMP chemical mechanical polishing
- the two-layer structure in which the semiconductor element 12 and the semiconductor element 14 are laminated has been described as an example.
- the present invention is not limited to this and may be three or more layers. It is.
- alignment marks (not shown), terminals 30 a and terminals 30 b are provided on the back surface 62 b of the second semiconductor wafer 62.
- the terminal 30a and the terminal 30b on the back surface 62b are electrically connected to the element region on the front surface 62a.
- a fourth example of the laminated device manufacturing method will be described.
- 31 to 33 are schematic views showing a fourth example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps.
- a fourth example of the manufacturing method of the laminated device relates to a chip-on-wafer, and shows a manufacturing method of the laminated device 10 shown in FIG.
- the fourth example of the manufacturing method of the laminated device has the semiconductor element 12 and the semiconductor element 14 laminated and bonded via the anisotropic conductive member 20. Except for this point, it is the same as the first example of the manufacturing method of the laminated device.
- the semiconductor element 14 in which the anisotropic conductive member 20 is provided on the surface 14a is prepared.
- the semiconductor element 14 is arranged with the anisotropic conductive member 20 facing the first semiconductor wafer 60.
- the alignment of the semiconductor element 14 is performed with respect to the first semiconductor wafer 60 using the alignment mark of the semiconductor element 14 and the alignment mark of the first semiconductor wafer 60.
- the semiconductor element 14 is placed on the element region of the first semiconductor wafer 60 via the anisotropic conductive member 20, for example, a predetermined pressure is applied and heated to a predetermined temperature, Holding for a predetermined time, temporary bonding is performed using the resin layer 44 (see FIG. 11). This is performed for all the semiconductor elements 14 and all the semiconductor elements 14 are temporarily bonded to the element region of the first semiconductor wafer 60 as shown in FIG. Using the resin layer 44 for temporary bonding is one of the methods, and the method described below may be used.
- a sealing resin or the like may be supplied onto the first semiconductor wafer 60 with a dispenser or the like, and the semiconductor element 14 may be temporarily bonded to the element region of the first semiconductor wafer 60, or the first semiconductor wafer 60
- the semiconductor element 14 may be temporarily bonded to the element region using an insulating resin film (NCF (Non-conductive Film)) supplied in advance.
- NCF Non-conductive Film
- a predetermined pressure is applied to the semiconductor elements 14 and heated to a predetermined temperature.
- the plurality of semiconductor elements 14 are collectively bonded to the element region of the first semiconductor wafer 60 while being held for a predetermined time.
- This joining is called main joining as described above.
- the terminal 30 a and the terminal 30 b of the semiconductor element 14 are joined to the anisotropic conductive member 20, and the terminal 30 a and the terminal 30 b of the first semiconductor wafer 60 are joined to the anisotropic conductive member 20.
- the first semiconductor wafer 60 to which the semiconductor element 14 is bonded via the anisotropic conductive member 20 is separated into individual elements by dicing or laser scribing or the like. Thereby, the laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 20, and the semiconductor element 14 are joined can be obtained.
- the temperature condition in the temporary bonding process is not particularly limited, but is preferably 0 ° C. to 300 ° C., more preferably 10 ° C. to 200 ° C., and particularly preferably room temperature (23 ° C.) to 100 ° C. preferable.
- the pressurizing condition in the temporary bonding process is not particularly limited, but is preferably 10 MPa or less, more preferably 5 MPa or less, and particularly preferably 1 MPa or less.
- the temperature condition in the main bonding is not particularly limited, but is preferably higher than the temperature of the temporary bonding, specifically, 150 ° C. to 350 ° C. is more preferable, and 200 ° C. to 300 ° C. is preferable. Is particularly preferred.
- the pressure condition in the main joining is not particularly limited, but is preferably 30 MPa or less, more preferably 0.1 MPa to 20 MPa.
- the time of the main joining is not particularly limited, but is preferably 1 second to 60 minutes, and more preferably 5 seconds to 10 minutes.
- the semiconductor element 14 provided with the anisotropic conductive member 20 on the surface 14a is used, but the present invention is not limited to this.
- the semiconductor element 14 not provided with the anisotropic conductive member 20 may be bonded to the first semiconductor wafer 60 provided with the anisotropic conductive member 20 on the surface 60a.
- a fifth example of the manufacturing method of the laminated device will be described.
- 34 to 36 are schematic views showing a fifth example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps.
- the fifth example of the manufacturing method of the laminated device compared to the second example of the manufacturing method of the laminated device, three semiconductor elements 12, 14, and 16 are laminated via the anisotropic conductive member 20 and bonded. Except for this point, this is the same as the second example of the method for manufacturing a laminated device. For this reason, the detailed description about the manufacturing method common to the 2nd example of the manufacturing method of a laminated device is abbreviate
- the semiconductor element 14 is provided with the alignment mark (not shown) on the back surface 14b, and with the terminal 30a and the terminal 30b. Further, the semiconductor element 14 is provided with an anisotropic conductive member 20 on the surface 14a. The semiconductor element 16 also has an anisotropic conductive member 20 on the surface 16a.
- the alignment marks on the back surface 14b of the semiconductor element 14 are performed with respect to the semiconductor element 14 using the alignment mark of the semiconductor element 16.
- the semiconductor element 16 is temporarily joined to the back surface 14 b of the semiconductor element 14 via the anisotropic conductive member 20.
- all the semiconductor elements 14 are temporarily bonded to the element region of the first semiconductor wafer 60 via the anisotropic conductive member 20, and the semiconductor elements are connected to all the semiconductor elements 14 via the anisotropic conductive member 20.
- the main joining is performed under predetermined conditions. Thereby, the semiconductor element 14 and the semiconductor element 16 are bonded via the anisotropic conductive member 20, and the semiconductor element 14 and the first semiconductor wafer 60 are bonded via the anisotropic conductive member 20.
- the semiconductor element 14, the semiconductor element 16, and the terminals 30 a and 30 b of the first semiconductor wafer 60 are bonded to the anisotropic conductive member 20.
- the first semiconductor wafer 60 to which the semiconductor element 14 and the semiconductor element 16 are bonded via the anisotropic conductive member 20 is divided into element regions, for example, dicing or laser scribing. It separates into pieces. Thereby, the laminated device 10 in which the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 are joined via the anisotropic conductive member 20 can be obtained.
- a sixth example of the method for manufacturing a laminated device will be described.
- 37 to 38 are schematic views showing a sixth example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps.
- the sixth example of the manufacturing method of the laminated device relates to a wafer on wafer, and shows a manufacturing method of the laminated device 10 shown in FIG.
- the sixth example of the manufacturing method of the multilayer device includes the first semiconductor wafer 60 and the second semiconductor wafer 62 via the anisotropic conductive member 20.
- the method is the same as the third example of the method for manufacturing a laminated device, except that these are joined.
- a first semiconductor wafer 60 and a second semiconductor wafer 62 are prepared.
- the anisotropic conductive member 20 is provided on either the surface 60 a of the first semiconductor wafer 60 or the surface 62 a of the second semiconductor wafer 62.
- the surface 60 a of the first semiconductor wafer 60 and the surface 62 a of the second semiconductor wafer 62 are opposed to each other.
- the alignment of the second semiconductor wafer 62 is performed with respect to the first semiconductor wafer 60 using the alignment marks of the first semiconductor wafer 60 and the alignment marks of the second semiconductor wafer 62.
- the front surface 60a of the first semiconductor wafer 60 and the front surface 62a of the second semiconductor wafer 62 are opposed to each other, and the first semiconductor wafer 60 and the second semiconductor wafer 60 and the second semiconductor wafer 60 are formed as shown in FIG.
- the semiconductor wafer 62 is bonded via the anisotropic conductive member 20.
- the main bonding may be performed or only the main bonding may be performed.
- first semiconductor wafer 60 and the second semiconductor wafer 62 it is necessary to make the first semiconductor wafer 60 and the second semiconductor wafer 62 thinner while the first semiconductor wafer 60 and the second semiconductor wafer 62 are bonded. If there is a semiconductor wafer, it can be thinned by chemical mechanical polishing (CMP) or the like.
- CMP chemical mechanical polishing
- the two-layer structure in which the semiconductor element 12 and the semiconductor element 14 are laminated is described as an example.
- the present invention is not limited to this. Of course it is good.
- three layers are provided by providing an alignment mark (not shown), the terminal 30a, and the terminal 30b on the back surface 62b of the second semiconductor wafer 62.
- the above laminated device 10 can be obtained.
- the anisotropic conductive member 20 in the laminated device 10 even if the semiconductor element has irregularities, the irregularities are absorbed by using the protruding portions 42a and 42b as buffer layers. can do. Since the protruding portion 42a and the protruding portion 42b function as a buffer layer, high surface quality can be eliminated for the surface having the element region in the semiconductor element. For this reason, a smoothing process such as polishing is unnecessary, the production cost can be suppressed, and the production time can be shortened. Further, since the laminated device 10 can be manufactured using a chip-on-wafer, the yield is maintained and the manufacturing loss is reduced by bonding only the non-defective semiconductor chip to the non-defective part in the semiconductor wafer. Can do. Furthermore, as described above, the resin layer 44 has adhesiveness, and can be used as a temporary bonding agent at the time of temporary bonding.
- the semiconductor element 14 provided with the anisotropic conductive member 20 includes the anisotropic conductive member 20 of the anisotropic conductive material 50 shown in FIG. 12 and a semiconductor wafer including a plurality of element regions (not shown). Can be formed. As described above, alignment marks (not shown) for alignment and the terminals 30a and 30b shown in FIG. 2 are provided in the element region. In the anisotropic conductive material 50, the anisotropic conductive member 20 is formed in a pattern that matches the element region.
- a predetermined pressure is applied, heated to a predetermined temperature, and held for a predetermined time to bond the anisotropic conductive member 20 of the anisotropic conductive material 50 to the element region of the semiconductor wafer.
- the support 46 of the anisotropic conductive material 50 is removed, and only the anisotropic conductive member 20 is bonded to the semiconductor wafer.
- the anisotropic conductive material 50 is heated to a predetermined temperature to reduce the adhesive force of the release agent 49 of the release layer 47, and the support 46 starts from the release layer 47 of the anisotropic conductive material 50. Remove.
- the semiconductor wafer is separated into pieces for each element region to obtain a plurality of semiconductor elements 14.
- the semiconductor element 14 provided with the anisotropic conductive member 20 has been described as an example, the semiconductor element 16 provided with the anisotropic conductive member 20 is also the second provided with the anisotropic conductive member 20. Also for the semiconductor wafer 62, the anisotropic conductive member 20 can be provided in the same manner as the semiconductor element 14 provided with the anisotropic conductive member 20.
- the present invention is not limited to this, and it is a form in which a plurality of semiconductor elements are bonded to one semiconductor element. One to a plurality of forms may be used. Further, a multiple-to-multiple configuration in which a plurality of semiconductor elements and a plurality of semiconductor elements are joined may be used. 39 is a schematic diagram illustrating an eighth example of the multilayer device according to the embodiment of the present invention, FIG. 40 is a schematic diagram illustrating a ninth example of the multilayer device according to the embodiment of the present invention, and FIG. FIG.
- FIG. 42 is a schematic diagram showing a tenth example of the multilayer device according to the embodiment of the invention
- FIG. 42 is a schematic diagram showing an eleventh example of the multilayer device according to the embodiment of the present invention
- FIG. 43 is an embodiment of the present invention. It is a schematic diagram which shows the 12th example of the laminated device of.
- the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 are joined and electrically connected using an anisotropic conductive member 20, respectively.
- the laminated device 63 of the form is illustrated.
- the semiconductor element 12 may have an interposer function.
- a semiconductor element wafer may be used in the laminated device 63.
- the semiconductor element 14 and the semiconductor element 16 are bonded to one semiconductor element 12 using the anisotropic conductive member 20, and
- the laminated device 64 in an electrically connected form is exemplified.
- the semiconductor element 12 may have an interposer function.
- a plurality of devices such as a logic chip having a logic circuit and a memory chip can be stacked on a device having an interposer function. In this case, bonding can be performed even if the electrode size is different for each device.
- the electrodes 68 are not the same in size but are mixed in different sizes.
- a semiconductor element 12 is used for the semiconductor element 12 by using the anisotropic conductive member 20.
- the element 14 and the semiconductor element 16 are joined and electrically connected.
- the semiconductor element 66 is joined to the semiconductor element 14 using the anisotropic conductive member 20 and is electrically connected thereto.
- the semiconductor element 67 is joined and electrically connected across the semiconductor element 14 and the semiconductor element 16 using the anisotropic conductive member 20.
- the semiconductor element 14 and the semiconductor element 16 are joined and electrically connected to one semiconductor element 12 using the anisotropic conductive member 20 as in the laminated device 69 shown in FIG. Yes. Further, the semiconductor element 66 and the semiconductor element 67 are joined to the semiconductor element 14 using the anisotropic conductive member 20, the semiconductor element 71 is joined to the semiconductor element 16 using the anisotropic conductive member 20, and electrically A connected configuration can also be adopted.
- a light emitting element such as a VCSEL (Vertical Cavity Surface Emitting Laser) and a light receiving element such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor are stacked on the device surface including the optical waveguide.
- VCSEL Vertical Cavity Surface Emitting Laser
- CMOS Complementary Metal Oxide Semiconductor
- the semiconductor element 66 and the semiconductor element 67 are joined to the semiconductor element 14 using the anisotropic conductive member 20, the semiconductor element 71 is joined to the semiconductor element 16 using the anisotropic conductive member 20, and electrically It is connected.
- the semiconductor element 12 is provided with an optical waveguide 61.
- the semiconductor element 16 is provided with a light emitting element 75, and the semiconductor element 14 is provided with a light receiving element 76.
- the light Lo output from the light emitting element 75 of the semiconductor element 16 passes through the optical waveguide 61 of the semiconductor element 12 and is emitted as the outgoing light Ld to the light receiving element 76 of the semiconductor element 14. Thereby, it can respond to the above-mentioned silicon photonics.
- a hole 21 is formed at a location corresponding to the optical path of the light Lo and the emitted light Ld.
- TSV Through Silicon Via
- Devices having TSVs are classified into three types: via first, via amidel, and via last, depending on at which stage the TSV is formed. Forming the TSV before forming the transistor of the device is called via first. What is formed after the formation of the transistor and before the formation of the rewiring layer is referred to as biamide. What is formed after the rewiring layer is formed is called via last. TSV formation by any method requires thinning of the silicon substrate in order to perform the penetration process.
- a method for bonding a semiconductor chip or a wafer to which TSV is applied will be described together with an example of a usage form of a laminated body.
- via first or via amide there is a stacked memory chip called HBM (High Bandwidth Memory) or HMC (Hybrid Memory Cube).
- HBM High Bandwidth Memory
- HMC Hybrid Memory Cube
- the memory area and TSV area are formed in the same die shape, the base wafer is thinned, the TSV is formed, electrodes called micro bumps are formed on the surface of the via, and the layers are joined together. Is going.
- vialast there is a step of bonding a semiconductor chip or wafer having no metal bump with an insulating adhesive or an insulating oxide, and then forming a TSV.
- the area of the joint is increased and the resistance per shear stress can be improved.
- heat conduction between layers is improved, heat is easily diffused throughout the laminate.
- Examples of the bonding method applicable to any of via first, via amide, and via last include metal diffusion bonding, oxide film direct bonding, metal bump bonding, and eutectic bonding.
- Metal diffusion bonding or oxide film direct bonding has good bonding properties under low pressure and low temperature conditions.
- a high degree of cleanliness with respect to the bonding surface for example, a level equivalent to that immediately after surface cleaning by Ar etching is required.
- the flatness for example, the arithmetic average roughness Ra is required to be 1 nm or less, so that strict atmosphere control and parallelism control are required at the time of bonding.
- the types of semiconductor devices or wiring rules may be different. When laminating, the strictest precision or control is required.
- metal bump bonding or eutectic bonding has good bondability even when there are some defects or the process is redundant.
- the cleanliness or flatness of the device surface when bonding different types of devices may be lower than metal diffusion bonding or oxide film direct bonding.
- the bonding strength is lower than that of metal diffusion bonding and oxide film direct bonding, and the problem is that the portion that has already been bonded may be reheated each time the stacking is repeated, resulting in device failure. Can be mentioned.
- Literature AIST Research Report, March 8, 2013: “Multifunctional, High-Density Three-Dimensional Integration Technology (2) Research and Development of Evaluation and Analysis Technology for Next-Generation Three-Dimensional Integration ⁇ (2) -B Thermal and Multilayer Bonding” Technology R &D> ”) proposes a method of avoiding the influence of temperature history by temporarily fixing at the time of stacking with an organic resin and heating and bonding all the layers at once after stacking. Since heat dissipation can be improved by forming an electrode that does not contribute to signal transmission, it is particularly useful to apply a laminate to an embodiment using an organic resin layer with low thermal conductivity.
- the anisotropic conductive member which comprises a laminated body is utilized for the above-mentioned joining.
- the anisotropic conductive member used for the laminate is preferably formed with a resin layer on at least one surface, and more preferably on both surfaces.
- the resin layer 44 of the above-mentioned anisotropic conductive member contains a thermosetting resin.
- the formed resin layer as described above serves as a temporary bonding layer and suppresses misalignment after lamination. Since temporary bonding can be performed at a low temperature and in a short time, adverse effects on the device can be reduced.
- the thickness of the resin layer is preferably 100 nm to 1000 nm, and the thermal conductivity of the anisotropic conductive member is 20 to 100 W / (m ⁇ K), and the coefficient of thermal expansion (CTE) of the anisotropic conductive member is preferably 5 ppm to 10 ppm.
- the anisotropic conductive member is preferably supplied in a form held on the support through a peelable adhesive layer.
- the material of the support is not particularly limited, but a material such as silicon or glass is preferable because it is difficult to bend and a certain flatness can be secured.
- the peelable adhesive layer may be an adhesive layer with low adhesiveness, but is preferably an adhesive layer whose adhesiveness is lowered by heating or light irradiation. Examples of the adhesive layer whose adhesiveness is lowered by heating include Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation or Somatack (registered trademark) manufactured by Somaru Corporation.
- Riva Alpha registered trademark
- Somatack registered trademark
- a pattern may be formed on the anisotropic conductive member when it is held on the support.
- pattern formation include, for example, concavo-convex pattern formation, singulation, and hydrophilic / hydrophobic pattern formation.
- the hydrophilic / hydrophobic pattern is formed, and the hydrophilic / hydrophobic pattern is singulated. More preferred.
- An anisotropic conductive member contains a conductive material, so it is only necessary that electrodes be formed on the surfaces to be joined in order to perform joining.
- Special metal bumps such as fine conical gold bumps or Connectec Japan Co., Ltd.
- Special technology such as monster pack core technology by the company, Tohoku Microtech Co., Ltd. and AIST Masahiro Aoyagi Research Group is not required.
- the anisotropic conductive member preferably has a protrusion on the surface.
- the protruding portion 42a that is, the protrusion is conductive. It is more preferable to include a protrusion made of a material.
- the laminated body which has a terminal which has an area ratio of this invention has favorable heat conduction between layers, since heat
- the COC method is a method in which semiconductor chips are stacked on a semiconductor chip fixed to a substrate, and semiconductor chips of different sizes can be stacked. It is possible to sort out good semiconductor chips before bonding. However, when a large number of semiconductor chips are stacked, alignment is required each time, which is expensive.
- the COW method is a method in which semiconductor chips are stacked on a substrate wafer. When a large number of semiconductor chips are stacked, alignment is required every time as in the COC method, which is expensive.
- the WOW method is a method in which wafers are bonded to each other, and has advantages such as a reduction in bonding time and easy alignment. However, since a good semiconductor chip cannot be selected, the yield of a multilayer stack tends to decrease. .
- an anisotropic conductive member is preferably used for each joint of the laminated body, but the laminated body may include a joint by a conventional method.
- a laminate having bonding by an anisotropic conductive member has hybrid bonding between an optical semiconductor and an ASIC (Application Specific Integrated Circuit), and a surface between the memory and the ASIC.
- ASIC Application Specific Integrated Circuit
- Conventional bonding has the advantage of facilitating the stacking of devices manufactured with different rules.
- Examples of three-dimensional lamination using anisotropic conductive members include the following modes. First, the first semiconductor chip group is inspected and separated into pieces, and the first non-defective semiconductor chip group is selected. The first non-defective semiconductor chip group is arranged on the first base via the first anisotropic conductive member, and temporary bonding is performed. The temporary bonding can be performed by an apparatus such as a flip chip bonder.
- the first substrate is not particularly limited, and examples thereof include a device having a transistor or a substrate having a wiring layer and a through electrode. After the stacked semiconductor chip group is inspected, it is separated into individual chips and the stacked good semiconductor chip group is selected.
- the stacked semiconductor chip group is not particularly limited, and examples thereof include an aspect having a through electrode or an aspect in which a back surface of a semiconductor chip having an embedded via is removed.
- Examples of the method for removing the back surface include back grinding, CMP, and chemical etching. In particular, a removal method such as chemical etching with little lateral stress is preferable.
- the stacked non-defective semiconductor chip groups are arranged at positions corresponding to the arrangement of the first non-defective semiconductor chip groups on the first base. After aligning the first base and the second base, a second anisotropic conductive member is sandwiched between the first base and the second base, and the second anisotropic conductive member. The first non-defective semiconductor chip group and the stacked non-defective semiconductor chip group are temporarily joined via Next, the second substrate is peeled off from the stacked non-defective semiconductor chip group.
- a structure composed of the first non-defective semiconductor chip group, the second anisotropic conductive member, and the stacked non-defective semiconductor chip group is defined as a new first non-defective semiconductor chip group, and a structure of a predetermined hierarchy is formed.
- the second anisotropic conductive member and the stacked semiconductor chip group are repeatedly stacked.
- the layers are subjected to main joining by performing heating and pressurization in a lump to obtain a three-dimensional joining structure.
- the obtained three-dimensional junction structure is sealed by a technique such as compression bonding, and is divided into individual pieces to obtain a target element. It should be noted that processing such as thinning, rewiring, and electrode formation may be performed before dividing into individual pieces.
- examples include an embodiment in which the stacked semiconductor chip group is separated into pieces after being joined to the first non-defective semiconductor chip group via the second anisotropic conductive member, and the anisotropic conductive having a pattern formed thereon.
- An aspect in which the member is used as the first or second anisotropic conductive member, and the anisotropic conductive member in which the pattern is formed is used as an adhesive for arranging the stacked semiconductor chip groups on the second base, Examples include an embodiment in which peeling is performed at the interface between the second substrate and the anisotropic conductive member.
- a first anisotropic conductive member is provided on the surface of the first base.
- the first substrate may be an embodiment in which a MOS (Metal Oxide Semiconductor) is present, or may be an embodiment in which no MOS is present.
- the first semiconductor chip group is inspected, separated into individual pieces, and the first non-defective semiconductor chip group is selected.
- a second anisotropic conductive member is provided on the surface of the support through a temporary bonding layer whose adhesiveness is reduced by the treatment.
- the material of the support is not particularly limited, but silicon or glass is preferable.
- As the temporary bonding layer whose adhesion is lowered by the treatment a temporary bonding layer whose adhesion is lowered by heating or a temporary bonding layer whose adhesion is lowered by light irradiation is preferable.
- the ⁇ Pattern is provided on the second anisotropic conductive member.
- the pattern is more preferably an individual hydrophilic / hydrophobic pattern.
- the method for singulation is not particularly limited, and examples thereof include a dicing method, a laser irradiation method, a stealth dicing method, a wet etching method, and a dry etching method.
- the first non-defective semiconductor chip group is arranged on the support via the second anisotropic conductive member by self-assembly technology using a pattern, and temporary bonding is performed.
- a self-assembly technique for example, a droplet containing an active agent is formed on a mounting region of a substrate, a semiconductor chip group is placed on the droplet, an element is positioned in the mounting region, and the droplet is dried. There is a method in which the element and the mounting substrate are bonded via a curable resin layer, and the activator is washed away.
- the electrode may be used as an alignment mark.
- the first base and the first non-defective semiconductor chip group are temporarily joined via the first anisotropic conductive member.
- a process for reducing the adhesiveness of the temporary bonding layer is performed, and peeling is performed at the interface between the second anisotropic conductive member and the support.
- the structure including the first base, the first anisotropic conductive member, and the first non-defective semiconductor chip group is a new first base, and the second anisotropic conductive member is a new first anisotropic. Lamination of the first good semiconductor chip group and the second anisotropic conductive member is repeated until a conductive layer is formed and a predetermined hierarchical structure is formed.
- the hierarchy is subjected to a batch process under conditions of higher pressure and higher temperature than the conditions used in the temporary joining, thereby obtaining a three-dimensional joined structure. Since the temporary bonding layer remains in the laminate, it is preferable to use a material that undergoes a curing reaction under the main bonding conditions as the temporary bonding layer.
- the obtained three-dimensional junction structure is sealed by a technique such as compression bonding and separated into individual pieces to obtain a target laminated device. It should be noted that processing such as thinning, rewiring, and electrode formation may be performed before the separation.
- the temporary bonding and the main bonding can be separated by using the anisotropic conductive member, it is not necessary to perform a high temperature process such as solder reflow a plurality of times, and the risk of device failure occurrence can be reduced. Further, as described above, in the aspect using the anisotropic conductive member having the resin layer on the surface, the resin layer can mitigate the influence of the process condition on the joint portion. Moreover, in the aspect using the anisotropic conductive member having protrusions on the surface, since the bonding is possible even when the surface flatness of the bonding target is low, the flattening process can be simplified.
- FIG. 44 to 54 are schematic views showing a seventh example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps.
- FIG. 55 to FIG. 57 are schematic views showing the manufacturing method of the laminated body used in the seventh example of the manufacturing method of the laminated device of the embodiment of the present invention in the order of steps.
- FIG. 58 and FIG. 59 are schematic views showing the manufacturing method of the laminated body used in the seventh example of the manufacturing method of the laminated device of the embodiment of the present invention in the order of steps.
- the seventh example of the method for manufacturing a laminated device relates to three-dimensional lamination, and uses an anisotropic conductive member as in the fifth example of the method for manufacturing a laminated device. For this reason, the detailed description about the manufacturing method common to the 5th example of the manufacturing method of a laminated device is abbreviate
- a first laminated substrate 70 is prepared in which the anisotropic conductive member 20 is provided on the entire surface 72a of the semiconductor wafer 72.
- the semiconductor wafer 72 can have the same configuration as the first semiconductor wafer 60 including a plurality of element regions (not shown).
- the semiconductor wafer 72 may be the above-described interposer 18.
- a second laminated substrate 80 provided with a plurality of semiconductor elements 14 is prepared. In the second laminated substrate 80, the release functional layer 84 and the anisotropic conductive member 20 are laminated on the surface 82 a of the second substrate 82. A plurality of semiconductor elements 14 are provided on the anisotropic conductive member 20.
- a hydrophilic / hydrophobic film 85 is provided in a region where the semiconductor element 14 is not provided.
- the back surface 14b of the semiconductor element 14 is the surface on the second substrate 82 side, and the front surface 14a is the opposite surface.
- the semiconductor element 14 for example, a non-defective semiconductor element selected by inspection is used.
- the peeling functional layer 84 is composed of, for example, an adhesive layer whose adhesiveness is lowered by heating or light irradiation.
- the adhesive layer whose adhesiveness is lowered by heating include Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation or Somatack (registered trademark) manufactured by Somaru Corporation.
- Riva Alpha registered trademark
- Somatack registered trademark
- the first laminated substrate 70 and the second laminated substrate 80 are temporarily joined.
- the method of temporary bonding is as described above.
- an apparatus such as a flip chip bonder can be used for the temporary bonding.
- the second base 82 of the second laminated base 80 is removed.
- the semiconductor element 14 is temporarily bonded to the anisotropic conductive member 20 of the semiconductor wafer 72, and the anisotropic conductive member 20 is transferred to the surface 14 a of the semiconductor element 14.
- the second base 82 is removed by reducing the adhesiveness of the release functional layer 84 by, for example, heating or light irradiation.
- another second laminated substrate 80 is temporarily joined to the anisotropic conductive member 20 on the surface 14a side of the semiconductor element 14 with the positions of the semiconductor elements 14 aligned.
- the back surface 14b of the semiconductor element 14 of another second laminated substrate 80 and the anisotropic conductive member 20 on the front surface 14a side of the semiconductor element 14 temporarily bonded to the semiconductor wafer 72 are temporarily bonded.
- the method of temporary joining is as described above.
- the second base 82 of another second laminated base 80 is removed. The method for removing the second substrate 82 is as described above. As shown in FIG.
- FIG. 49 shows a configuration in which two layers of semiconductor elements 14 are provided. As described above, the number of stacked semiconductor elements 14 can be controlled by repeating the temporary bonding of the second stacked substrate 80.
- a third composite laminate 86 shown in FIG. 50 is prepared.
- the third composite laminate 86 has a third substrate 88, and a hydrophilic / hydrophobic film 89 is formed in a specific pattern on the surface 88a.
- the semiconductor element 14 is provided in the surface 88a of the third base 88, that is, in a region where the hydrophilic / hydrophobic film 89 is not provided.
- the semiconductor element 14 is, for example, a non-defective semiconductor element selected by inspection.
- the hydrophilic / hydrophobic film 89 is formed by applying a water-repellent material through a mask to form a desired pattern.
- a compound such as alkylsilane or fluoroalkylsilane can be used.
- a material that exhibits a water-repellent effect depending on the shape for example, a phase separation structure of isotactic polypropylene (i-PP) can be used.
- the third composite laminate is formed on the anisotropic conductive member 20 on the surface 14 a side of the semiconductor element 14 with respect to the first laminate base 70 provided with two layers of the semiconductor elements 14.
- the body 86 is temporarily joined by aligning the positions of the semiconductor elements 14.
- the semiconductor element 14 is provided with three layers.
- the third substrate 88 of the third composite laminate 86 is removed.
- the method for removing the third substrate 88 is the same as the method for removing the second substrate 82 described above.
- the semiconductor element 14, the anisotropic conductive member 20, and the semiconductor wafer 72 are subjected to main bonding by performing batch processing under conditions of higher pressure and higher temperature than the conditions used for the temporary bonding, and the three-dimensional shown in FIG. 53.
- a bonded structure 74 is obtained.
- the three-dimensional bonded structure 74 may be subjected to processing such as thinning, rewiring, and electrode formation.
- the semiconductor wafer 72 and the anisotropic conductive member 20 of the three-dimensional bonded structure 74 are cut into individual pieces as shown in FIG. Thereby, the laminated device 10 in which the three semiconductor elements 14 are joined via the anisotropic conductive member 20 can be obtained.
- the above-described method can be appropriately used as the method for dividing into pieces.
- the second laminated base 80 shown in FIG. 45 is formed by laminating the release functional layer 84 and the anisotropic conductive member 20 on the surface 82a of the second base 82.
- a hydrophilic / hydrophobic film 85 is formed in a specific pattern on the anisotropic conductive member 20.
- the hydrophilic / hydrophobic film 85 has a pattern formed on the anisotropic conductive member 20 by a method such as a lithography method or a self-assembly method.
- examples of hydrophilic materials that form a hydrophilic pattern include hydrophilic polymers such as polyvinyl alcohol.
- the hydrophilic / hydrophobic film 85 can be formed of the material used for the hydrophilic / hydrophobic film 89 described above.
- the hydrophilic / hydrophobic film 85 may be formed with a specific pattern by exposure and development using a resist material containing a fluorine compound.
- the semiconductor element 14 is provided in a region where the hydrophilic / hydrophobic film 85 is not provided.
- a second laminated substrate 80 shown in FIG. 45 is obtained.
- a method for providing the semiconductor element 14 for example, a droplet containing an active agent is formed in a region where the hydrophilic / hydrophobic film 85 is not provided, the semiconductor element 14 is placed on the droplet, positioned, and the droplet is A method of drying, bonding the semiconductor element 14 and the second base 82 through a curable resin layer, and washing away the active agent is used.
- a hydrophilic / hydrophobic film 89 is formed in a specific pattern on the surface 88 a of the third base 88.
- the hydrophilic / hydrophobic film 89 has the same configuration as the above-described hydrophilic / hydrophobic film 85 and can be formed by the same method.
- the semiconductor element 14 is provided in a region where the hydrophilic / hydrophobic film 89 is not provided.
- a droplet containing an active agent is formed in a region where the hydrophilic / hydrophobic film 89 is not provided, the semiconductor element 14 is placed on the droplet, positioned, and the droplet is A method is used in which the semiconductor element 14 and the third base 88 are bonded together via a curable resin layer, and the activator is washed away. Thereby, the third composite laminate 86 shown in FIG. 50 is obtained.
- FIGS. 60 to 72 are schematic views showing an eighth example of the manufacturing method of the laminated device according to the embodiment of the present invention in the order of steps, and FIGS. It is a schematic diagram which shows the example of 9 in process order. 60 to 77, the same components as those of the anisotropic conductive material 50 shown in FIG. 12 and the laminated device 10 shown in FIG. 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the anisotropic conductive material 50 having the support 46 and the anisotropic conductive member 20 and the wafer 112 provided with the rewiring layer 110 are prepared.
- the rewiring layer 110 has the above-described interposer function.
- the rewiring layer 110 may be configured as the above-described rewiring layer 34, for example.
- the rewiring layer 110 is disposed opposite to the anisotropic conductive member 20, and the anisotropic conductive member 20 and the rewiring layer 110 are joined as shown in FIG. Connecting.
- FIG. 62 the wafer 112 is separated from the rewiring layer 110.
- the anisotropic conductive member 50 is disposed on the rewiring layer 110 with the anisotropic conductive member 20 facing the rewiring layer 110.
- the rewiring layer 110 and the anisotropic conductive member 20 are joined as shown in FIG. 64, and one support 46 is separated as shown in FIG.
- the semiconductor element 12 is disposed so as to face the anisotropic conductive member 20 from which one support 46 is separated.
- the anisotropic conductive member 20 and the semiconductor element 12 are joined and electrically connected.
- the remaining support 46 is separated.
- the semiconductor element 14 is disposed so as to face the anisotropic conductive member 20 from which the remaining support 46 is separated on the side where the semiconductor element 12 is not provided.
- the anisotropic conductive member 20 and the semiconductor element 14 are joined and electrically connected. Thereby, the semiconductor element 12 and the semiconductor element 14 can be laminated
- the present invention is not limited to this, and the semiconductor element 14 and the semiconductor element 16 may be disposed for one semiconductor element 12, as shown in FIG. Good.
- a plurality of semiconductor elements 14 and semiconductor elements 16 are arranged in one semiconductor element 12. Also in this case, the semiconductor element 14 and the semiconductor element 16 can be stacked on the semiconductor element 12 without using TSV.
- the rewiring layer 110 is not limited to being used alone, and can be used by being embedded in an organic substrate.
- the organic substrate 120 is disposed so as to face the rewiring layer 110 with respect to the anisotropic conductive material 50 provided with the rewiring layer 110.
- the organic substrate 120 functions as, for example, an interposer.
- the organic substrate 120 is electrically connected to the rewiring layer 110 using, for example, solder.
- the rewiring layer 110 may be embedded in the organic substrate 120.
- the support body 46 is separated as shown in FIG. Next, as shown in FIG.
- the semiconductor element 12 is disposed so as to face the anisotropic conductive member 20.
- the semiconductor element 12 is joined to the anisotropic conductive member 20 and electrically connected thereto.
- a stacked layer of the rewiring layer 110 and the semiconductor element 12 can be obtained.
- the semiconductor element has been described as an example.
- the present invention is not limited to this, and a semiconductor wafer may be used instead of the semiconductor element.
- the configuration of the semiconductor element is not particularly limited, and the above-described examples can be used as appropriate.
- the insulating base material is made of an inorganic material and is particularly limited as long as it has an electrical resistivity (about 10 14 ⁇ ⁇ cm) comparable to that of an insulating base material that constitutes a conventionally known anisotropic conductive film or the like.
- electrical resistivity about 10 14 ⁇ ⁇ cm
- “consisting of an inorganic material” is a rule for distinguishing from a polymer material constituting a resin layer described later, and is not a rule limited to an insulating base material composed only of an inorganic material, but an inorganic material. Is the main component (50% by mass or more).
- the insulating substrate examples include metal oxide substrates, metal nitride substrates, glass substrates, ceramic substrates such as silicon carbide, silicon nitride, carbon substrates such as diamond-like carbon, polyimide substrates, These composite materials are exemplified.
- the insulating base material may be a film formed of an inorganic material containing 50% by mass or more of a ceramic material or a carbon material on an organic material having a through hole.
- the insulating base material is preferably a metal oxide base material because micropores having a desired average opening diameter are formed as through-holes, and it is easy to form a conduction path described later.
- An oxide film is more preferable.
- Specific examples of the valve metal include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Of these, an anodic oxide film (base material) of aluminum is preferable because it has good dimensional stability and is relatively inexpensive.
- the interval between the conductive paths in the insulating substrate is preferably 5 nm to 800 nm, more preferably 10 nm to 200 nm, and even more preferably 50 nm to 140 nm.
- the insulating base functions sufficiently as an insulating partition.
- the interval between the conductive paths means the width w between the adjacent conductive paths, and the cross section of the anisotropic conductive member is observed at a magnification of 200,000 times with a field emission scanning electron microscope. An average value obtained by measuring the width between passages at 10 points.
- the plurality of conduction paths are made of a conductive material that penetrates in the thickness direction of the insulating base material and is electrically insulated from each other.
- the conduction path has a protruding portion protruding from the surface of the insulating base material, and the end of the protruding portion of each conduction path may be embedded in a resin layer described later.
- the conductive material constituting the conduction path is not particularly limited as long as the electrical resistivity is 10 3 ⁇ ⁇ cm or less, and specific examples thereof include gold (Au), silver (Ag), copper (Cu), Preferred examples include aluminum (Al), magnesium (Mg), nickel (Ni), tin oxide doped with indium (ITO), and the like. Among these, from the viewpoint of electrical conductivity, copper, gold, aluminum, and nickel are preferable, and copper and gold are more preferable.
- the protruding portion of the conductive path is a portion where the conductive path protrudes from the surface of the insulating base material, and the end of the protruding portion is embedded in the resin layer.
- the aspect ratio of the protruding portion is preferably 0.5 or more and less than 50, more preferably 0.8 to 20, and further preferably 1 to 10. preferable.
- the height of the protruding portion of the conduction path is preferably 20 nm or more as described above, and more preferably 100 nm to 500 nm.
- the height of the protruding portion of the conduction path is an average obtained by observing the cross section of the anisotropic conductive member with a field emission scanning electron microscope at a magnification of 20,000 times and measuring the height of the protruding portion of the conduction path at 10 points. Value.
- the diameter of the protruding portion of the conduction path refers to an average value obtained by observing the cross section of the anisotropic conductive member with a field emission scanning electron microscope and measuring the diameter of the protruding portion of the conduction path at 10 points.
- the conduction path is columnar, and the diameter d of the conduction path is preferably more than 5 nm and 10 ⁇ m or less, more preferably 20 nm to 1000 nm, and even more preferably 100 nm or less, like the diameter of the protruding portion.
- a density of 20,000 pieces / mm is preferably 2 or more, 2 million / mm 2 or more Is more preferably 10 million pieces / mm 2 or more, particularly preferably 50 million pieces / mm 2 or more, and most preferably 100 million pieces / mm 2 or more.
- center-to-center distance p between adjacent conductive paths is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and even more preferably 50 nm to 140 nm.
- the resin layer is provided on the surface of the insulating base material and embeds the above-described conduction path. That is, the resin layer covers the surface of the insulating base and the end of the conductive path protruding from the insulating base.
- the resin layer imparts bondability to the connection target.
- the resin layer preferably exhibits fluidity in a temperature range of 50 ° C. to 200 ° C. and is cured at 200 ° C. or higher.
- the composition of the resin layer will be described.
- the resin layer contains a polymer material.
- the resin layer may contain an antioxidant material.
- thermosetting resin examples include epoxy resins, phenol resins, polyimide resins, polyester resins, polyurethane resins, bismaleimide resins, melamine resins, and isocyanate resins. Among these, it is preferable to use a polyimide resin and / or an epoxy resin because the insulation reliability is further improved and the chemical resistance is excellent.
- antioxidant material contained in the resin layer include 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole, 5-methyl-1,2, 3,4-tetrazole, 1H-tetrazole-5-acetic acid, 1H-tetrazole-5-succinic acid, 1,2,3-triazole, 4-amino-1,2,3-triazole, 4,5-diamino-1 , 2,3-triazole, 4-carboxy-1H-1,2,3-triazole, 4,5-dicarboxy-1H-1,2,3-triazole, 1H-1,2,3-triazole-4- Acetic acid, 4-carboxy-5-carboxymethyl-1H-1,2,3-triazole, 1,2,4-triazole, 3-amino-1,2,4-triazole, 3,5-diamino-1,2 , 4-triazole, -Carboxy-1,2,4-triazole, 3,5-dicar
- benzotriazole and its derivatives are preferred.
- benzotriazole derivatives include a hydroxyl group, an alkoxy group (eg, methoxy group, ethoxy group, etc.), an amino group, a nitro group, an alkyl group (eg, methyl group, ethyl group, butyl group, etc.) on the benzene ring of benzotriazole.
- substituted benzotriazole having a halogen atom for example, fluorine, chlorine, bromine, iodine, etc.
- substituted naphthalenetriazole, substituted naphthalenebistriazole and the like substituted in the same manner as naphthalenetriazole and naphthalenebistriazole can also be mentioned.
- antioxidant material contained in the resin layer include general antioxidants, higher fatty acids, higher fatty acid copper, phenolic compounds, alkanolamines, hydroquinones, copper chelating agents, organic amines, organic An ammonium salt etc. are mentioned.
- the content of the antioxidant material contained in the resin layer is not particularly limited, but is preferably 0.0001% by mass or more and more preferably 0.001% by mass or more with respect to the total mass of the resin layer from the viewpoint of the anticorrosive effect. Moreover, from the reason for obtaining an appropriate electrical resistance in this joining process, 5.0 mass% or less is preferable and 2.5 mass% or less is more preferable.
- the resin layer contains a migration prevention material because the insulation reliability is further improved by trapping metal ions, halogen ions, and metal ions derived from the semiconductor chip and the semiconductor wafer that can be contained in the resin layer. Is preferred.
- an ion exchanger for example, an ion exchanger, specifically, a mixture of a cation exchanger and an anion exchanger, or only a cation exchanger can be used.
- the cation exchanger and the anion exchanger can be appropriately selected from, for example, an inorganic ion exchanger and an organic ion exchanger described later.
- inorganic ion exchanger examples include metal hydrated oxides typified by hydrous zirconium oxide.
- metals for example, in addition to zirconium, iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, bismuth, and the like are known.
- zirconium-based ones have exchangeability for the cationic Cu 2+ and Al 3+ .
- iron-based ones have exchange ability for Ag + and Cu 2+ .
- those based on tin, titanium and antimony are cation exchangers.
- those of bismuth-based, anion Cl - has exchange capacity for.
- Zirconium-based ones exhibit anion exchange capacity depending on the production conditions. The same applies to aluminum-based and tin-based ones.
- inorganic ion exchangers other than these synthetic compounds such as acid salts of polyvalent metals typified by zirconium phosphate, heteropolyacid salts typified by ammonium molybdophosphate, insoluble ferrocyanides, and the like are known. Some of these inorganic ion exchangers are already commercially available. For example, various grades under the trade name IXE “IXE” of Toa Gosei Co., Ltd. are known.
- natural product zeolite or inorganic ion exchanger powder such as montmorillonite can also be used.
- organic ion exchanger examples include crosslinked polystyrene having a sulfonic acid group as a cation exchanger, and those having a carboxylic acid group, a phosphonic acid group, or a phosphinic acid group. Moreover, the crosslinked polystyrene which has a quaternary ammonium group, a quaternary phosphonium group, or a tertiary sulfonium group as an anion exchanger is mentioned.
- inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the type of cation to be captured, the type of anion, and the exchange capacity for the ion. Of course, it goes without saying that an inorganic ion exchanger and an organic ion exchanger may be mixed and used. Since the manufacturing process of an electronic device includes a heating process, an inorganic ion exchanger is preferable.
- the mixing ratio of the migration preventing material and the above-described polymer material is preferably, for example, 10% by mass or less for the migration preventing material and 5% by mass or less for the migration preventing material from the viewpoint of mechanical strength. More preferably, the migration prevention material is further preferably 2.5% by mass or less. Moreover, it is preferable that a migration prevention material shall be 0.01 mass% or more from a viewpoint of suppressing the migration at the time of joining a semiconductor chip or a semiconductor wafer, and an anisotropic conductive member.
- the resin layer preferably contains an inorganic filler.
- the inorganic filler is not particularly limited and can be appropriately selected from known ones. For example, kaolin, barium sulfate, barium titanate, silicon oxide powder, finely divided silicon oxide, gas phase method silica, and amorphous silica , Crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconium oxide, yttrium oxide, silicon carbide, silicon nitride and the like.
- the average particle diameter of the inorganic filler is larger than the interval between the conduction paths.
- the average particle size of the inorganic filler is preferably 30 nm to 10 ⁇ m, and more preferably 80 nm to 1 ⁇ m.
- the average particle size is defined as a primary particle size measured by a laser diffraction / scattering particle size measuring device (Microtrack MT3300 manufactured by Nikkiso Co., Ltd.).
- the resin layer may contain a curing agent.
- a curing agent it does not use a solid curing agent at room temperature, but contains a liquid curing agent at room temperature, from the viewpoint of suppressing poor bonding with the surface shape of the semiconductor chip or semiconductor wafer to be connected. Is more preferable.
- solid at normal temperature means a solid at 25 ° C., for example, a substance having a melting point higher than 25 ° C.
- the curing agent examples include aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone, aliphatic amines, imidazole derivatives such as 4-methylimidazole, dicyandiamide, tetramethylguanidine, thiourea-added amine, methyl
- aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone
- aliphatic amines examples include imidazole derivatives such as 4-methylimidazole, dicyandiamide, tetramethylguanidine, thiourea-added amine, methyl
- carboxylic acid anhydrides such as hexahydrophthalic anhydride, carboxylic acid hydrazides, carboxylic acid amides, polyphenol compounds, novolak resins, polymercaptans, and the like.
- curing agent may be used individually by 1
- the resin layer may contain various additives such as a dispersant, a buffering agent, and a viscosity modifier that are generally added to a resin insulating film of a semiconductor package as long as the characteristics are not impaired.
- additives such as a dispersant, a buffering agent, and a viscosity modifier that are generally added to a resin insulating film of a semiconductor package as long as the characteristics are not impaired.
- the thickness of the resin layer is preferably larger than the height of the protruding portion of the conduction path and is 1 ⁇ m to 5 ⁇ m.
- ⁇ Transparent insulator> A transparent insulator is comprised by what is visible light transmittance
- the transparent insulator when the main component (polymer material) is the same as the above [resin layer], the adhesion between the transparent insulator and the resin layer is preferable. Since the transparent insulator is formed in a portion where there is no electrode or the like, it is preferable not to include the ⁇ antioxidation material> of the above [resin layer] and the ⁇ migration prevention material> of the above [resin layer].
- the transparent insulator preferably contains ⁇ inorganic filler> of the above [resin layer] because the warpage of the anisotropic conductive material is reduced when the CTE (linear expansion coefficient) is closer to the support such as silicon.
- the polymer material and the curing agent are the same as those in the above [resin layer] because curing conditions such as temperature and time are the same.
- the visible light transmittance of 80% or more means that the light transmittance is 80% or more in the visible light wavelength region having a wavelength of 400 to 800 nm.
- the light transmittance is measured using “Plastic—How to obtain total light transmittance and total light reflectance” defined in JIS (Japanese Industrial Standard) K 7375: 2008.
- the method for manufacturing the anisotropic conductive member is not particularly limited.
- a conductive path forming step in which a conductive material is present in a through hole provided in an insulating base material to form a conductive path and a conductive path forming step A trimming step of removing only a part of the surface of the insulating base material later and projecting the conductive path; and a resin layer forming step of forming a resin layer on the surface of the insulating base material and the protruding portion of the conductive path after the trimming process; And the like.
- insulating substrate for example, a glass substrate having a through hole (Through Glass Via: TGV) can be used as it is, but from the viewpoint of setting the opening diameter of the conduction path and the aspect ratio of the protruding portion in the above range, A substrate formed by anodizing the valve metal is preferred.
- anodizing treatment for example, when the insulating substrate is an anodized film of aluminum, anodizing treatment for anodizing the aluminum substrate, and pores formed by anodizing after the anodizing treatment are performed. It can produce by performing the penetration process which penetrates in this order.
- the aluminum substrate used for the production of the insulating base material and each processing step applied to the aluminum substrate those similar to those described in paragraphs ⁇ 0041> to ⁇ 0121> of JP 2008-270158 A should be adopted. Can do.
- the conduction path forming step is a step of causing a conductive material to exist in a through hole provided in the insulating base material.
- a method of making the metal exist in the through hole for example, each method (electrolytic plating method or electroless method described in paragraphs ⁇ 0123> to ⁇ 0126> of JP-A-2008-270158 and FIG. 4) is used. The same method as the plating method) can be mentioned.
- the electrolytic plating method or the electroless plating method it is preferable to provide an electrode layer of gold, nickel, copper or the like in advance.
- Examples of the method for forming the electrode layer include vapor phase treatment such as sputtering, liquid layer treatment such as electroless plating, and a combination thereof.
- vapor phase treatment such as sputtering
- liquid layer treatment such as electroless plating
- a combination thereof By the metal filling step, an anisotropic conductive member before the protruding portion of the conduction path is formed is obtained.
- the surface on one side of the aluminum substrate (hereinafter also referred to as “single side”) is subjected to anodization treatment, and aluminum
- An anodizing treatment step for forming an anodized film having micropores in the thickness direction and a barrier layer at the bottom of the micropores on one side of the substrate, and an anodizing barrier layer after the anodizing step A barrier layer removing step to be removed, a metal filling step of performing electrolytic plating after the barrier layer removing step to fill the inside of the micropore with a metal, an aluminum substrate being removed after the metal filling step, and a metal-filled microstructure And a substrate removing step for obtaining the method.
- an anodizing process is performed on one surface of the aluminum substrate to form an anodized film having micropores in the thickness direction and a barrier layer present at the bottom of the micropore on one surface of the aluminum substrate. It is a process.
- a conventionally known method can be used for the anodizing treatment, but it is preferable to use a self-regulating method or a constant voltage treatment from the viewpoint of increasing the regularity of the micropore array and ensuring anisotropic conductivity.
- the self-ordering method or the constant voltage process of the anodizing process is the same as the processes described in paragraphs ⁇ 0056> to ⁇ 0108> and [FIG. 3] of Japanese Patent Application Laid-Open No. 2008-270158. Can be applied.
- the barrier layer removing step is a step of removing the barrier layer of the anodized film after the anodizing treatment step. By removing the barrier layer, a part of the aluminum substrate is exposed through the micropore.
- the method for removing the barrier layer is not particularly limited.
- the barrier layer is electrochemically dissolved at a potential lower than the potential in the anodizing treatment in the anodizing treatment step (hereinafter also referred to as “electrolytic removal treatment”). ); Method of removing the barrier layer by etching (hereinafter, also referred to as “etching removal treatment”); a combination of these (especially, after the electrolytic removal treatment is performed, the remaining barrier layer is removed by the etching removal treatment) Method);
- the electrolytic removal treatment is not particularly limited as long as it is an electrolytic treatment performed at a potential lower than the potential (electrolytic potential) in the anodizing treatment in the anodizing treatment step.
- the electrolytic dissolution treatment can be performed continuously with the anodizing treatment, for example, by lowering the electrolytic potential at the end of the anodizing treatment step.
- the electrolytic removal treatment can employ the same electrolytic solution and treatment conditions as those of the above-described conventionally known anodizing treatment except for the electrolytic potential.
- the electrolytic removal treatment and the anodic oxidation treatment are successively performed as described above, it is preferable to perform treatment using the same electrolytic solution.
- the electrolytic potential in the electrolytic removal treatment is preferably lowered continuously or stepwise (stepwise) to a potential lower than the electrolytic potential in the anodic oxidation treatment.
- the reduction width (step width) when the electrolytic potential is lowered stepwise is preferably 10 V or less, more preferably 5 V or less, and more preferably 2 V or less from the viewpoint of the withstand voltage of the barrier layer. More preferably it is.
- the voltage drop rate when dropping the electrolytic potential continuously or stepwise is preferably 1 V / second or less, more preferably 0.5 V / second or less, and 0.2 V / second from the viewpoint of productivity. More preferred is less than a second.
- the etching removal process is not particularly limited, but may be a chemical etching process using an acid aqueous solution or an alkali aqueous solution, or may be a dry etching process.
- the removal of the barrier layer by the chemical etching treatment is performed, for example, by immersing the structure after the anodizing treatment step in an acid aqueous solution or an alkali aqueous solution, filling the inside of the micropore with the acid aqueous solution or the alkali aqueous solution, For example, the surface of the micropore opening side is brought into contact with a pH (hydrogen ion index) buffer solution, and only the barrier layer can be selectively dissolved.
- a pH (hydrogen ion index) buffer solution for example, the surface of the micropore opening side is brought into contact with a pH (hydrogen ion index) buffer solution, and only the barrier layer can be selectively dissolved.
- an acid aqueous solution when used, it is preferable to use an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture thereof.
- concentration of the aqueous acid solution is preferably 1% by mass to 10% by mass.
- the temperature of the aqueous acid solution is preferably 15 to 80 ° C, more preferably 20 to 60 ° C, and further preferably 30 to 50 ° C.
- an alkaline aqueous solution it is preferable to use an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide.
- the concentration of the alkaline aqueous solution is preferably 0.1% by mass to 5% by mass.
- the temperature of the alkaline aqueous solution is preferably 10 ° C. to 60 ° C., more preferably 15 ° C. to 45 ° C., and further preferably 20 ° C. to 35 ° C.
- the alkaline aqueous solution may contain zinc and other metals. Specifically, for example, 50 g / L, 40 ° C. phosphoric acid aqueous solution, 0.5 g / L, 30 ° C. sodium hydroxide aqueous solution, 0.5 g / L, 30 ° C. potassium hydroxide aqueous solution, etc. are preferably used. It is done.
- the buffer solution corresponding to the acid aqueous solution or alkali aqueous solution mentioned above can be used suitably.
- the immersion time in the acid aqueous solution or alkaline aqueous solution is preferably 8 minutes to 120 minutes, more preferably 10 minutes to 90 minutes, and further preferably 15 minutes to 60 minutes.
- a gas species such as a Cl 2 / Ar mixed gas is preferably used.
- the metal filling step is a step of filling the inside of the micropores in the anodic oxide film with an electrolytic plating process after the barrier layer removing step.
- the same methods electrolytic plating method or electroless plating method as those described in the paragraph and [FIG. 4] can be mentioned.
- an aluminum substrate exposed through a micropore after the barrier layer removing step described above can be used as an electrode.
- the substrate removal step is a step of removing the aluminum substrate after the metal filling step to obtain a metal-filled microstructure.
- the treatment solution is used to dissolve only the aluminum substrate without dissolving the metal filled in the micropores and the anodic oxide film as the insulating base material in the metal filling step. And the like.
- the treatment liquid examples include aqueous solutions of mercury chloride, bromine / methanol mixture, bromine / ethanol mixture, aqua regia, hydrochloric acid / copper chloride mixture, etc. Among them, a hydrochloric acid / copper chloride mixture is preferable.
- the concentration of the treatment liquid is preferably 0.01 mol / L to 10 mol / L, more preferably 0.05 mol / L to 5 mol / L.
- the treatment temperature is preferably ⁇ 10 ° C. to 80 ° C., and preferably 0 ° C. to 60 ° C.
- the trimming process is a process of removing only a part of the insulating base material on the surface of the anisotropic conductive member after the conductive path forming process and projecting the conductive path.
- the trimming treatment is not particularly limited as long as it does not dissolve the metal constituting the conduction path.
- an acid aqueous solution an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture thereof
- an aqueous solution of Especially, the aqueous solution which does not contain chromic acid is preferable at the point which is excellent in safety
- the concentration of the acid aqueous solution is preferably 1% by mass to 10% by mass.
- the temperature of the acid aqueous solution is preferably 25 ° C. to 60 ° C.
- an alkaline aqueous solution it is preferable to use an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide.
- the concentration of the alkaline aqueous solution is preferably 0.1% by mass to 5% by mass.
- the temperature of the alkaline aqueous solution is preferably 20 ° C. to 50 ° C. Specifically, for example, 50 g / L, 40 ° C.
- the immersion time in the acid aqueous solution or alkali aqueous solution is preferably 8 minutes to 120 minutes, more preferably 10 minutes to 90 minutes, and further preferably 15 minutes to 60 minutes.
- the immersion time refers to the total of each immersion time when a short immersion process (trimming process) is repeated. In addition, you may perform a washing process between each immersion process.
- the insulating substrate and the end of the conduction path are processed to be in the same plane after the conduction path forming process, It is preferable to selectively remove (trim) the material.
- examples of the method of processing in the same plane include physical polishing (for example, free abrasive polishing, back grinding, surface planar, etc.), electrochemical polishing, polishing combining these, and the like.
- heat treatment can be performed for the purpose of reducing distortion in the conduction path caused by metal filling.
- the heat treatment is preferably performed in a reducing atmosphere from the viewpoint of suppressing metal oxidation.
- the heat treatment is preferably performed at an oxygen concentration of 20 Pa or less, and more preferably performed in a vacuum.
- the vacuum means a state of a space having a gas density or atmospheric pressure lower than that of the atmosphere.
- the resin layer forming step is a step of forming a resin layer on the surface of the insulating substrate and the protruding portion of the conduction path after the trimming step.
- a resin composition containing the above-described antioxidant material, polymer material, solvent (for example, methyl ethyl ketone) or the like is used to protrude the surface of the insulating substrate and the conduction path. Examples include a method of applying to a part, drying, and firing as necessary.
- the coating method of the resin composition is not particularly limited.
- the drying method after coating is not particularly limited, for example, a treatment of heating at a temperature of 0 ° C. to 100 ° C. in the atmosphere for several seconds to several tens of minutes, and a temperature of 0 ° C. to 80 ° C. under reduced pressure, Examples of the treatment include heating for 10 minutes to several hours.
- the baking method after drying is not particularly limited because it varies depending on the polymer material to be used. However, when a polyimide resin is used, for example, a treatment of heating at a temperature of 160 ° C. to 240 ° C. for 2 minutes to 60 minutes, etc. In the case of using an epoxy resin, for example, a treatment of heating at a temperature of 30 ° C. to 80 ° C. for 2 minutes to 60 minutes may be mentioned.
- each process described above can be carried out as a single wafer, or can be continuously processed with a web using an aluminum coil as a raw fabric. Moreover, when performing a continuous process, it is preferable to install an appropriate washing
- the present invention is basically configured as described above. As described above, the laminated device and the manufacturing method of the laminated device of the present invention have been described in detail. However, the present invention is not limited to the above-described embodiment, and various improvements or modifications can be made without departing from the gist of the present invention. Of course it is also good.
- the joint strength was evaluated by measuring the shear strength using a universal bond tester Dage-4000 (manufactured by Nordson Advanced Technology Co., Ltd.). As the bonding strength, the bonding strength value per area of the semiconductor element was determined from the obtained breaking load. The bonding strength was evaluated according to the following evaluation criteria. “A”: 20 MPa ⁇ joining strength “B”: 10 MPa ⁇ joining strength ⁇ 20 MPa “D”: bonding strength ⁇ 10 MPa
- the heat dissipation is measured using a thermal conduction measuring device TCM1001 (product name) manufactured by Resuka Co., Ltd., and the laser flash method thermal constant measuring device TC-9000H manufactured by Advanced Riko Co., Ltd. (Model) was used for evaluation.
- TCM1001 product name
- TC-9000H manufactured by Advanced Riko Co., Ltd.
- the heat dissipation was evaluated according to the evaluation criteria shown below for the average value of thermal conductivity.
- a temperature cycle test was performed according to TCT (Temperature Cycle Test according to JESD22-A104 standard). The temperature range was ⁇ 40 ° C. to 125 ° C., and Soak Mode 3 (each temperature holding time 10 minutes). The cycle time was 1 hour (1 cycle / hour). In addition, it is preferable that reliability is 1 hour or more.
- a shear strength test and a heat dissipation test were performed under the above-described conditions. Reliability was evaluated according to the following evaluation criteria. “A”: There is no change in the evaluation of the shear strength test and the evaluation of the heat dissipation test. “B”: Either of the evaluation of the shear strength test and the evaluation of the heat dissipation test is evaluated. Decrease “C”: Decrease in both the evaluation of the shear strength test and the evaluation of the heat dissipation test
- Example 1 78 has a silicon oxide insulating layer formed on the surface of a silicon substrate.
- the silicon oxide insulating layer has a terminal 92 and a terminal 92 in plan view of the terminal 92 as shown in FIG.
- the surface 91 is formed with an area ratio of 45%.
- the terminal 92 is made of copper.
- the test substrate 90 was manufactured by the following processes (i) to (iv). (I) Using a photolithography method, a resist pattern of the terminal 92 was formed on the surface of the silicon substrate so that the area ratio in the surface 91 having the terminal 92 in plan view was 45%, as shown in FIG. .
- a seed layer serving as a starting point of plating was provided in a resist opening (concave portion) of the resist pattern.
- a metal was plated on the resist opening.
- the resist was peeled off so that the terminals were aligned on the silicon substrate surface.
- a silicon oxide insulating layer was formed on the entire surface of the silicon substrate by chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- Vi The terminal was exposed and the surface was smoothed by CMP polishing.
- two test substrates 90 shown in FIG. 78 were joined using DBI (Direct Bond Interconnect).
- DBI Direct Bond Interconnect
- the surface on the side to be bonded of the test substrate 90 was polished by CMP to smooth the surface.
- the upper and lower test substrates 90 are aligned by alignment marks provided around the test substrate 90 and held at a temperature of 300 ° C. for 2 hours with a pressure of 200 MPa applied to the bonding surface. did.
- the “recess amount is 0” shown in the “recess amount” column of Table 1 below means that the silicon oxide insulating layer including the terminal is polished and the terminal and the silicon oxide insulating layer are flush with each other.
- the end surface 30 c of the terminal 30 a and the end surface 30 c of the terminal 30 b are in a state of being in agreement with the surface 36 a of the passivation layer 36.
- the silicon oxide insulating layer is removed by dry etching using a fluorine-based gas to project the terminal.
- the amount of recess was controlled by changing the dry etching process time of the recess process.
- Example 2 was the same as Example 1 except that the bonding configuration was SAB (Surface Activated Bond).
- Example 3 was the same as Example 1 except that the recess amount was 80 nm, the bonding form was SAB, and the sealing resin was used when bonding the test substrate 90.
- the recess amount was adjusted by changing the dry etching processing time as described above. The sealing resin will be described in detail later.
- Example 4 was the same as Example 1 except that the recess amount was 200 nm, the bonding form was SAB, and the sealing resin was used when bonding the test substrate 90.
- the recess amount was adjusted by changing the dry etching processing time as described above.
- Example 5 In Example 5, the recess amount is 200 nm, the test substrate 90 is bonded via an anisotropic conductive member, and the sealing resin is used when the test substrate 90 is bonded. And the same.
- the recess amount was adjusted by changing the dry etching processing time as described above.
- Example 6 In Example 6, the recess amount is 200 nm, the test substrate 90 is bonded via an anisotropic conductive member, the number of layers is five, and a sealing resin is used when the test substrate 90 is bonded. It was the same as Example 1 except the point which had. The recess amount was adjusted by changing the dry etching processing time as described above. (Example 7) In Example 7, the recess amount is 800 nm, the test substrate 90 is bonded via an anisotropic conductive member, and the sealing resin is used when the test substrate 90 is bonded. And the same. The recess amount was adjusted by changing the dry etching processing time as described above.
- Comparative Example 1 In Comparative Example 1, two test substrates 100 shown in FIG. 79 were joined using solder. The test substrate 100 shown in FIG. 79 has the same configuration as the test substrate 90 shown in FIG. 78 except that the area ratio on the surface 101 having the terminals 92 in plan view of the terminals 92 is 23%. In Comparative Example 1, the recess amount was 5 ⁇ m. The recess amount was adjusted by changing the dry etching processing time as described above. In Comparative Example 1, the proportion of the area of the terminals 92 electrically connected among the terminals 92 was 80%.
- the test substrate 100 is a process for manufacturing the test substrate 90 described above except that the area ratio of the surface 92 having the terminals 92 in the plan view of the terminals 92 is 23% in the process (i) of the test substrate 90 described above. It was produced in the same manner as (i) to (iv).
- Comparative Example 2 Comparative Example 2 was the same as Comparative Example 1 except that the sealing resin was used when the test substrate 100 was bonded.
- Comparative Example 3 Comparative Example 3 was the same as Example 2 except that the test substrate 100 was used and the above-described terminal area ratio was 80%.
- Comparative Example 4 Comparative Example 4 was the same as Example 1 except that the test substrate 100 was used and that the above-described terminal area ratio was 80%.
- Comparative Example 5 Comparative Example 5 was the same as Example 5 except that the test substrate 100 was used and the ratio of the above-described terminal area was 80%.
- Comparative Example 6 Comparative Example 6 was carried out except that a test board having an area ratio of 35% on the surface 101 having the terminals 92 in a plan view of the terminals 92 was used, and that the above-mentioned terminal area ratio was 52%. Same as Example 5.
- the test substrate with the above-described terminal 92 having an area ratio of 35% is manufactured by the above-described test substrate 90 except that the area ratio of the above-described terminal 92 is set to 35% in the above-described test substrate 90 manufacturing process (i). It was produced in the same manner as in processes (i) to (iv).
- Comparative Example 7 In Comparative Example 7, except that a test board having an area ratio of 45% in the surface 101 having the terminals 92 in a plan view of the terminals 92 and the ratio of the area of the terminals 92 described above was 52%, Same as Example 5.
- test substrate having the area ratio of the terminal 92 of 45% is the same as that of the test substrate 90 except that the area ratio of the terminal 92 is 45% in the manufacturing process (i) of the test substrate 90 described above. It was produced in the same manner as in processes (i) to (iv).
- Comparative Example 8 Comparative Example 8 was the same as Example 5 except that the test substrate 100 was used.
- the above-mentioned aluminum substrate was subjected to electropolishing using an electropolishing liquid having the following composition under the conditions of a voltage of 25 V, a liquid temperature of 65 ° C., and a liquid flow rate of 3.0 m / min.
- the cathode was a carbon electrode, and GP0110-30R (manufactured by Takasago Seisakusho Co., Ltd.) was used as the power source.
- the flow rate of the electrolyte was measured using a vortex type flow monitor FLM22-10PCW (manufactured by ASONE CORPORATION).
- Electrolytic polishing liquid composition -660 mL of 85% phosphoric acid (reagent manufactured by Wako Pure Chemical Industries, Ltd.) ⁇ Pure water 160mL ⁇ Sulfuric acid 150mL ⁇ Ethylene glycol 30mL
- the aluminum substrate after the electrolytic polishing treatment was subjected to an anodizing treatment by a self-ordering method according to the procedure described in JP-A-2007-204802.
- the aluminum substrate after the electropolishing treatment was pre-anodized for 5 hours with an electrolyte solution of 0.50 mol / L oxalic acid at a voltage of 40 V, a liquid temperature of 16 ° C., and a liquid flow rate of 3.0 m / min. .
- a film removal treatment was performed in which the aluminum substrate after the pre-anodizing treatment was immersed in a mixed aqueous solution (liquid temperature: 50 ° C.) of 0.2 mol / L chromic anhydride and 0.6 mol / L phosphoric acid for 12 hours. Thereafter, reanodization treatment was performed for 3 hours and 45 minutes with an electrolyte of 0.50 mol / L oxalic acid at a voltage of 40 V, a liquid temperature of 16 ° C., and a liquid flow rate of 3.0 m / min. An oxide film was obtained.
- the cathode was a stainless electrode, and the power supply was GP0110-30R (manufactured by Takasago Seisakusho Co., Ltd.). Further, NeoCool BD36 (manufactured by Yamato Kagaku Co., Ltd.) was used as the cooling device, and Pair Stirrer PS-100 (manufactured by EYELA Tokyo Rika Kikai Co., Ltd.) was used as the stirring and heating device. Furthermore, the flow rate of the electrolytic solution was measured using a vortex flow monitor FLM22-10PCW (manufactured by ASONE Corporation).
- electrolytic treatment electrolytic removal treatment
- electrolytic removal treatment electrolytic removal treatment
- an etching process etching removal process
- the average opening diameter of the micropores present in the anodized film after the barrier layer removing step was 60 nm.
- the average opening diameter was calculated as an average value obtained by taking a surface photograph (magnification 50000 times) with a FE-SEM (Field emission-Scanning Electron Microscope) and measuring 50 points.
- the average thickness of the anodic oxide film after the barrier layer removing step was 80 ⁇ m.
- the average thickness is an average obtained by cutting the anodized film with FIB (Focused Ion Beam) in the thickness direction, photographing a surface photograph (magnification 50000 times) with FE-SEM, and measuring 10 points. Calculated as value.
- the density of micropores present in the anodic oxide film was about 100 million / mm 2 .
- the density of the micropores was measured and calculated by the method described in paragraphs ⁇ 0168> and ⁇ 0169> of JP-A-2008-270158. Further, the degree of ordering of the micropores present in the anodic oxide film was 92%. The degree of ordering was calculated by taking a surface photograph (magnification: 20000 times) with FE-SEM, measuring it by the method described in paragraphs ⁇ 0024> to ⁇ 0027> of JP-A-2008-270158.
- ⁇ Metal filling process> electrolytic plating was performed using the aluminum substrate as the cathode and platinum as the positive electrode. Specifically, a metal-filled microstructure in which copper was filled in the micropores was produced by performing constant current electrolysis using a copper plating solution having the composition shown below.
- the constant current electrolysis is performed by performing cyclic voltammetry in a plating solution using a power source (HZ-3000) manufactured by Hokuto Denko Co., Ltd. using a plating apparatus manufactured by Yamamoto Metal Testing Co., Ltd. After confirming the potential, the treatment was performed under the following conditions.
- the surface of the anodic oxide film after filling the micropores with metal was observed with FE-SEM, and the presence or absence of pores due to metal in 1000 micropores was observed to determine the sealing rate (number of sealed micropores / 1000 ) was calculated to be 96%.
- the anodic oxide film after filling the micropores with metal was cut with FIB in the thickness direction, and the cross-section was taken with FE-SEM to take a surface photograph (magnification 50000 times). As a result of confirmation, it was found that the inside of the sealed micropore was completely filled with metal.
- a metal-filled microstructure was prepared by dissolving and removing the aluminum substrate by immersing it in a 20 mass% mercury chloride aqueous solution (raised) at 20 ° C. for 3 hours.
- ⁇ Trimming process> The metal-filled microstructure after the substrate removal step is immersed in an aqueous sodium hydroxide solution (concentration: 5 mass%, liquid temperature: 20 ° C.), and the immersion time is adjusted so that the height of the protruding portion is 500 nm.
- the surface of the aluminum anodic oxide film was selectively dissolved, then washed with water and dried to produce a structure in which a copper cylinder as a conduction path was projected.
- ⁇ Adhesive layer forming step> An anisotropic conductive member was produced by forming an adhesive layer on the structure after the trimming process by the method described below.
- ⁇ Adhesive layer> As a commercial product of a polyamic acid ester solution (including dimethyl sulfoxide, trialkoxyamidocarboxysilane, and oxime derivative) using gamma-butyrolactone as a solvent, LTC9320 (manufactured by FUJIFILM Electronics Materials Co., Ltd.) was used. This solution is applied to the surface of the insulating base material from which the conductive path protrudes, dried and formed into a film, and then the imidization reaction is allowed to proceed at 200 ° C. for 3 hours in a nitrogen-substituted reactor (oxygen concentration of 10 ppm or less).
- LTC9320 manufactured by FUJIFILM Electronics Materials Co., Ltd.
- the adhesion layer which consists of a polyimide resin layer was formed in the thickness of 500 nm.
- the thickness of the adhesive layer was adjusted by adding a solvent (methyl ethyl ketone).
- the average thickness of the metal-filled microstructure excluding the resin layer was 30 ⁇ m.
- ⁇ Sealing resin> The components shown below were dissolved in methyl ethyl ketone at the ratio shown below, and first, a resin layer coating solution having a solid content concentration of 60.6% by weight was prepared. When forming the sealing resin, the resin layer coating solution was diluted. The resin layer coating solution was applied to the surface of the adhesive layer and dried to form a sealing resin. The thickness of the sealing resin was adjusted by further adding a solvent (methyl ethyl ketone) to the coating liquid having the following formulation so as to be 1 ⁇ m. Moreover, drying after application
- the antioxidant material was blended with 0.01% by mass of 2-mercaptobenzothiazole.
- (Migration prevention material) As the migration prevention material, Toa Gosei Co., Ltd., trade name IXE-100 (median diameter 1 ⁇ m, cation exchange, heat-resistant temperature 550 ° C.) 2.5% by mass was blended.
- (Inorganic filler) As the inorganic filler, aluminum nitride nanoparticles, an average particle size of 100 nm, and 55% by mass of Sigma-Aldrich were mixed.
Abstract
Description
さらには、複数の半導体素子等を積層して配置して、電子部品を小型化または高密度化することがなされている。上述のように半導体素子等を積層した場合、半導体素子で発生した熱が、他の半導体素子の動作不良を引き起こすことがある。
特許文献1の積層型半導体パッケージは、第1の回路基板と第1の回路基板に実装された第1の半導体素子を含む第1の半導体パッケージと、第2の回路基板と第2の回路基板に実装された第2の半導体素子を含み第1の半導体パッケージに積層された第2の半導体パッケージと、第1の半導体素子上及び第1の半導体素子の周辺の第1の回路基板上に配置される熱伝導材料とを有する。
特許文献2の積層型半導体パッケージは、第1の回路基板と、第1の回路基板に第1の半導体素子が実装された第1の半導体パッケージと、第2の回路基板と、第2の回路基板に第2の半導体素子が実装され、第1の半導体パッケージに積層された第2の半導体パッケージと、第1の半導体を封止する封止樹脂と、封止樹脂に接して配置される導電層と、導電層と接続し第1の回路基板上に配置されるサーマルビアとを有する。
また、特許文献4には、半導体チップで生じた熱を効率よく放熱できる電子部品内蔵基板が記載されている。特許文献4の電子部品内蔵基板は、複数の絶縁層とそれぞれ配線パターンを含む複数の配線層とが交互に積層された積層体と、裏面が積層体と接するように積層体の表面に載置された半導体チップと、積層体を貫通して半導体チップの裏面と接触し、かつ配線層それぞれに含まれる配線パターンと接触する第1のビア導体とを備える。
特許文献5では、熱消散を改善するために、3次元積層集積回路内の予め定められたデバイス層で指定の能動回路の上または下方に適切な深さのダミースルーシリコンビア構造を位置させている。
複数の端子は、積層方向に導通する導通路を有する異方導電性部材を介して接合されており、導通路は、直径が100nm以下であることが好ましい。
異方導電性部材は、絶縁性基材と、絶縁性基材の厚み方向に貫通し、互いに電気的に絶縁された状態で設けられた、複数の導通路とを有することが好ましい。
また、インターポーザーを有することが好ましい。
複数の端子は、積層方向に導通する導通路を有する異方導電性部材を介して接合されており、導通路は、直径が100nm以下であることが好ましい。
異方導電性部材は、絶縁性基材と、絶縁性基材の厚み方向に貫通し、互いに電気的に絶縁された状態で設けられた、複数の導通路とを有することが好ましい。
また、インターポーザーを有することが好ましい。
なお、以下に説明する図は、本発明を説明するための例示的なものであり、以下に示す図に本発明が限定されるものではない。
なお、以下において数値範囲を示す「~」とは両側に記載された数値を含む。例えば、εが数値α~数値βとは、εの範囲は数値αと数値βを含む範囲であり、数学記号で示せばα≦ε≦βである。
「平行」、および「直交」等の角度は、特に記載がなければ、該当する技術分野で一般的に許容される誤差範囲を含む。また、「全面」等は、該当する技術分野で一般的に許容される誤差範囲を含む。
本発明の半導体とは、半導体素子、回路素子、およびセンサ素子等のことであり、半導体素子には受動素子および能動素子が含まれる。このように、本発明の半導体とは、物質としての半導体を示すものではない。
上述の直接電気的に接続されているとは、半導体素子12の端子30と半導体素子14の端子30とが直接接続された状態のことをいう。
また、例えば、半導体素子12、14同士を電気的に接続する端子30aと半導体素子12、14同士を電気的に接続しない端子30bとは、形状および大きさが同じである。
なお、上述の平面視での端子30を有する面31における面積率のことを、単に、面積率ともいう。
半導体素子12と半導体素子14とでは、複数の端子30のうち、半導体素子12の端子30が他の半導体素子14の端子30と電気的に接続されている端子30aの面積の割合が50%未満である。これにより、積層デバイス10は接合強度が確保され、かつ放熱性が優れたものとなる。さらには、放熱性が優れることにより、半導体素子12、14等の半導体の温度上昇が抑制され、積層デバイス10の信頼性も向上する。
接合強度とは、半導体素子12と半導体素子14との接合界面における剥離強度のことであり、シェア強度により評価される。
半導体素子12、14は、複数の端子が設けられた面における複数の端子の面積率が40%以上であり、複数の端子のうち、半導体同士を接合しかつ電気的に接続する端子の面積率が50%未満である。半導体素子12、14において平面視での端子30を有する面31における端子30の面積率が40%未満では、半導体素子12、14同士の接合強度を確保することが難しい。一方、半導体素子12、14同士を電気的に接続する端子30aの面積の割合が50%を超えると、放熱性が低下する。
なお、半導体素子12と半導体素子14とは、上述の端子30aの面積率を満たせば端子30の配置は同じでもよい。
半導体素子12、14の複数の端子が設けられた面(電極を有する面)の面積Sは、図2に示すように、半導体素子12、14の平面視での形状が四角であれば、平行な1組の辺の長さをW1とし、残りの平行な1組の辺の長さをW2とするとき、S=W1×W2で表される。
半導体層32の表面32a上に再配線層34が設けられている。再配線層34では、半導体層32の素子領域に電気的に接続される配線37が設けられている。配線37にパッド38が設けられており、配線37とパッド38は導通する。配線37とパッド38とにより、素子領域との信号の授受が可能となり、かつ素子領域への電圧等の供給ができる。
また、再配線層34には、配線37が設けられていないが、パッド38だけが設けられている。配線37に設けられていないパッド38に端子30bが設けられている。端子30bは半導体層32と電気的に接続されていない。
例えば、図4に示す構成の半導体素子12と半導体素子14とを接合した場合、複数の端子同士が直接接合されていてもよく、図5に示すように、互いに対応する端子30a同士が直接接続され、互いに対応する端子30b同士が直接接続される。このように半導体素子12と半導体素子14とは、端子30aにより相互に電気的に接続され、端子30bにより電気的に接続されることなく物理的に接続される。
リセス量δが200nm未満では、図4に示す端子30aと端子30bが突出していない構成と略同じであり、高い精度で研磨する必要がある。一方、リセス量δが1μmを超えると、パッド電極を設ける一般的な構成と同じであり、半田ボール等を用いて接合する必要がある。
図6に示す構成では、端子30aと端子30bがパッシベーション層36の表面36aに対して突出しているため、パッシベーション層36の表面36aに、端子30aと端子30bを保護するための樹脂層39を設けてもよい。
端子30aの端面30cと端子30bの端面30cは、いずれもパッシベーション層36の表面36aから最も離れた位置にある面のことであり、一般的に上面と呼ばれる面のことである。
再配線層34は、電気的に絶縁性を有するもので構成され、例えば、ポリイミドで構成される。
また、パッシベーション層36も、電気的に絶縁性を有するもので構成され、例えば、窒化珪素(SiN)またはポリイミドで構成される。
配線37およびパッド38は、導電性を有するもので構成され、例えば、銅、銅合金、アルミニウム、またはアルミニウム合金等で構成される。
なお、端子30aおよび端子30bは、導電性を有するものであればよく、金属または合金で構成されることに限定されるものではなく、半導体素子分野において端子、または電極パッドと呼ばれるものに用いられる材料を適宜利用可能である。
また、図8に示す積層デバイス10のように、3つの半導体素子12、14、16に、さらに1つのインターポーザー18を有する構成でもよい。3つの半導体素子12、14、16と1つのインターポーザー18とにより積層体19が構成される。図8示す積層デバイス10では、積層方向Dsにおける半導体素子12と半導体素子14との間にインターポーザー18が設けられている。半導体素子14と半導体素子16とが直接接合されている。
なお、3つの半導体素子12、14、16の端子30は、端子30aおよび端子30bについては上述の要件を満たす。図7に示す積層デバイス10でも図8示す積層デバイス10でも、図1に示す積層デバイス10と同様に、接合強度が確保され、かつ放熱性が優れる。
インターポーザー18の構成は、上述の機能を実現することができれば、その構成は特に限定されるものではなく、公知のものを含め適宜利用可能である。インターポーザー18は、例えば、ポリイミド等の有機材料、ガラス、セラミックス、金属、シリコン、および多結晶シリコン等を用いて構成することができる。
図10は本発明の実施形態の積層デバイスに用いられる異方導電性部材の構成の一例を示す平面図であり、図11は本発明の実施形態の積層デバイスに用いられる異方導電性部材の構成の一例を示す模式的断面図である。図11は図10の切断面線IB-IB断面図である。また、図12は異方導電材の構成の一例を示す模式的断面図である。
ここで、「互いに電気的に絶縁された状態」とは、絶縁性基材の内部に存在している各導通路が絶縁性基材の内部において互いに各導通路間の導通性が十分に低い状態であることを意味する。
異方導電性部材20は、導通路42が互いに電気的に絶縁されており、絶縁性基材40の厚み方向Z(図11参照)と直交する方向xには導電性が十分に低く、厚み方向Zに導電性を有する。このように異方導電性部材20は異方導電性を示す部材である。異方導電性部材20は厚み方向Zを、積層デバイス10の積層方向Dsに一致させて配置される。
さらに、導通路42は、図11に示すように、絶縁性基材40の表面40aおよび40bから突出した突出部分42aおよび突出部分42bを有してもよい。異方導電性部材20は、さらに、絶縁性基材40の表面40aおよび裏面40bに設けられた樹脂層44を具備してもよい。樹脂層44は、粘着性を備え、接合性を付与するものでもある。突出部分42aおよび突出部分42bの長さは、6nm以上であることが好ましく、より好ましくは30nm~500nmである。
同様に、図12および図11の導通路42は両端に突出部分42aおよび突出部分42bがあるが、これに限定されるものではなく、絶縁性基材40の少なくとも樹脂層44を有する側の表面に突出部分を有する構成でもよい。
が好ましい。
ここで、異方導電性部材20の厚みhは、異方導電性部材20を、電解放出形走査型電子顕微鏡により20万倍の倍率で観察し、異方導電性部材20の輪郭形状を取得し、厚みhに相当する領域について10点測定した平均値のことである。
また、異方導電性部材20のTTV(Total Thickness Variation)は、異方導電性部材20をダイシングで支持体46ごと切断し、異方導電性部材20の断面形状を観察して求めた値である。
支持体46は、異方導電性部材20を支持するものであり、例えば、シリコン基板で構成されている。支持体46としては、シリコン基板以外に、例えば、SiC、SiN、GaNおよびアルミナ(Al2O3)等のセラミックス基板、ガラス基板、繊維強化プラスチック基板、ならびに金属基板を用いることができる。繊維強化プラスチック基板には、プリント配線基板であるFR-4(Flame Retardant Type 4)基板等も含まれる。
ここで、透明とは、位置合せに使用する波長の光で透過率が80%以上であることをいう。このため、波長400~800nmの可視光全域で透過率が低くてもよいが、波長400~800nmの可視光全域で透過率が80%以上であることが好ましい。透過率は、分光光度計により測定される。
剥離剤49には、例えば、日東電工社製リバアルファ(登録商標)、およびソマール株式会社製ソマタック(登録商標)等を用いることができる。
また、図14に示す積層デバイス10のように、インターポーザー18と異方導電性部材20を用いて、半導体素子12と半導体素子14と半導体素子16を積層方向Dsに積層して接合し、かつ電気的に接続した構成としてもよい。3つの半導体素子12、14、16と1つのインターポーザー18と1つの異方導電性部材20とにより積層体19が構成される。
図13示す積層デバイス10でも、図14示す積層デバイス10でも、図1に示す積層デバイス10と同様に、接合強度が確保され、かつ放熱性が優れる。
センサチップ54は、光を検出する光センサを有するものである。光センサは、光を検出することができれば、特に限定されるものではなく、例えば、CCD(Charge Coupled
Device)イメージセンサまたはCMOS(Complementary Metal Oxide Semiconductor)イメージセンサが用いられる。
なお、図15に示す積層デバイス10では、半導体素子52とセンサチップ54とを異方導電性部材20を介して接続したが、これに限定されるものではなく、半導体素子52とセンサチップ54とを直接接合する構成でもよい。
レンズ56は、センサチップ54に光を集光することができれば、その構成は特に限定されるものではなく、例えば、マイクロレンズと呼ばれるものが用いられる。
素子領域とは、電子素子として機能するための、コンデンサ、抵抗およびコイル等の各種の素子構成回路等が形成された領域である。素子領域には、例えば、フラッシュメモリ等のようなメモリ回路、マイクロプロセッサおよびFPGA(field-programmable gate array)等のような論理回路が形成された領域、無線タグ等の通信モジュールならびに配線が形成された領域がある。素子領域には、これ以外に、発信回路、またはMEMS(Micro Electro Mechanical Systems)が形成されてもよい。MEMSとは、例えば、センサ、アクチュエーターおよびアンテナ等である。センサには、例えば、加速度、音および光等の各種のセンサが含まれる。
積層デバイスでは、例えば、論理回路を有する半導体素子と、メモリ回路を有する半導体素子の組合せとすることができる。また、半導体素子を全てメモリ回路を有するものとしてもよく、また、全て論理回路を有するものとしてもよい。また、積層デバイス10における半導体素子の組合せとしては、センサ、アクチュエーターおよびアンテナ等と、メモリ回路と論理回路との組み合わせでもよく、積層デバイス10の用途等に応じて適宜決定されるものである。
[積層デバイスの製造方法]
積層デバイスの製造方法の第1の例について説明する。
図16~図18は本発明の実施形態の積層デバイスの製造方法の第1の例を工程順に示す模式図である。
図16~図18に示す積層デバイスの製造方法の第1の例において、図1に示す積層デバイス10、ならびに図2および図4に示す半導体素子12、14と同一構成物には同一符号を付して、その詳細な説明は省略する。
積層デバイスの製造方法の第1の例は、チップオンウエハに関するものであり、図1に示す積層デバイス10の製造方法を示す。
各半導体素子14を、端子30aおよび端子30bが設けられた表面14aを第1の半導体ウエハ60に向けて配置する。
次に、第1の半導体ウエハ60のアライメントマークと、半導体素子14のアライメントマークとを用いて第1の半導体ウエハ60と半導体素子14との位置合せを行う。
アライメントマークを用いた位置合せは、例えば、第1の半導体ウエハ60のアライメントマークと、半導体素子14のアライメントマークとを同時に撮像し、第1の半導体ウエハ60のアライメントマークの画像と、半導体素子14のアライメントマークの画像を基に、第1の半導体ウエハのアライメントマークの位置情報と、半導体素子14のアライメントマークの位置情報とを求め位置合せを行う。
なお、位置合せについては、第1の半導体ウエハ60のアライメントマークの画像または反射像と、半導体素子14のアライメントマークの画像または反射像について、デジタル画像データを得ることができれば、その構成は特に限定されるものではなく、公知の撮像装置を適宜利用可能である。
仮接合とは、半導体素子または半導体ウエハを、接合する対象物に対して位置合せした状態で、接合する対象物上に固定することをいう。
本接合は、上述のように一括して行うことにより、タクトタイムを低減でき、生産性を高くできる。
上述のDBIは、半導体素子14および第1の半導体ウエハ60に、シリコン酸化膜を積層し、化学的機械研磨を施す。その後、プラズマ処理によってシリコン酸化膜界面を活性化させ、半導体素子14および第1の半導体ウエハ60を接触させることにより両者を接合する。
上述のSABは、半導体素子14および第1の半導体ウエハ60の各接合面を真空中で表面処理し活性化する。この状態で、半導体素子14および第1の半導体ウエハ60を、常温環境で接触させることにより両者を接合する。表面処理には、アルゴン等の不活性ガスのイオン照射、または中性原子ビーム照射が用いられる。
なお、個片化については、ダイシングに限定されるものではなく、レーザースクライビングを用いてもよい。
また、半導体素子12を素子領域に接合する工程では、複数の半導体素子14を仮接合した後、全て一括して接合したが、これに限定されるものではない。接合方法によっては、仮接合ができないものもある。この場合、半導体素子12の仮接合を省略してもよい。さらには、半導体素子14を、第1の半導体ウエハ60の素子領域に1つずつ接合してもよい。
半導体素子14および第1の半導体ウエハ60の搬送およびピッキング等、ならびに仮接合および本接合については、公知の半導体製造装置を用いることにより実現できる。
上述の本接合に用いる装置としては、例えば、三菱重工工作機械、ボンドテック、株式会社PMT、アユミ工業、東京エレクトロン(TEL)、EVG、ズースマイクロテック株式会社(SUSS)、ムサシノエンジニアリング等各社のウエハ接合装置を用いることができる。
仮接合および本接合のそれぞれの接合に際しては、接合時の雰囲気、加熱温度、加圧力(荷重)、および処理時間が制御因子として挙げられるが用いる半導体素子等のデバイスに適合した条件を選ぶことができる。
加熱温度は、温度100℃~400℃まで種々選択可能であり、かつ昇温速度に関しても10℃/分~10℃/秒まで加熱ステージの性能、または加熱方式に従って選択することができる。冷却に関しても同様である。またステップ状に加熱することも可能であり、数段に分け、順次加熱温度を上げて接合することも可能である。
圧力(荷重)に関しても樹脂封止剤の特性等に応じて急速に加圧したり、ステップ状に加圧することを選択できる。
このような手順は、様々に組み替えることができ、大気下で加圧後、真空状態にして加熱してもよいし、真空化、加圧、加熱を一気に行ってもよい。これらの組合せの例を図19~図25に示す。
また、面内の加圧分布、加熱分布を接合時に個別に制御する機構を利用すれば接合の歩留まり向上につなげられる。
仮接合に関しても同じように変更可能で、例えば、不活性雰囲気化で行うことにより、半導体素子の電極表面の酸化を抑制できる。更に超音波を付加しながら接合を行うことも可能である。
接合時の雰囲気、加熱温度、および荷重については、例えば、図19~図21に示すように、圧力を減圧した状態で荷重をかけた後に、温度を上昇させてもよい。また、図22、図24および図25に示すように、荷重を加えるタイミングと温度を上げるタイミングとを合わせてもよい。図23に示すように温度を上昇させた後、荷重を加えるようにしてもよい。また、図22および図23に示すように、圧力の減圧のタイミングと温度を上げるタイミングとを合わせてもよい。
温度の上昇も、図19、図20および図24に示すように、ステップ状に上昇させてもよいし、図25に示すように2段階で加熱してもよい。荷重も図21および図24に示すようにステップ状に加えてもよい。
また、圧力を減圧するタイミングは、図19、図21、図23、図24および図25に示すように減圧してから荷重を加えてもよく、図20および図22に示すように減圧のタイミングと荷重を加えるタイミングとを合わせてもよい。この場合、減圧と接合を同時並行する。
図26~図28は本発明の実施形態の積層デバイスの製造方法の第2の例を工程順に示す模式図である。
積層デバイスの製造方法の第2の例は、チップオンウエハに関するものであり、図7に示す積層デバイス10の製造方法を示す。
積層デバイスの製造方法の第2の例は、積層デバイスの製造方法の第1の例に比して、3つの半導体素子12、14、16が積層される点以外は、積層デバイスの製造方法の第1の例と同じである。このため、積層デバイスの製造方法の第1の例と共通する製造方法についての詳細な説明は省略する。
また、半導体素子16は、表面16aに素子領域(図示せず)が設けられ、かつ素子領域にアライメントマーク(図示せず)が設けられている。
次に、図27に示すように、半導体素子14の裏面14bに半導体素子16を仮接合する。次に、全ての半導体素子14を第1の半導体ウエハ60の素子領域に仮接合し、全ての半導体素子14に半導体素子16を仮接合した状態で、予め定めた条件にて本接合を行い、半導体素子14と半導体素子16を接合し、かつ半導体素子14を第1の半導体ウエハ60の素子領域に接合する。これにより、半導体素子14と半導体素子16と第1の半導体ウエハ60において、端子30a同士および端子30b同士が接合される。
次に、図28に示すように、半導体素子14および半導体素子16が接合された第1の半導体ウエハ60を、素子領域毎に、例えば、ダイシングまたはレーザースクライビング等により個片化する。これにより、半導体素子12と半導体素子14と半導体素子16とが接合された積層デバイス10を得ることができる。
積層デバイスの製造方法の第2の例では、全ての半導体素子14を第1の半導体ウエハ60の素子領域に接合した状態で、半導体素子16を接合してもよい。
図29~図30は本発明の実施形態の積層デバイスの製造方法の第3の例を工程順に示す模式図である。
積層デバイスの製造方法の第3の例は、ウエハオンウエハに関するものであり、図1に示す積層デバイス10の製造方法を示す。
積層デバイスの製造方法の第3の例は、積層デバイスの製造方法の第1の例に比して、半導体素子14に代えて第2の半導体ウエハ62を用いる点以外は、積層デバイスの製造方法の第1の例と同じである。このため、積層デバイスの製造方法の第1の例と共通する製造方法についての詳細な説明は省略する。
次に、第1の半導体ウエハ60の表面60aと第2の半導体ウエハ62の表面62aを対向させる。そして、第1の半導体ウエハ60のアライメントマークと、第2の半導体ウエハ62のアライメントマークとを用いて、第1の半導体ウエハ60に対して、第2の半導体ウエハ62の位置合せを行う。
次に、図29に示すように、第1の半導体ウエハ60の表面60aと第2の半導体ウエハ62の表面62aを対向させて、上述の方法を用いて第1の半導体ウエハ60と第2の半導体ウエハ62とを接合する。この場合、仮接合した後に、本接合をしてもよく、本接合だけでもよい。
なお、個片化については、上述のとおりであるため、詳細な説明は省略する。
また、図30に示すように、第1の半導体ウエハ60と第2の半導体ウエハ62が接合された状態で、第1の半導体ウエハ60および第2の半導体ウエハ62のうち、薄くする必要がある半導体ウエハがあれば、化学的機械的研磨(CMP:Chemical Mechanical Polishing)等により、薄くすることができる。
図31~図33は本発明の実施形態の積層デバイスの製造方法の第4の例を工程順に示す模式図である。
積層デバイスの製造方法の第4の例は、チップオンウエハに関するものであり、図9に示す積層デバイス10の製造方法を示す。
積層デバイスの製造方法の第4の例は、積層デバイスの製造方法の第1の例に比して、半導体素子12と半導体素子14とが異方導電性部材20を介して積層されて接合されている点以外は、積層デバイスの製造方法の第1の例と同じである。このため、積層デバイスの製造方法の第1の例と共通する製造方法についての詳細な説明は省略する。
まず、異方導電性部材20が表面14aに設けられた半導体素子14を用意する。
次に、異方導電性部材20を、第1の半導体ウエハ60に向けて半導体素子14を配置する。次に、半導体素子14のアライメントマークと、第1の半導体ウエハ60のアライメントマークとを用いて、第1の半導体ウエハ60に対して、半導体素子14の位置合せを行う。
仮接合に樹脂層44を使うことは方法の1つであり、以下に示す方法でもよい。例えば,封止樹脂等をディスペンサー等で第1の半導体ウエハ60上に供給して、半導体素子14を第1の半導体ウエハ60の素子領域に仮接合してもよいし、第1の半導体ウエハ60上に、事前に供給した絶縁性樹脂フイルム(NCF(Non-conductive Film))を使って半導体素子14を素子領域に仮接合してもよい。
次に、図33に示すように、異方導電性部材20を介して半導体素子14が接合された第1の半導体ウエハ60を、素子領域毎に、ダイシングまたはレーザースクライビング等により個片化する。これにより、半導体素子12と異方導電性部材20と半導体素子14とが接合された積層デバイス10を得ることができる。
また、仮接合プロセスにおける温度条件は特に限定されないが、0℃~300℃であることが好ましく、10℃~200℃であることがより好ましく、常温(23℃)~100℃であることが特に好ましい。
同様に、仮接合プロセスにおける加圧条件は特に限定されないが、10MPa以下であることが好ましく、5MPa以下であることがより好ましく、1MPa以下であることが特に好ましい。
また、本接合における加圧条件は特に限定されないが、30MPa以下であることが好ましく、0.1MPa~20MPaであることがより好ましい。
また、本接合の時間は特に限定されないが、1秒~60分であることが好ましく、5秒~10分であることがより好ましい。
上述の条件で本接合を行うことにより、樹脂層が、半導体素子14の電極間に流動し、接合部に残存し難くなる。
上述のように本接合では、複数の半導体素子14の接合を一括して行うことにより、タクトタイムを低減でき、生産性を高くできる。
図34~図36は本発明の実施形態の積層デバイスの製造方法の第5の例を工程順に示す模式図である。
積層デバイスの製造方法の第5の例は、積層デバイスの製造方法の第2の例に比して、3つの半導体素子12、14、16が異方導電性部材20を介して積層されて接合される点以外は、積層デバイスの製造方法の第2の例と同じである。このため、積層デバイスの製造方法の第2の例と共通する製造方法についての詳細な説明は省略する。
上述のように、半導体素子14には、裏面14bにアライメントマーク(図示せず)が設けられており、かつ端子30aおよび端子30bが設けられている。さらに、半導体素子14には表面14aに異方導電性部材20が設けられている。また、半導体素子16でも表面16aに異方導電性部材20が設けられている。
次に、図36に示すように、半導体素子14および半導体素子16が異方導電性部材20を介して接合された第1の半導体ウエハ60を、素子領域毎に、例えば、ダイシングまたはレーザースクライビング等により個片化する。これにより、半導体素子12と半導体素子14と半導体素子16とが異方導電性部材20を介して接合された積層デバイス10を得ることができる。
図37~図38は本発明の実施形態の積層デバイスの製造方法の第6の例を工程順に示す模式図である。
積層デバイスの製造方法の第6の例は、ウエハオンウエハに関するものであり、図9に示す積層デバイス10の製造方法を示す。
積層デバイスの製造方法の第6の例は、積層デバイスの製造方法の第3の例に比して、異方導電性部材20を介して第1の半導体ウエハ60と第2の半導体ウエハ62とを接合する点以外は、積層デバイスの製造方法の第3の例と同じである。このため、積層デバイスの製造方法の第3の例と共通する製造方法についての詳細な説明は省略する。また、異方導電性部材20についても、上述の説明のとおりであるため、その詳細な説明は省略する。
次に、第1の半導体ウエハ60の表面60aと第2の半導体ウエハ62の表面62aを対向させる。そして、第1の半導体ウエハ60のアライメントマークと、第2の半導体ウエハ62のアライメントマークとを用いて、第1の半導体ウエハ60に対して、第2の半導体ウエハ62の位置合せを行う。
次に、第1の半導体ウエハ60の表面60aと第2の半導体ウエハ62の表面62aを対向させて、上述の方法を用いて、図37に示すように第1の半導体ウエハ60と第2の半導体ウエハ62とを異方導電性部材20を介して接合する。この場合、仮接合した後に、本接合をしてもよく、本接合だけでもよい。
なお、個片化については、上述のとおりであるため、詳細な説明は省略する。
また、図38に示すように、第1の半導体ウエハ60と第2の半導体ウエハ62が接合された状態で、第1の半導体ウエハ60および第2の半導体ウエハ62のうち、薄くする必要がある半導体ウエハがあれば、化学的機械的研磨(CMP:Chemical Mechanical Polishing)等により、薄くすることができる。
また、チップオンウエハを用いて積層デバイス10を製造することができるため、半導体チップの良品のみを、半導体ウエハ内の良品部分に接合することで、得率を維持し、製造ロスを低減することができる。
さらには、上述のように樹脂層44は粘着性を備え、仮接合の際に仮接合剤として用いることができ、一括で本接合できる。
次に、異方導電材50の支持体46を取り除き、異方導電性部材20だけを半導体ウエハに接合させる。この場合、異方導電材50に、予め定められた温度に加熱し、剥離層47の剥離剤49の接着力を低下させて、異方導電材50の剥離層47を起点にして支持体46を取り除く。次に、半導体ウエハについて、素子領域毎に個片化し、複数の半導体素子14を得る。
なお、異方導電性部材20が設けられた半導体素子14を例にして説明したが、異方導電性部材20が設けられた半導体素子16も、異方導電性部材20が設けられた第2の半導体ウエハ62についても、異方導電性部材20が設けられた半導体素子14と同様にして、異方導電性部材20を設けることができる。
図39は本発明の実施形態の積層デバイスの第8の例を示す模式図であり、図40は本発明の実施形態の積層デバイスの第9の例を示す模式図であり、図41は本発明の実施形態の積層デバイスの第10の例を示す模式図であり、図42は本発明の実施形態の積層デバイスの第11の例を示す模式図であり、図43は本発明の実施形態の積層デバイスの第12の例を示す模式図である。
また、複数対複数の形態としては、例えば、図40に示すように、1つの半導体素子12に対して、異方導電性部材20を用いて半導体素子14と半導体素子16とが接合され、かつ電気的に接続された形態の積層デバイス64が例示される。半導体素子12は、インターポーザー機能を有するものであってもよい。
また、例えば、インターポーザー機能を有するデバイス上に、論理回路を有する論理チップ、およびメモリーチップ等の複数のデバイスを積層することも可能である。また、この場合、それぞれのデバイスごとに電極サイズが異なっていても接合することができる。
図41に示す積層デバイス65では、電極68の大きさは同じではなく、大きさが異なるものが混在しているが、1つの半導体素子12に対して、異方導電性部材20を用いて半導体素子14と半導体素子16とが接合され、かつ電気的に接続されている。さらに半導体素子14に半導体素子66が異方導電性部材20を用いて接合され、かつ電気的に接続されている。半導体素子14と半導体素子16とに跨って半導体素子67が異方導電性部材20を用いて接合され、かつ電気的に接続されている。
例えば、図43に示す積層デバイス69aのように、1つの半導体素子12に対して、異方導電性部材20を用いて半導体素子14と半導体素子16とが接合され、かつ電気的に接続されている。さらに半導体素子14に半導体素子66と半導体素子67とが異方導電性部材20を用いて接合され、半導体素子16に半導体素子71が異方導電性部材20を用いて接合され、かつ電気的に接続されている。半導体素子12には光導波路61が設けられている。半導体素子16には発光素子75が設けられ、半導体素子14には受光素子76が設けられている。半導体素子16の発光素子75から出力された光Loは、半導体素子12の光導波路61を通過し、半導体素子14の受光素子76に出射光Ldとして出射される。これにより、上述のシリコンフォトニクスに対応することができる。
なお、異方導電性部材20には、光Loおよび出射光Ldの光路に相当する箇所に穴21が形成されている。
3次元積層を実現するためには積層するデバイスにおいて積層方向の電気的な接続を担う配線が形成されていることが必要であり、この積層方向の接続を担う配線はTSV(Through Silicon Via)と呼ばれる。TSVを有するデバイスは、TSVをどの段階で形成するかによりビアファースト、ビアミドル、およびビアラストの3種類に分類される。デバイスのトランジスタを形成する前にTSVを形成するものがビアファーストと呼ばれる。トランジスタの形成後、かつ再配線層の形成前に形成するものがビアミドルと呼ばれる。再配線層形成後に形成するものがビアラストと呼ばれる。いずれの方法によるTSV形成も貫通処理を行なうためにシリコン基板の薄化を必要とする。
ビアファーストまたはビアミドルの代表的な例として、HBM(High Bandwidth Memory)、またはHMC(Hybrid Memory Cube)と呼ばれる積層型のメモリーチップが挙げられる。これらの例では、同一ダイ状にメモリ領域の形成とともにTSV領域を形成し、基材ウエハを薄化し、TSVを形成し、ビアの表面にマイクロバンプと呼ばれる電極を形成し、積層して接合を行っている。
ビアラストの例としては、メタルバンプを有しない半導体チップまたはウエハを絶縁性接着剤または絶縁性酸化物によって接合し、その後にTSVを形成する工程が挙げられる。
しかし、金属充填がめっき核の成長によって形成されたものであるため、充填金属と配線部分との接合は必ずしも担保されていない。これに対し、異方導電性部材を用いてバンプ同士を接続する場合には、異方導電性部材の導通路がバンプとの結合を直接形成するため電気的接続が強化され、信号接続が一層良好となる。この際、半導体チップ表面またはウエハ表面に信号伝送に寄与しない電極を設けておくことで接合部の面積が増加し、せん断応力あたりの耐性を向上させることができる。また、層間での熱伝導が良好となるため、熱が積層体全体に拡散しやすくなる。これらの機構により接続強度と放熱性が一層向上する。
金属拡散接合または酸化膜ダイレクト接合は低圧低温条件での接合性が良好である。一方、接合面に対して高い清浄度として、例えば、Arエッチングによる表面清浄化直後と同等のレベルが要求される。また、平坦性として、例えば、算術平均粗さRaが1nm以下が要求されるため、接合時には厳密な雰囲気制御、および平行度制御が必要である。また、異なる会社、または会社が同一であっても異なる工場で製造された半導体デバイスの製品群は、半導体デバイスの種類または配線ルールが異なることがあり、そのような半導体デバイスの製品群を3次元積層する場合、その中で最も厳しい精度または制御が要求される。
これらの接合方式においては、接合強度が金属拡散接合および酸化膜ダイレクト接合に比べて低い点、積層を繰り返す毎に既に接合した部分が再加熱されてデバイス不良を引き起こす可能性がある点が課題として挙げられる。文献(産総研研究成果報告2013年3月8日:「多機能高密度三次元集積化技術(2)次世代三次元集積化の評価解析技術の研究開発<(2)-B熱・積層接合技術の研究開発>」)には、有機樹脂によって積層時の一時固定を行ない、全層積層後に一括で加熱して接合することで温度履歴の影響を回避する方法が提案されている。信号伝送に寄与しない電極を形成することで放熱性を向上させられるため、熱伝導性の低い有機樹脂層を用いる態様に対して、積層体を適用することは特に有用である。
積層体に用いられる異方導電性部材は、少なくとも1つの表面に樹脂層が形成されていることが好ましく、両面に形成されていることがより好ましい。
また、上述の異方導電性部材の樹脂層44は熱硬化性樹脂を含むことが好ましい。形成された上述の樹脂層は、仮接合層として積層後の位置ずれを抑制する。仮接合は低温かつ短時間で行なうことが可能であるため、デバイスへの悪影響を低減することができる。プロセス中の熱による位置ずれを抑制する観点で、上述の樹脂層の厚さは100nm~1000nmであることが好ましく、異方導電性部材の熱伝導率は厚み方向で20~100W/(m・K)であることが好ましく、異方導電性部材の熱膨張係数(CTE)は5ppm~10ppmであることが好ましい。
剥離可能な接着層としては、接着性が低い接着層であってもよいが、加熱または光照射により接着性が低下する接着層が好ましい。加熱により接着性が低下する接着層の例としては、日東電工社製リバアルファ(登録商標)またはソマール株式会社製ソマタック(登録商標)が挙げられる。光照射により接着性が低下する接着層としては一般的なダイシングテープとして用いられているような材料を使うことができる他、3M社製の光剥離層も例として挙げられる。
異方導電性部材は導電材を含んでいるため、接合を行なうためには接合対象の表面に電極が形成されていればよく、微細円錐金バンプ等の特殊な金属バンプまたは、コネクテックジャパン株式会社、東北マイクロテック社および産総研青柳昌宏研究グループによるモンスターパックコア技術等の特殊な技術を必要としない。特に、接合対象の表面平坦性が低い場合においても接合を可能とするために、異方導電性部材は突起を表面に有することが好ましく、上述のように、突出部分42a、すなわち、突起が導電材からなる突起を含むことがより好ましい。
また、本発明の面積率を有する端子を有する積層体は層間の熱伝導が良好であることから熱が積層体全体に拡散しやすくなるため、放熱性が特に良好である。
異なる半導体チップを積層する態様には、COC(Chip on Chip)法、COW(Chip on Wafer)法、WOW(Wafer on Wafer)法が挙げられる。COC法は基板に固定した半導体チップの上に半導体チップを積層していくという方法であり、異なるサイズの半導体チップの積層が可能である、接合前に良品半導体チップを選別することが可能である等のメリットを有するが、多数の半導体チップを積層する場合は都度アライメントを要するため高コストである。COW法は基板ウエハ上に半導体チップを積層するという方法であり、多数の半導体チップを積層する場合はCOC法と同様に都度アライメントを要するため高コストである。WOW法はウエハ同士を接合するという方法であり、接合時間の短縮が可能である、アライメントが容易等のメリットを有するが、良品半導体チップの選別ができないため多層積層体の得率が低下しやすい。
したがって、積層体の各接合には異方導電性部材を用いることが好ましいが、積層体は従来法による接合を含んでもよい。従来法による接合を含む例として、異方導電性部材による接合を有する積層体が光半導体とASIC(Application Specific Integrated Circuit)との間にハイブリッドボンディングを有する態様、およびメモリーとASICとの間に表面活性化接合を有する態様が挙げられる。従来法による接合は、異なるルールで製造されたデバイス同士の積層が容易になるという利点を有する。
まず、第1の半導体チップ群を検査、個片化し、第1の良品半導体チップ群を選別する。
第1の異方導電性部材を介して第1の基体に第1の良品半導体チップ群を配列し、仮接合を行なう。仮接合は、フリップチップボンダー等の装置により行なうことができる。第1の基体としては、特に限定されるものではないが、トランジスタを有するデバイスまたは、配線層と貫通電極を有する基体が例として挙げられる。
被積層半導体チップ群を検査した後、個片化し、被積層良品半導体チップ群を選別する。被積層半導体チップ群としては、特に限定されるものではないが、貫通電極を有する態様または埋設されたビアを有する半導体チップの裏面を除去する態様が例として挙げられる。裏面の除去方法は、バックグラインド、CMP、およびケミカルエッチング等の方法が挙げられる。特に、横方向の応力の少ないケミカルエッチング等の除去方法が好ましい。
第1の基体と第2の基体との位置合わせを行なった後、第1の基体と第2の基体の間に第2の異方導電性部材を挟み、この第2の異方導電性部材を介して第1の良品半導体チップ群と被積層良品半導体チップ群との仮接合を行なう。次に、被積層良品半導体チップ群から第2の基体を剥して除去する。
第1の良品半導体チップ群、第2の異方導電性部材、および被積層良品半導体チップ群からなる構造を新たな第1の良品半導体チップ群とし、予め定められた階層の構造が形成されるまで第2の異方導電性部材と被積層半導体チップ群の積層を繰り返す。
予め定められた階層の構造が形成された後、一括で加熱および加圧を行なうことで階層間を本接合し、3次元接合構造を得る。
得られた3次元接合構造をコンプレッションボンディング等の手法で封止し、個片化を行なうことで目的とする素子を得る。なお、個片化を行なう前に、薄化、再配線、電極形成等の処理を行なってもよい。
まず、第1の基体の表面に第1の異方導電性部材を設ける。第1の基体としては、MOS(Metal Oxide Semiconductor)が存在する態様であってもよく、MOSが存在しない態様であってもよい。
第1の半導体チップ群を検査し、個片化し、第1の良品半導体チップ群を選別する。
処理により接着性が低下する仮接合層を介して支持体の表面に第2の異方導電性部材を設ける。支持体の材質としては、特に限定されるものではないが、シリコンまたはガラスが好ましい。処理により接着性が低下する仮接合層としては、加熱により接着性が低下する仮接合層または光照射により接着性が低下する仮接合層が好ましい。
第1の基体、第1の異方導電性部材、および第1の良品半導体チップ群からなる構造を新たな第1の基体とし、第2の異方導電性部材を新たな第1の異方導電性部材とし、予め定められた階層の構造が形成されるまで第1の良品半導体チップ群と第2の異方導電性部材の積層を繰り返す。
得られた3次元接合構造をコンプレッションボンディング等の手法で封止し、個片化を行なうことで目的とする積層デバイスを得る。なお、個片化を行なう前に、薄化、再配線および電極形成等の処理を行なってもよい。
上述のように、異方導電性部材を用いることで仮接合と本接合とを分離できるため、はんだリフロー等の高温プロセスを複数回かける必要がなく、デバイス不良発生リスクを低減することができる。また、上述のように、樹脂層を表面に有する異方導電性部材を用いる態様では、プロセス条件による接合部への影響を樹脂層が緩和することができる。また、突起を表面に有する異方導電性部材を用いる態様では、接合対象の表面平坦性が低い場合においても接合が可能となるため、平坦化プロセスを簡略化することができる。
図44~図54は本発明の実施形態の積層デバイスの製造方法の第7の例を工程順に示す模式図である。
図55~図57は本発明の実施形態の積層デバイスの製造方法の第7の例に用いられる積層体の製造方法を工程順に示す模式図である。
図58および図59は本発明の実施形態の積層デバイスの製造方法の第7の例に用いられる積層体の製造方法を工程順に示す模式図である。
積層デバイスの製造方法の第7の例は、3次元積層に関するものであり、積層デバイスの製造方法の第5の例と同様に異方導電性部材を用いるものである。このため、積層デバイスの製造方法の第5の例と共通する製造方法についての詳細な説明は省略する。
また、図45に示すように、複数の半導体素子14が設けられた第2の積層基体80を用意する。第2の積層基体80は、第2の基体82の表面82a上に剥離機能層84と異方導電性部材20とが積層されている。異方導電性部材20上に、複数の半導体素子14が設けられている。異方導電性部材20上には、半導体素子14が設けられていない領域に親疎水性膜85が設けられている。
第2の積層基体80において、半導体素子14の裏面14bは第2の基体82側の面であり、表面14aはその反対側の面である。半導体素子14は、例えば、検査して選別された良品半導体素子が用いられる。
次に、図47に示すように、第2の積層基体80の第2の基体82を除去する。この場合、半導体素子14は半導体ウエハ72の異方導電性部材20と仮接合された状態であり、かつ半導体素子14の表面14aに異方導電性部材20が転載された状態となる。
第2の基体82は、例えば、加熱または光照射により剥離機能層84の接着性を低下させて除去する。
次に、図49に示すように、別の第2の積層基体80の第2の基体82を除去する。第2の基体82の除去方法は、上述のとおりである。
図49に示すように半導体素子14は、半導体ウエハ72の側の半導体素子14の異方導電性部材20と仮接合された状態であり、かつ半導体素子14の表面14aに異方導電性部材20が転載された状態となる。図49は、半導体素子14が2層設けられた構成を示す。このように、第2の積層基体80の仮接合を繰り返すことにより、半導体素子14の積層数を制御することができる。
親疎水性膜89は、例えば、撥水性の材料をマスクを介して塗布し、所望のパターンにして、特定のパターンを得る。撥水性材料としては、アルキルシラン、またはフルオロアルキルシランといった化合物を用いることができる。撥水性材料としては、形状による撥水効果を発現する材料、例えば、イソタクチックポリプロピレン(i-PP)の相分離構造等を用いることができる。
次に、図52に示すように、第3の複合積層体86の第3の基体88を取り除く。第3の基体88の除去方法は、上述の第2の基体82の除去方法と同じである。
次に、仮接合で用いた条件より高圧、かつ高温の条件で一括処理を行なうことにより、半導体素子14と異方導電性部材20と半導体ウエハ72とを本接合し、図53に示す3次元接合構造体74を得る。なお、3次元接合構造体74に対して、薄化、再配線および電極形成等の処理を行なってもよい。
次に、図56に示すように、異方導電性部材20上に特定のパターンで親疎水性膜85を形成する。
親疎水性膜85は、例えば、リソグラフィ法または自己組織化法等の方法でパターンを異方導電性部材20上に形成される。親疎水性膜85のうち、親水パターンを形成する親水性材料の例としては、ポリビニルアルコール等の親水性高分子が挙げられる。
また、上述の親疎水性膜89に用いた材料で、親疎水性膜85を形成することもできる。親疎水性膜85は、例えば、フッ素系化合物を含むレジスト材料を使って、露光現像により特定のパターンを形成することもできる。
半導体素子14を設ける方法としては、例えば、親疎水性膜85が設けられていない領域に活性剤を含む液滴を形成し、液滴上に半導体素子14を載置し、位置決めし、液滴を乾燥させ、半導体素子14と第2の基体82とを硬化性樹脂層を介して接合し、活性剤を洗い流す方法が用いられる。
次に、親疎水性膜89が設けられていない領域に半導体素子14を設ける。半導体素子14を設ける方法としては、例えば、親疎水性膜89が設けられていない領域に活性剤を含む液滴を形成し、液滴上に半導体素子14を載置し、位置決めし、液滴を乾燥させ、半導体素子14と第3の基体88とを硬化性樹脂層を介して接合し、活性剤を洗い流す方法が用いられる。これにより、図50に示す第3の複合積層体86を得る。
このような問題を解決する方法として、再配線層(RDL:Re-Distribution Layer)
を単独で用いる方法が提案されている。種々デバイスをつなぐインターポーザー機能を有する再配線層を異方導電膜に接合し、内包させることにより個々のデバイス設計にこだわることなく低背化、およびTSVフリーが実現できる。
同様な仕組みで有機基板内に複数のデバイスを積層したスタックを設置することも可能となる。
これらのアセンブリの例を図60~図77に示す。なお、もちろん具体的なアセンブリの手法としては、図60~図77に示すものに限定されるものではない。
図60~図72は本発明の実施形態の積層デバイスの製造方法の第8の例を工程順に示す模式図であり、図73~図77は本発明の実施形態の積層デバイスの製造方法の第9の例を工程順に示す模式図である。なお、図60~図77において、図12に示す異方導電材50および図13に示す積層デバイス10と同一構成物には同一符号を付して、その詳細な説明は省略する。
図60に示すように、異方導電性部材20に対向して再配線層110を配置し、図61に示すように異方導電性部材20と再配線層110とを接合し、電気的に接続する。
次に、図62に示すようにウエハ112を再配線層110から分離する。
次に、図64に示すように再配線層110と異方導電性部材20とを接合し、図65に示すように、一方の支持体46を分離する。
次に、図66に示すように、一方の支持体46が分離された異方導電性部材20に対向させて、半導体素子12を配置する。次に、図67に示すように、異方導電性部材20と半導体素子12とを接合し、電気的に接続する。次に、図68に示すように、残りの支持体46を分離する。
次に、図69に示すように半導体素子12が設けられていない側の、残りの支持体46が分離された異方導電性部材20に対向させて、半導体素子14を配置する。
なお、図69では半導体素子14を配置したが、これに限定されるものではなく、図71に示すように、1つの半導体素子12に対して、半導体素子14と半導体素子16を配置してもよい。この場合、図72に示すにように1つの半導体素子12に、複数の半導体素子14、半導体素子16が配置される構成となる。この場合も、TSVを用いることなく、半導体素子12に、半導体素子14と半導体素子16を積層することができる。
この場合、図73に示すように再配線層110が設けられた異方導電材50に対して、再配線層110に対向させて、有機基板120を配置する。有機基板120は、例えば、インターポーザーとして機能するものである。
次に、図74に示すように再配線層110に有機基板120を、例えば、半田を用いて電気的に接続する。この場合、再配線層110を有機基板120に埋め込んでもよい。
次に、図75に示すように支持体46を分離する。次に、図76に示すように半導体素子12を、異方導電性部材20に対向させて配置する。
次に、図77に示すように半導体素子12を異方導電性部材20に接合し、電気的に接続する。これにより、再配線層110と半導体素子12とが積層されたものを得ることができる。
なお、上述では、半導体素子を例にして説明したが、これに限定されるものではなく、半導体素子に代えて半導体ウエハでもよい。
また、半導体素子の構成は、特に限定されるものではなく、上述の例示のものを適宜利用可能である。
〔絶縁性基材〕
絶縁性基材は、無機材料からなり、従来公知の異方導電性フィルム等を構成する絶縁性基材と同程度の電気抵抗率(1014Ω・cm程度)を有するものであれば特に限定されない。
なお、「無機材料からなり」とは、後述する樹脂層を構成する高分子材料と区別するための規定であり、無機材料のみから構成された絶縁性基材に限定する規定ではなく、無機材料を主成分(50質量%以上)とする規定である。
ここで、バルブ金属としては、具体的には、例えば、アルミニウム、タンタル、ニオブ、チタン、ハフニウム、ジルコニウム、亜鉛、タングステン、ビスマス、アンチモン等が挙げられる。これらのうち、寸法安定性がよく、比較的安価であることからアルミニウムの陽極酸化膜(基材)であることが好ましい。
ここで、各導通路の間隔とは、隣接する導通路間の幅wをいい、異方導電性部材の断面を電解放出形走査型電子顕微鏡により20万倍の倍率で観察し、隣接する導通路間の幅を10点で測定した平均値をいう。
複数の導通路は、絶縁性基材の厚み方向に貫通し、互いに電気的に絶縁された状態で設けられた、導電材からなる。
導通路は、絶縁性基材の表面から突出した突出部分を有しており、かつ、各導通路の突出部分の端部が後述する樹脂層に埋設されていてもよい。
導通路を構成する導電材は、電気抵抗率が103Ω・cm以下の材料であれば特に限定されず、その具体例としては、金(Au)、銀(Ag)、銅(Cu)、アルミニウム(Al)、マグネシウム(Mg)、ニッケル(Ni)、インジウムがドープされたスズ酸化物(ITO)等が好適に例示される。
中でも、電気伝導性の観点から、銅、金、アルミニウム、およびニッケルが好ましく、銅および金がより好ましい。
導通路の突出部分は、導通路が絶縁性基材の表面から突出した部分であり、また、突出部分の端部は、樹脂層に埋設している。
導通路の突出部分の高さは、異方導電性部材の断面を電解放出形走査型電子顕微鏡により2万倍の倍率で観察し、導通路の突出部分の高さを10点で測定した平均値をいう。
導通路の突出部分の直径は、異方導電性部材の断面を電解放出形走査型電子顕微鏡により観察し、導通路の突出部分の直径を10点で測定した平均値をいう。
導通路は柱状であり、導通路の直径dは、突出部分の直径と同様、5nm超10μm以下であることが好ましく、20nm~1000nmであることがより好ましく、100nm以下であることがさらに好ましい。
樹脂層は、絶縁性基材の表面に設けられ、上述の導通路を埋設するものである。すなわち、樹脂層は、絶縁性基材の表面、および絶縁性基材から突出した導通路の端部を被覆するものである。
樹脂層は、接続対象に対して接合性を付与するものである。樹脂層は、例えば、50℃~200℃の温度範囲で流動性を示し、200℃以上で硬化するものであることが好ましい。
以下、樹脂層の組成について説明する。樹脂層は、高分子材料を含有するものである。樹脂層は酸化防止材料を含有してもよい。
樹脂層に含まれる高分子材料としては特に限定されないが、半導体チップまたは半導体ウエハと異方導電性部材との隙間を効率よく埋めることができ、半導体チップまたは半導体ウエハとの密着性がより高くなる理由から、熱硬化性樹脂であることが好ましい。
熱硬化性樹脂としては、具体的には、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリエステル樹脂、ポリウレタン樹脂、ビスマレイミド樹脂、メラミン樹脂、イソシアネート系樹脂等が挙げられる。
なかでも、絶縁信頼性がより向上し、耐薬品性に優れる理由から、ポリイミド樹脂および/またはエポキシ樹脂を用いるのが好ましい。
樹脂層に含まれる酸化防止材料としては、具体的には、例えば、1,2,3,4-テトラゾール、5-アミノ-1,2,3,4-テトラゾール、5-メチル-1,2,3,4-テトラゾール、1H-テトラゾール-5-酢酸、1H-テトラゾール-5-コハク酸、1,2,3-トリアゾール、4-アミノ-1,2,3-トリアゾール、4,5-ジアミノ-1,2,3-トリアゾール、4-カルボキシ-1H-1,2,3-トリアゾール、4,5-ジカルボキシ-1H-1,2,3-トリアゾール、1H-1,2,3-トリアゾール-4-酢酸、4-カルボキシ-5-カルボキシメチル-1H-1,2,3-トリアゾール、1,2,4-トリアゾール、3-アミノ-1,2,4-トリアゾール、3,5-ジアミノ-1,2,4-トリアゾール、3-カルボキシ-1,2,4-トリアゾール、3,5-ジカルボキシ-1,2,4-トリアゾール、1,2,4-トリアゾール-3-酢酸、1H-ベンゾトリアゾール、1H-ベンゾトリアゾール-5-カルボン酸、ベンゾフロキサン、2,1,3-ベンゾチアゾール、o-フェニレンジアミン、m-フェニレンジアミン、カテコール、o-アミノフェノール、2-メルカプトベンゾチアゾール、2-メルカプトベンゾイミダゾール、2-メルカプトベンゾオキサゾール、メラミン、およびこれらの誘導体が挙げられる。
これらのうち、ベンゾトリアゾールおよびその誘導体が好ましい。
ベンゾトリアゾール誘導体としては、ベンゾトリアゾールのベンゼン環に、ヒドロキシル基、アルコキシ基(例えば、メトキシ基、エトキシ基等)、アミノ基、ニトロ基、アルキル基(例えば、メチル基、エチル基、ブチル基等)、ハロゲン原子(例えば、フッ素、塩素、臭素、ヨウ素等)等を有する置換ベンゾトリアゾールが挙げられる。また、ナフタレントリアゾール、ナフタレンビストリアゾール、と同様に置換された置換ナフタレントリアゾール、置換ナフタレンビストリアゾール等も挙げることができる。
樹脂層は、樹脂層に含有し得る金属イオン、ハロゲンイオン、ならびに半導体チップおよび半導体ウエハに由来する金属イオンをトラップすることによって絶縁信頼性がより向上する理由から、マイグレーション防止材料を含有しているのが好ましい。
ここで、陽イオン交換体および陰イオン交換体は、それぞれ、例えば、後述する無機イオン交換体および有機イオン交換体の中から適宜選択することができる。
無機イオン交換体としては、例えば、含水酸化ジルコニウムに代表される金属の含水酸化物が挙げられる。
金属の種類としては、例えば、ジルコニウムのほか、鉄、アルミニウム、錫、チタン、アンチモン、マグネシウム、ベリリウム、インジウム、クロム、ビスマス等が知られている。
これらの中でジルコニウム系のものは、陽イオンのCu2+、Al3+について交換能を有している。また、鉄系のものについても、Ag+、Cu2+について交換能を有している。
同様に、錫系、チタン系、アンチモン系のものは、陽イオン交換体である。
一方、ビスマス系のものは、陰イオンのCl-について交換能を有している。
また、ジルコニウム系のものは条件に製造条件によっては陰イオンの交換能を示す。アルミニウム系、錫系のものも同様である。
これら以外の無機イオン交換体としては、リン酸ジルコニウムに代表される多価金属の酸性塩、モリブドリン酸アンモニウムに代表されるヘテロポリ酸塩、不溶性フェロシアン化物等の合成物が知られている。
これらの無機イオン交換体の一部は既に市販されており、例えば、東亜合成株式会社の商品名イグゼ「IXE」における各種のグレードが知られている。
なお、合成品のほか、天然物のゼオライト、またはモンモリロン石のような無機イオン交換体の粉末も使用可能である。
有機イオン交換体には、陽イオン交換体としてスルホン酸基を有する架橋ポリスチレンが挙げられ、そのほかカルボン酸基、ホスホン酸基またはホスフィン酸基を有するものも挙げられる。
また、陰イオン交換体として四級アンモニウム基、四級ホスホニウム基または三級スルホニウム基を有する架橋ポリスチレンが挙げられる。
電子素子の製造工程では加熱するプロセスを含むため、無機イオン交換体が好ましい。
樹脂層は、無機充填剤を含有しているのが好ましい。
無機充填剤としては特に制限はなく、公知のものの中から適宜選択することができ、例えば、カオリン、硫酸バリウム、チタン酸バリウム、酸化ケイ素粉、微粉状酸化ケイ素、気相法シリカ、無定形シリカ、結晶性シリカ、溶融シリカ、球状シリカ、タルク、クレー、炭酸マグネシウム、炭酸カルシウム、酸化アルミニウム、水酸化アルミニウム、マイカ、窒化アルミニウム、酸化ジルコニウム、酸化イットリウム、炭化ケイ素、窒化ケイ素等が挙げられる。
無機充填剤の平均粒子径は、30nm~10μmであることが好ましく、80nm~1μmであることがより好ましい。
ここで、平均粒子径は、レーザー回折散乱式粒子径測定装置(日機装(株)製マイクロトラックMT3300)で測定される、一次粒子径を平均粒子径とする。
樹脂層は、硬化剤を含有していてもよい。
硬化剤を含有する場合、接続対象の半導体チップまたは半導体ウエハの表面形状との接合不良を抑制する観点から、常温で固体の硬化剤を用いず、常温で液体の硬化剤を含有しているのがより好ましい。
ここで、「常温で固体」とは、25℃で固体であることをいい、例えば、融点が25℃より高い温度である物質をいう。
異方導電性部材の導通路を保護する理由から、樹脂層の厚みは、導通路の突出部分の高さより大きく、1μm~5μmであることが好ましい。
透明絶縁体は、上述の〔樹脂層〕に挙げている材料から構成されるもののうち、可視光透過率が80%以上であるもので構成される。このため、各材料に関し、詳細な説明は省略する。
透明絶縁体において、主成分(高分子材料)が上述の〔樹脂層〕と同じである場合、透明絶縁体と樹脂層との間の密着性が良好となるため好ましい。
透明絶縁体は、電極等がない部分に形成するため、上述の〔樹脂層〕の<酸化防止材料>および上述の〔樹脂層〕の<マイグレーション防止材料>を含まないことが好ましい。
透明絶縁体はCTE(線膨張係数)がシリコン等の支持体に近い方が、異方導電材の反りが減るため、上述の〔樹脂層〕の<無機充填剤>を含むことが好ましい。
透明絶縁体において、高分子材料と硬化剤が、上述の〔樹脂層〕と同じである場合、温度および時間等の硬化条件が同じになるため好ましい。
なお、可視光透過率が80%以上とは、光透過率が波長400~800nmの可視光波長域において、80%以上のことをいう。光透過率は、JIS(日本工業規格) K 7375:2008に規定される「プラスチック--全光線透過率および全光線反射率の求め方」を用いて測定されるものである。
異方導電性部材の製造方法は特に限定されないが、例えば、絶縁性基材に設けられた貫通孔に導電性材料を存在させて導通路を形成する導通路形成工程と、導通路形成工程の後に絶縁性基材の表面のみを一部除去し、導通路を突出させるトリミング工程と、トリミング工程の後に絶縁性基材の表面および導通路の突出部分に樹脂層を形成する樹脂層形成工程とを有する製造方法等が挙げられる。
絶縁性基材は、例えば、貫通孔を有するガラス基板(Through Glass Via:TGV)をそのまま用いることができるが、導通路の開口径、および突出部分のアスペクト比を上述の範囲とする観点から、バルブ金属に対して陽極酸化処理を施して形成した基板が好ましい。
陽極酸化処理としては、例えば、絶縁性基材がアルミニウムの陽極酸化皮膜である場合は、アルミニウム基板を陽極酸化する陽極酸化処理、および陽極酸化処理の後に、陽極酸化により生じたマイクロポアによる孔を貫通化する貫通化処理をこの順に施すことにより作製することができる。
絶縁性基材の作製に用いられるアルミニウム基板ならびにアルミニウム基板に施す各処理工程については、特開2008-270158号公報の<0041>~<0121>段落に記載したものと同様のものを採用することができる。
導通路形成工程は、絶縁性基材に設けられた貫通孔に導電性材料を存在させる工程である。
ここで、貫通孔に金属を存在させる方法としては、例えば、特開2008-270158号公報の<0123>~<0126>段落および[図4]に記載された各方法(電解メッキ法または無電解メッキ法)と同様の方法が挙げられる。
また、電解メッキ法または無電解メッキ法においては、金、ニッケル、銅等による電極層を予め設けることが好ましい。この電極層の形成方法としては、例えば、スパッタ等の気相処理、無電解めっき等の液層処理、およびこれらを組合せた処理等が挙げられる。
金属充填工程により、導通路の突出部分が形成される前の異方導電性部材が得られる。
陽極酸化工程は、アルミニウム基板の片面に陽極酸化処理を施すことにより、アルミニウム基板の片面に、厚み方向に存在するマイクロポアとマイクロポアの底部に存在するバリア層とを有する陽極酸化膜を形成する工程である。
陽極酸化処理は、従来公知の方法を用いることができるが、マイクロポア配列の規則性を高くし、異方導電性を担保する観点から、自己規則化法または定電圧処理を用いるのが好ましい。
ここで、陽極酸化処理の自己規則化法または定電圧処理については、特開2008-270158号公報の<0056>~<0108>段落および[図3]に記載された各処理と同様の処理を施すことができる。
バリア層除去工程は、陽極酸化処理工程の後に、陽極酸化膜のバリア層を除去する工程である。バリア層を除去することにより、マイクロポアを介してアルミニウム基板の一部が露出することになる。
バリア層を除去する方法は特に限定されず、例えば、陽極酸化処理工程の陽極酸化処理における電位よりも低い電位でバリア層を電気化学的に溶解する方法(以下、「電解除去処理」ともいう。);エッチングによりバリア層を除去する方法(以下、「エッチング除去処理」ともいう。);これらを組み合わせた方法(特に、電解除去処理を施した後に、残存するバリア層をエッチング除去処理で除去する方法);等が挙げられる。
電解除去処理は、陽極酸化処理工程の陽極酸化処理における電位(電解電位)よりも低い電位で施す電解処理であれば特に限定されない。
電解溶解処理は、例えば、陽極酸化処理工程の終了時に電解電位を降下させることにより、陽極酸化処理と連続して施すことができる。
特に、上述したように電解除去処理と陽極酸化処理とを連続して施す場合は、同様の電解液を用いて処理するのが好ましい。
電解除去処理における電解電位は、陽極酸化処理における電解電位よりも低い電位に、連続的または段階的(ステップ状)に降下させるのが好ましい。
ここで、電解電位を段階的に降下させる際の下げ幅(ステップ幅)は、バリア層の耐電圧の観点から、10V以下であることが好ましく、5V以下であることがより好ましく、2V以下であることがさらに好ましい。
また、電解電位を連続的または段階的に降下させる際の電圧降下速度は、生産性等の観点から、いずれも1V/秒以下が好ましく、0.5V/秒以下がより好ましく、0.2V/秒以下がさらに好ましい。
エッチング除去処理は特に限定されないが、酸水溶液またはアルカリ水溶液を用いて溶解する化学的エッチング処理であってもよく、ドライエッチング処理であってもよい。
化学エッチング処理によるバリア層の除去は、例えば、陽極酸化処理工程後の構造物を酸水溶液またはアルカリ水溶液に浸漬させ、マイクロポアの内部に酸水溶液またはアルカリ水溶液を充填させた後に、陽極酸化膜のマイクロポアの開口部側の表面にpH(水素イオン指数)緩衝液に接触させる方法等であり、バリア層のみを選択的に溶解させることができる。
一方、アルカリ水溶液を用いる場合は、水酸化ナトリウム、水酸化カリウムおよび水酸化リチウムからなる群から選ばれる少なくとも一つのアルカリの水溶液を用いることが好ましい。また、アルカリ水溶液の濃度は0.1質量%~5質量%であることが好ましい。アルカリ水溶液の温度は、10℃~60℃が好ましく、さらに15℃~45℃が好ましく、さらに20℃~35℃であることが好ましい。なお、アルカリ水溶液には、亜鉛および他の金属を含有していてもよい。
具体的には、例えば、50g/L、40℃のリン酸水溶液、0.5g/L、30℃の水酸化ナトリウム水溶液、0.5g/L、30℃の水酸化カリウム水溶液等が好適に用いられる。
なお、pH緩衝液としては、上述した酸水溶液またはアルカリ水溶液に対応した緩衝液を適宜使用することができる。
ドライエッチング処理は、例えば、Cl2/Ar混合ガス等のガス種を用いることが好ましい。
金属充填工程は、バリア層除去工程の後に、電解めっき処理を施して陽極酸化膜におけるマイクロポアの内部に金属を充填する工程であり、例えば、特開2008-270158号公報の<0123>~<0126>段落および[図4]に記載された各方法と同様の方法(電解メッキ法または無電解メッキ法)が挙げられる。
なお、電解メッキ法または無電解メッキ法においては、上述したバリア層除去工程の後にマイクロポアを介して露出するアルミニウム基板を電極として利用することができる。
基板除去工程は、金属充填工程の後にアルミニウム基板を除去し、金属充填微細構造体を得る工程である。
アルミニウム基板を除去する方法としては、例えば、処理液を用いて、金属充填工程においてマイクロポアの内部に充填した金属および絶縁性基材としての陽極酸化膜を溶解せずに、アルミニウム基板のみを溶解させる方法等が挙げられる。
また、処理液の濃度としては、0.01mol/L~10mol/Lが好ましく、0.05mol/L~5mol/Lがより好ましい。
また、処理温度としては、-10℃~80℃が好ましく、0℃~60℃が好ましい。
トリミング工程は、導通路形成工程後の異方導電性部材表面の絶縁性基材のみを一部除去し、導通路を突出させる工程である。
ここで、トリミング処理は、導通路を構成する金属を溶解しない条件であれば特に限定されず、例えば、酸水溶液を用いる場合は、硫酸、リン酸、硝酸、塩酸等の無機酸またはこれらの混合物の水溶液を用いることが好ましい。中でも、クロム酸を含有しない水溶液が安全性に優れる点で好ましい。酸水溶液の濃度は1質量%~10質量%であることが好ましい。酸水溶液の温度は、25℃~60℃であることが好ましい。
一方、アルカリ水溶液を用いる場合は、水酸化ナトリウム、水酸化カリウムおよび水酸化リチウムからなる群から選ばれる少なくとも一つのアルカリの水溶液を用いることが好ましい。アルカリ水溶液の濃度は0.1質量%~5質量%であることが好ましい。アルカリ水溶液の温度は、20℃~50℃であることが好ましい。
具体的には、例えば、50g/L、40℃のリン酸水溶液、0.5g/L、30℃の水酸化ナトリウム水溶液または0.5g/L、30℃の水酸化カリウム水溶液が好適に用いられる。
酸水溶液またはアルカリ水溶液への浸漬時間は、8分~120分であることが好ましく、10分~90分であることがより好ましく、15分~60分であることがさらに好ましい。ここで、浸漬時間は、短時間の浸漬処理(トリミング処理)を繰り返した場合には、各浸漬時間の合計をいう。なお、各浸漬処理の間には、洗浄処理を施してもよい。
ここで、同一平面状に加工する方法としては、例えば、物理的研磨(例えば、遊離砥粒研磨、バックグラインド、サーフェスプレーナー等)、電気化学的研磨、これらを組み合わせた研磨等が挙げられる。
加熱処理は、金属の酸化を抑制する観点から還元性雰囲気で施すことが好ましく、具体的には、酸素濃度が20Pa以下で行うことが好ましく、真空下で行うことがより好ましい。ここで、真空とは、大気よりも気体密度または気圧の低い空間の状態をいう。
また、加熱処理は、矯正の目的で、材料を加圧しながら行うことが好ましい。
樹脂層形成工程は、トリミング工程後に絶縁性基材の表面および導通路の突出部分に樹脂層を形成する工程である。
ここで、樹脂層を形成する方法としては、例えば、上述した酸化防止材料、高分子材料、溶媒(例えば、メチルエチルケトン等)等を含有する樹脂組成物を絶縁性基材の表面および導通路の突出部分に塗布し、乾燥させ、必要に応じて焼成する方法等が挙げられる。
樹脂組成物の塗布方法は特に限定されず、例えば、グラビアコート法、リバースコート法、ダイコート法、ブレードコーター、ロールコーター、エアナイフコーター、スクリーンコーター、バーコーター、カーテンコーター等、従来公知のコーティング方法が使用できる。
また、塗布後の乾燥方法は特に限定されず、例えば、大気下において0℃~100℃の温度で、数秒~数十分間、加熱する処理、減圧下において0℃~80℃の温度で、十数分~数時間、加熱する処理等が挙げられる。
また、乾燥後の焼成方法は、使用する高分子材料により異なるため特に限定されないが、ポリイミド樹脂を用いる場合には、例えば、160℃~240℃の温度で2分間~60分間加熱する処理等が挙げられ、エポキシ樹脂を用いる場合には、例えば、30℃~80℃の温度で2分間~60分間加熱する処理等が挙げられる。
本実施例では、実施例1~実施例7および比較例1~比較例8について接合強度、放熱性および信頼性を評価した。接合強度、放熱性および信頼性の評価結果を下記表1に示す。
接合強度は、万能型ボンドテスターDage-4000(ノードソンアドバンストテクノロジー株式会社製)を用いてシェア強度を測定して評価した。
接合強度は、得られた破壊荷重から半導体素子の面積当たりの接合強度値を求めた。接合強度は、以下に示す評価基準により評価した。
「A」:20MPa≦接合強度
「B」:10MPa≦接合強度<20MPa
「D」:接合強度<10MPa
放熱性の評価では、一方向熱流定常法とレーザーフラッシュ法との両者で測定した接合部分の熱伝導率の平均値を用いた。放熱性は、熱伝導率の平均値を以下に示す評価基準により評価した。
「A」:100W/(m・K)<熱伝導率
「B」:10W/(m・K)<熱伝導率≦100W/(m・K)
「D」:2W/(m・K)<熱伝導率≦10W/(m・K)
「F」:熱伝導率≦2W/(m・K)
1000サイクルの試験後、シェア強度の試験および放熱性の試験を上述の条件で実施した。信頼性は、以下に示す評価基準により評価した。
「A」:シェア強度の試験の評価および放熱性の試験の評価のうち、いずれかも変化なし
「B」:シェア強度の試験の評価および放熱性の試験の評価のうち、いずれか一方の評価が低下
「C」:シェア強度の試験の評価および放熱性の試験の評価の両方の評価が低下
(実施例1)
図78に示すテスト基板90は、シリコン基板の表面に酸化シリコン絶縁層が形成されており、酸化シリコン絶縁層に端子92が、図78に示すように端子92の平面視での端子92を有する面91における面積率45%で形成されたものである。端子92は、銅で構成されたものである。
テスト基板90は、以下の(i)~(iv)のプロセスで作製した。
(i)フォトリソグラフィー法を用いて、シリコン基板の表面に図78に示すように、平面視での端子92を有する面91における面積率が45%となるような端子92のレジストパターンを形成した。
(ii)レジストパターンのレジスト開口部(凹部)にメッキの起点となるシード層を設けた。
(iii)レジスト開口部に金属をメッキした。
(iv)レジストを剥離し、端子がシリコン基板表面に並んだ状態にした。
(v)シリコン基板全面に酸化シリコン絶縁層を化学気相蒸着法(CVD)により形成した。
(vi)CMP研磨により端子の露出および表面平滑化を行った。
実施例1は、図78に示すテスト基板90を2つDBI(Direct Bond Interconnect)を用いて接合した。実施例1は、端子92のうち、電気的に接続されている端子の面積の割合を40%とした。
接合に際しては上述のテスト基板90の接合する側の表面に対してCMPによる研磨を実施して表面を平滑化した。図示はしていないがテスト基板90の周囲に設けたアライメントマークにより、上下のテスト基板90を位置合わせした上で、接合面に圧力200MPaを加圧した状態で、300℃の温度で2時間保持した。
リセス処理はドライエッチングによりフッ素系のガスを用いて酸化シリコン絶縁層のみを除去して端子を突出させるものである。リセス処理のドライエッチング処理時間を変えることにより、リセス量を制御した。
実施例2は、接合形態がSAB(Surface Activated Bond)である点以外は、実施例1と同じとした。
実施例3は、リセス量が80nmであり、接合形態がSABであり、テスト基板90の接合の際、封止樹脂を用いた点以外は、実施例1と同じとした。なお、リセス量は、上述のようにドライエッチングの処理時間を変えて調整した。封止樹脂は後に詳述する。
実施例4は、リセス量が200nmであり、接合形態がSABであり、テスト基板90の接合の際、封止樹脂を用いた点以外は、実施例1と同じとした。なお、リセス量は、上述のようにドライエッチングの処理時間を変えて調整した。
(実施例5)
実施例5は、リセス量が200nmであり、異方導電性部材を介してテスト基板90を接合しており、テスト基板90の接合の際、封止樹脂を用いた点以外は、実施例1と同じとした。なお、リセス量は、上述のようにドライエッチングの処理時間を変えて調整した。
実施例6は、リセス量が200nmであり、異方導電性部材を介してテスト基板90を接合しており、積層数が5層であり、テスト基板90の接合の際、封止樹脂を用いた点以外は、実施例1と同じとした。なお、リセス量は、上述のようにドライエッチングの処理時間を変えて調整した。
(実施例7)
実施例7は、リセス量が800nmであり、異方導電性部材を介してテスト基板90を接合しており、テスト基板90の接合の際、封止樹脂を用いた点以外は、実施例1と同じとした。なお、リセス量は、上述のようにドライエッチングの処理時間を変えて調整した。
比較例1は、図79に示すテスト基板100を2つ、半田を用いて接合した。図79に示すテスト基板100は、図78に示すテスト基板90に比して、端子92の平面視での端子92を有する面101における面積率が23%である点以外は同じ構成とした。なお、比較例1では、リセス量を5μmとした。なお、リセス量は、上述のようにドライエッチングの処理時間を変えて調整した。比較例1は、端子92のうち、電気的に接続されている端子の面積の割合を80%とした。
テスト基板100は、上述のテスト基板90の作製プロセス(i)において、端子92の平面視での端子92を有する面101における面積率を23%とした以外は、上述のテスト基板90の作製プロセス(i)~(iv)と同様にして作製した。
(比較例2)
比較例2は、テスト基板100の接合の際、封止樹脂を用いた点以外は、比較例1と同じとした。
比較例3は、テスト基板100を用いた点、および上述の端子の面積の割合を80%とした点以外は、実施例2と同じとした。
(比較例4)
比較例4は、テスト基板100を用いた点、および上述の端子の面積の割合を80%とした点以外は、実施例1と同じとした。
(比較例5)
比較例5は、テスト基板100を用いた点、および上述の端子の面積の割合を80%とした点以外は、実施例5と同じとした。
(比較例6)
比較例6は、端子92の平面視での端子92を有する面101における面積率が35%のテスト基板を用いた点、および上述の端子の面積の割合を52%とした点以外は、実施例5と同じとした。
上述の端子92の面積率が35%のテスト基板は、上述のテスト基板90の作製プロセス(i)において、上述の端子92の面積率を35%とした以外は、上述のテスト基板90の作製プロセス(i)~(iv)と同様にして作製した。
(比較例7)
比較例7は、端子92の平面視での端子92を有する面101における面積率が45%のテスト基板を用いた点、および上述の端子92の面積の割合を52%とした点以外は、実施例5と同じとした。
上述の端子92の面積率が45%のテスト基板は、上述のテスト基板90の作製プロセス(i)において、上述の端子92の面積率を45%とした以外は、上述のテスト基板90の作製プロセス(i)~(iv)と同様にして作製した。
(比較例8)
比較例8は、テスト基板100を用いた点以外は、実施例5と同じとした。
[異方導電性部材]
<アルミニウム基板の作製>
Si:0.06質量%、Fe:0.30質量%、Cu:0.005質量%、Mn:0.001質量%、Mg:0.001質量%、Zn:0.001質量%、Ti:0.03質量%を含有し、残部はAlと不可避不純物のアルミニウム合金を用いて溶湯を調製し、溶湯処理およびろ過を行った上で、厚さ500mm、幅1200mmの鋳塊をDC鋳造法で作製した。
次いで、表面を平均10mmの厚さで面削機により削り取った後、550℃で、約5時間均熱保持し、温度400℃に下がったところで、熱間圧延機を用いて厚さ2.7mmの圧延板とした。
さらに、連続焼鈍機を用いて熱処理を500℃で行った後、冷間圧延で、厚さ1.0mmに仕上げ、JIS 1050材のアルミニウム基板を得た。
アルミニウム基板を、直径200mm(8インチ)のウエハ状に形成した後、以下に示す各処理を施した。
上述のアルミニウム基板に対して、以下組成の電解研磨液を用いて、電圧25V、液温度65℃、液流速3.0m/分の条件で電解研磨処理を施した。
陰極はカーボン電極とし、電源は、GP0110-30R(株式会社高砂製作所社製)を用いた。また、電解液の流速は渦式フローモニターFLM22-10PCW(アズワン株式会社製)を用いて計測した。
(電解研磨液組成)
・85質量%リン酸(和光純薬社製試薬) 660mL
・純水 160mL
・硫酸 150mL
・エチレングリコール 30mL
次いで、電解研磨処理後のアルミニウム基板に、特開2007-204802号公報に記載の手順にしたがって自己規則化法による陽極酸化処理を施した。
電解研磨処理後のアルミニウム基板に、0.50mol/Lシュウ酸の電解液で、電圧40V、液温度16℃、液流速3.0m/分の条件で、5時間のプレ陽極酸化処理を施した。
その後、プレ陽極酸化処理後のアルミニウム基板を、0.2mol/L無水クロム酸、0.6mol/Lリン酸の混合水溶液(液温:50℃)に12時間浸漬させる脱膜処理を施した。
その後、0.50mol/Lシュウ酸の電解液で、電圧40V、液温度16℃、液流速3.0m/分の条件で、3時間45分の再陽極酸化処理を施し、膜厚30μmの陽極酸化膜を得た。
なお、プレ陽極酸化処理および再陽極酸化処理は、いずれも陰極はステンレス電極とし、電源はGP0110-30R(株式会社高砂製作所製)を用いた。また、冷却装置にはNeoCool BD36(ヤマト科学株式会社製)、かくはん加温装置にはペアスターラー PS-100(EYELA東京理化器械株式会社製)を用いた。さらに、電解液の流速は渦式フローモニターFLM22-10PCW(アズワン株式会社製)を用いて計測した。
次いで、上述の陽極酸化処理と同様の処理液および処理条件で、電圧を40Vから0Vまで連続的に電圧降下速度0.2V/secで降下させながら電解処理(電解除去処理)を施した。
その後、5質量%リン酸に30℃、30分間浸漬させるエッチング処理(エッチング除去処理)を施し、陽極酸化膜のマイクロポアの底部にあるバリア層を除去し、マイクロポアを介してアルミニウムを露出させた。
また、バリア層除去工程後の陽極酸化膜の平均厚みは80μmであった。なお、平均厚みは、陽極酸化膜を厚さ方向に対してFIB(Focused Ion Beam)で切削加工し、その断面をFE-SEMにより表面写真(倍率50000倍)を撮影し、10点測定した平均値として算出した。
また、陽極酸化膜に存在するマイクロポアの密度は、約1億個/mm2であった。なお、マイクロポアの密度は、特開2008-270158号公報の<0168>および<0169>段落に記載された方法で測定し、算出した。
また、陽極酸化膜に存在するマイクロポアの規則化度は、92%であった。なお、規則化度は、FE-SEMにより表面写真(倍率20000倍)を撮影し、特開2008-270158号公報の<0024>~<0027>段落に記載された方法で測定し、算出した。
次いで、アルミニウム基板を陰極にし、白金を正極にして電解めっき処理を施した。
具体的には、以下に示す組成の銅めっき液を使用し、定電流電解を施すことにより、マイクロポアの内部に銅が充填された金属充填微細構造体を作製した。
ここで、定電流電解は、株式会社山本鍍金試験器社製のめっき装置を用い、北斗電工株式会社製の電源(HZ-3000)を用い、めっき液中でサイクリックボルタンメトリを行って析出電位を確認した後に、以下に示す条件で処理を施した。
(銅めっき液組成および条件)
・硫酸銅 100g/L
・硫酸 50g/L
・塩酸 15g/L
・温度 25℃
・電流密度 10A/dm2
また、マイクロポアに金属を充填した後の陽極酸化膜を厚さ方向に対してFIBで切削加工し、その断面をFE-SEMにより表面写真(倍率50000倍)を撮影し、マイクロポアの内部を確認したところ、封孔されたマイクロポアにおいては、その内部が金属で完全に充填されていることが分かった。
次いで、20質量%塩化水銀水溶液(昇汞)に20℃、3時間浸漬させることによりアルミニウム基板を溶解して除去することにより、金属充填微細構造体を作製した。
基板除去工程後の金属充填微細構造体を、水酸化ナトリウム水溶液(濃度:5質量%、液温度:20℃)に浸漬させ、突出部分の高さが500nmとなるように浸漬時間を調整してアルミニウムの陽極酸化膜の表面を選択的に溶解し、次いで、水洗し、乾燥して、導通路である銅の円柱を突出させた構造体を作製した。
<粘着層形成工程>
トリミング工程後の構造体に、以下に示す方法で粘着層を形成し異方導電性部材を作製した。
ガンマブチロラクトンを溶媒としたポリアミド酸エステル溶液(ジメチルスルホキシド、トリアルコキシアミドカルボキシシラン、オキシム誘導体を含む)の市販品として、LTC9320(富士フイルムエレクトロニクスマテリアルズ株式会社製)を用いた。
この溶液を導通路が突出している絶縁性基材の表面に塗布し、乾燥させて成膜した後に、窒素置換した反応炉中(酸素濃度10ppm以下)で200℃3時間イミド化反応を進行させることにより、ポリイミド樹脂層からなる粘着層を、500nmの厚みに形成した。なお、粘着層の厚みは溶媒(メチルエチルケトン)を追添することで調整した。なお、樹脂層を除く金属充填微細構造体の平均厚みは30μmであった。
<封止樹脂>
以下に示す成分を以下に示す割合でメチルエチルケトンに溶解して、まず、固形分濃度が60.6重量%となる樹脂層塗布液を作製した。封止樹脂の形成時には、樹脂層塗布液を薄めて用いた。
樹脂層塗布液を、粘着層の表面に塗布し、乾燥させて成膜し、封止樹脂を形成した。
なお、封止樹脂の厚みは、1μmとなるように下記処方の塗布液に更に溶媒(メチルエチルケトン)を追添することで調整した。
また、塗布後の乾燥は、400mmHg(53.3kPa)の減圧下で温度を50℃に設定して行った。
<塗布液組成>
・エラストマー:アクリル酸ブチル-アクリロニトリル共重合体を主成分とするアクリル酸エステル系ポリマー(商品名:SG-28GM、長瀬ケムテックス株式会社製) 5質量部
・エポキシ樹脂1:jER(登録商標)828(三菱化学株式会社製) 33質量部
・エポキシ樹脂2:jER(登録商標)1004(三菱化学株式会社製) 11質量部
・フェノール樹脂:ミレックスXLC-4L(三井化学株式会社製) 44質量部
・有機酸:o-アニス酸(オルトアニス酸、東京化成工業株式会社製) 0.5質量部
・酸化防止材料:下記参照
・マイグレーション防止材料:下記参照
・無機充填剤:下記参照
・硬化剤:下記参照
酸化防止材料は、2-メルカプトベンゾチアゾールを0.01質量%配合した。
(マイグレーション防止材料)
マイグレーション防止材料は、東亜合成株式会社、商品名イグゼ「IXE―100」(メジアン径1μm、陽イオン交換、耐熱温度550℃)を2.5質量%配合した。
(無機充填剤)
無機充填剤は、窒化アルミニウムナノ粒子、平均粒子径100nm、シグマアルドリッチ社製を55質量%配合した。
(硬化剤)
硬化剤は、1-シアノエチル-2-エチル-4-メチルイミダゾール(2E4MZ-CN、四国化成工業株式会社製)を0.5質量%配合した。
12 半導体素子
14 半導体素子
14a 表面
14b 裏面
15、17、19、57 積層体
16 半導体素子
16a 表面
18 インターポーザー
20 異方導電性部材
30 端子
30a 端子
30b 端子
30c 端面
31、91、101 面
32 半導体層
32a 表面
34 再配線層
34a 表面
36 パッシベーション層
36a 表面
37 配線
38 パッド
39 樹脂層
40 絶縁性基材
40a 表面
42 導通路
42a 突出部分
42b 突出部分
44 樹脂層
46 支持体
47 剥離層
48 支持層
49 剥離剤
50 異方導電材
52 半導体素子
54 センサチップ
56 レンズ
60 第1の半導体ウエハ
60a 表面
61 光導波路
62 第2の半導体ウエハ
62a 表面
62b 裏面
63、64、65、69、69a 積層デバイス
66、67、71 半導体素子
68 電極
70 第1の積層基体
72 半導体ウエハ
72a 表面
74 3次元接合構造体
75 発光素子
76 受光素子
80 第2の積層基体
82 第2の基体
82a、88a 表面
84 剥離機能層
85、89 親疎水性膜
86 第3の複合積層体
88 第3の基体
89 親疎水性膜
90 テスト基板
92 端子
100 テスト基板
110 再配線層
112 ウエハ
120 有機基板
Ds 積層方向
Ld 出射光
Lo 光
h 厚み
x 方向
Z 厚み方向
δ リセス量
Claims (13)
- 複数の半導体が電気的に接続された積層体を含む積層デバイスであって、
前記半導体は、複数の端子が設けられた面を有し、
前記複数の端子は、前記半導体同士を接合しかつ電気的に接続する端子と、前記半導体同士を接合しかつ電気的に接続しない端子とを含み、
前記半導体の前記面における、前記複数の端子の面積率が40%以上であり、
前記複数の端子のうち、前記半導体同士を接合しかつ電気的に接続する端子の面積率が50%未満である積層デバイス。 - 前記半導体は前記面に絶縁層を有し、前記半導体の前記面から前記端子の表面までの高さは、前記半導体の前記面から前記絶縁層の表面までの高さに対して200nm以上1μm以下高い請求項1に記載の積層デバイス。
- 前記複数の端子同士が直接接合されている請求項1または2に記載の積層デバイス。
- 前記複数の端子は、積層方向に導通する導通路を有する異方導電性部材を介して接合されており、
前記導通路は、直径が100nm以下である請求項1または2に記載の積層デバイス。 - 前記異方導電性部材は、絶縁性基材と、前記絶縁性基材の厚み方向に貫通し、互いに電気的に絶縁された状態で設けられた、複数の前記導通路とを有する請求項4に記載の積層デバイス。
- インターポーザーを有する請求項1~5のいずれか1項に記載の積層デバイス。
- 複数の半導体が電気的に接続された積層体であって、
前記半導体は、複数の端子が設けられた面を有し、
前記複数の端子は、前記半導体同士を接合しかつ電気的に接続する端子と、前記半導体同士を接合しかつ電気的に接続しない端子とを含み、
前記半導体の前記面における、前記複数の端子の面積率が40%以上であり、
前記複数の端子のうち、前記半導体同士を接合しかつ電気的に接続する端子の面積率が50%未満である積層体。 - 前記半導体は前記面に絶縁層を有し、前記半導体の前記面から前記端子の表面の高さは、前記半導体の前記面から前記絶縁層の表面の高さに対して200nm以上1μm以下高い請求項7に記載の積層体。
- 前記複数の端子同士が直接接合されている請求項7または8に記載の積層体。
- 前記複数の端子は、積層方向に導通する導通路を有する異方導電性部材を介して接合されており、
前記導通路は、直径が100nm以下である請求項7または8に記載の積層体。 - 前記異方導電性部材は、絶縁性基材と、前記絶縁性基材の厚み方向に貫通し、互いに電気的に絶縁された状態で設けられた、複数の前記導通路とを有する請求項10に記載の積層体。
- インターポーザーを有する請求項7~11のいずれか1項に記載の積層体。
- 請求項1~6のいずれか1項に記載の積層デバイスの製造方法であって、
各半導体を仮接合し、前記複数の半導体のうち、全て半導体を一括して接合する積層デバイスの製造方法。
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