WO2020196225A1 - チップ転写板ならびに半導体チップ積層方法および半導体装置の製造方法 - Google Patents

チップ転写板ならびに半導体チップ積層方法および半導体装置の製造方法 Download PDF

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WO2020196225A1
WO2020196225A1 PCT/JP2020/012204 JP2020012204W WO2020196225A1 WO 2020196225 A1 WO2020196225 A1 WO 2020196225A1 JP 2020012204 W JP2020012204 W JP 2020012204W WO 2020196225 A1 WO2020196225 A1 WO 2020196225A1
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chip
semiconductor
transfer plate
semiconductor chip
adhesive layer
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PCT/JP2020/012204
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English (en)
French (fr)
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靖典 橋本
昇 朝日
新井　義之
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東レエンジニアリング株式会社
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Definitions

  • the present invention relates to a chip transfer plate for transferring a large number of semiconductor chips, a method for laminating semiconductor chips, and a method for manufacturing a semiconductor device.
  • Patent Document 1 describes a configuration in which a plurality of semiconductor chips are laminated in a temporarily crimped state and then collectively subjected to main crimping to reduce the number of times the semiconductor chips are exposed to high temperatures. There is. Further, when laminating a plurality of semiconductor chips in a temporarily crimped state, Patent Document 1 shows an example in which a bonding tool temporarily crimps and laminates each semiconductor chip one by one.
  • main crimping As a chip laminate, the number of semiconductor chips that can be processed by one main crimping is increasing, and the main crimping time per semiconductor chip is shortened. In recent years, as the number of layers has increased, it has become possible to perform main crimping of a plurality of chip laminates at once, and the number of semiconductor chips processed per unit time in the main crimping process has dramatically increased. ..
  • the temporary crimping process various measures are taken to shorten the tact time until the bonding tool picks up the semiconductor chip and temporarily crimps it.
  • the improvement in the temporary crimping process is not sufficient for the increase in the number of semiconductor chips processed per unit time in the main crimping process, and the number of temporary crimping devices for one main crimping device is increasing. Is.
  • Patent Document 2 discloses a method of forming a large number of chip laminates by laminating semiconductor wafers in a temporarily fixed state and then dicing.
  • the lamination since the lamination is performed at the semiconductor wafer level, a chip laminate can be obtained with extremely high productivity. Therefore, it is an extremely effective method if the defect rate in the semiconductor wafer is zero.
  • the defective chip Since it is possible to grasp the defective portion at the semiconductor wafer level, it is possible to know which layer of a large number of chip laminates is the defective chip, and since it is in a temporarily fixed state, the defective chip It is possible to repair a good chip. However, the productivity is lowered by performing such a repair work. Further, if the chip laminate containing the defective chips is discarded, many good chips are also discarded, and the product yield is greatly reduced.
  • the present invention has been made in view of the above problems, and provides a chip transfer plate and a semiconductor chip lamination method suitable for obtaining a chip laminate in which a plurality of semiconductor chips are laminated in a temporarily fixed state, and productivity is achieved. It provides a method for manufacturing a semiconductor device that achieves both a yield and a yield.
  • the invention according to claim 1 is a support substrate, an adhesive layer provided on one side of the support substrate, and a surface held by the adhesive layer and held by the adhesive layer. It is a chip transfer plate in which a large number of semiconductor chips having bump electrodes on opposite sides and an uncured thermosetting adhesive layer are provided on the bump electrode side of each of the semiconductor chips.
  • the invention according to claim 2 is the chip transfer plate according to claim 1.
  • a semiconductor wafer in which bump electrodes were arranged on a surface was fixed to a support substrate via an adhesive layer, and an uncured thermocurable adhesive film was attached to the surface of the semiconductor wafer on which the bump electrodes were formed. Later, it is a chip transfer plate formed by dicing the semiconductor wafer on which the thermosetting adhesive film is laminated and individualizing it into a large number of semiconductor chips.
  • the invention according to claim 3 is the chip transfer plate according to claim 1 or 2.
  • Chip transfer in which the adhesive layer has photoremovability in which the adhesive strength is reduced by light of a specific wavelength and the semiconductor chip is peeled off, and the support substrate has transparency to light of the specific wavelength. It is a board.
  • the invention according to claim 4 is the chip transfer plate according to claim 3.
  • the adhesive layer is a chip transfer plate having a property of generating gas by light having a specific wavelength and forming bubbles at an interface with a semiconductor chip.
  • the invention according to claim 5 is the chip transfer plate according to any one of claims 1 to 4.
  • the invention according to claim 6 uses the chip transfer plate according to any one of claims 1 to 5. All the semiconductor chips of the chip transfer plate are transferred and temporarily fixed on the temporary mounting plate, and the semiconductor chips are sequentially aligned and transferred onto the temporarily fixed semiconductor chips by using the chip transfer plate.
  • This is a semiconductor chip laminating method in which a large number of temporarily fixed chip laminates are formed on the temporary mounting plate by laminating in a fixed state.
  • the invention according to claim 7 is the semiconductor chip lamination method according to claim 6.
  • the semiconductor chip of the chip transfer plate is transferred onto the temporarily placed plate or the temporarily fixed semiconductor chip and temporarily fixed, the transfer is started from the semiconductor chip arranged on the outer peripheral portion of the chip transfer plate and sequentially inside.
  • This is a semiconductor chip stacking method that promotes transfer toward.
  • the invention according to claim 8 is the semiconductor chip lamination method according to claim 6 or 7. If there is a defective product in the semiconductor chip of the chip transfer plate, only the defective product is peeled off from the chip transfer plate, and then the chip is placed on a temporary mounting plate or a semiconductor chip temporarily fixed on the temporary mounting plate.
  • This is a semiconductor chip lamination method in which a semiconductor chip is transferred by a transfer plate, and a separately prepared non-defective semiconductor chip is placed at a position where the semiconductor chip is not transferred because the defective product is peeled off.
  • the temporarily fixed chip laminate obtained by the semiconductor chip lamination method according to any one of claims 6 to 8 is arranged on a wiring board.
  • This is a method for manufacturing a semiconductor device, which comprises a step of thermocompression bonding the chip laminate and mounting the chip laminate on the wiring board.
  • the present invention provides a chip transfer plate and a semiconductor chip lamination method suitable for obtaining a chip laminate in which a plurality of semiconductor chips are laminated in a temporarily fixed state, and manufactures a semiconductor device that achieves both productivity and yield. The method is realized.
  • FIG. 1 A state in which a semiconductor wafer used for forming a chip transfer plate according to an embodiment of the present invention is attached to a support substrate is shown, and is (a) a top view, (b) a cross-sectional view, and (c) an enlarged view of a cross section. ..
  • thermosetting adhesive film is bonded on a semiconductor wafer
  • top view (b) cross-sectional view, and (c) cross-sectional view.
  • top view (b) cross section, and (c) cross section.
  • the state of transferring the semiconducting chip onto the temporary mounting plate by using the chip transfer plate according to the embodiment of the present invention will be described.
  • B The state in which the semiconductor chip of the chip transfer plate is brought into close contact with the temporary plate to perform transfer, and (c) the state in which the semiconductor chip is transferred to the temporary plate are shown.
  • the state in which the semiconducting chips are laminated on the temporary mounting plate by using the chip transfer plate according to the embodiment of the present invention will be described.
  • A The semiconductor chip and the chip transfer plate transferred on the temporary mounting plate.
  • the state in which the semiconductor chips are aligned and opposed to each other is shown, (b) the state in which the semiconductor chip of the chip transfer plate is brought into close contact with the transferred semiconductor chip on the temporary plate to perform transfer, and (c) the semiconductor chip is shown.
  • a method for peeling a semiconductor chip from a chip transfer plate according to an embodiment of the present invention will be described, and (a) an example of peeling by light irradiation and (b) an example of peeling by heating will be shown.
  • the correspondence when the semiconductor chip included in the chip transfer plate according to the embodiment of the present invention contains a defective product will be described, and (a) an example of a chip transfer plate having a defective (NG) semiconductor chip will be described.
  • b) shows a state in which defective chips are peeled off from the chip transfer plate and removed
  • (c) shows a state in which the chip transfer plate from which defective chips have been removed is placed on a temporary mounting plate, and (d) the same transfer plate is used.
  • (B) It is a figure which shows the state which the chip laminated body holding means picked up the chip laminated body in the temporarily fixed state. The state in which the chip laminate is arranged on the wiring board is described.
  • (A) The state in which the chip laminate picked up from the temporary mounting plate is arranged so that the semiconductor chip in the lowermost layer and the electrode of the wiring board are aligned with each other is shown.
  • (B) shows a state in which the chip laminate is temporarily crimped to the wiring board
  • (c) is a diagram showing a state in which a plurality of chip laminates are temporarily crimped to the surface of the wiring board.
  • step of transferring all the semiconductor chips of the chip transfer plate of the present invention to the temporary mounting plate (a) showing a state in which all the semiconductor chips are simultaneously irradiated with light, and (b) a chip transfer plate. It is a figure which shows the state which all the semiconductor chips were peeled off and transferred.
  • step of transferring all the semiconductor chips of the chip transfer plate of the present invention to the temporary mounting plate will be described, wherein (a) a state in which the semiconductor chips are individually irradiated with light, and (b) individual semiconductor chips It is a figure which shows the difficulty of peeling after irradiating with light.
  • FIG. 1 is a cross-sectional view showing the configuration of the chip transfer plate 1 according to the embodiment of the present invention.
  • FIG. 2 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the chip transfer plate 1 is held in a state in which a large number of semiconductor chips C are arranged on the surface of the support substrate 10 via an adhesive layer 11.
  • the semiconductor chip C is provided with a bump electrode B formed on the side opposite to the adhesive layer 11, and further provided with a thermosetting adhesive layer R covering the bump electrode B.
  • adheresive layer and “adhesive layer” are used in the present specification, in principle, they are used for fixing the “adhesive layer” in a finally connected state. Therefore, the “adhesive layer” is used for the one that is finally peeled off.
  • FIG. 3 is a schematic flow showing a step of forming the chip transfer plate 1 (PT step in FIG. 2), and FIGS. 4 to 6 explain each step of the schematic flow.
  • FIG. 4A and 4B explain step ST0 in FIG. 3, FIG. 4A is a top view, FIG. 4B is a cross-sectional view, and FIG. 4C is a partially enlarged view of a cross section.
  • the semiconductor wafer W has a large number of semiconductor circuits formed in-plane by a so-called semiconductor wafer processing step, and bump electrodes B are formed at predetermined positions in each semiconductor circuit.
  • the semiconductor wafer W has a diameter of several tens of centimeters and a thickness of 50 ⁇ m, which is very thin and difficult to handle. Therefore, the semiconductor wafer W is handled in a state of being fixed to the support substrate 10 via the adhesive layer 11.
  • the support substrate 10 is preferably made of a material having excellent flatness, and as a specific material, glass or silicon is preferable. Further, it is preferable that the adhesive layer 11 is cured by being irradiated with light having a predetermined wavelength (adhesive strength is reduced) and exhibits peelability. In particular, a gas generated by irradiation with light of a specific wavelength and having improved peelability due to bubbles generated at the interface has been commercialized (for example, SELFA (registered trademark) of Sekisui Chemical Co., Ltd.). It is more preferable to use a pressure-sensitive adhesive layer 11 having such characteristics.
  • the height of the bump electrode B is 15 to 20 ⁇ m.
  • FIG. 5A and 5B explain step ST1 in FIG. 3, FIG. 5A is a top view, FIG. 5B is a cross-sectional view, and FIG. 5C is a partially enlarged view of a cross section.
  • FIG. 5 shows a state in which the thermosetting adhesive layer R is provided on the bump B forming surface in the state of FIG.
  • NCF Non Conducive Film
  • NCF Non Conducive Film
  • select one that also covers the tip of the bump electrode B select one that also covers the tip of the bump electrode B. Specifically, it is about 20 ⁇ m.
  • FIG. 6A and 6B explain step ST2 in FIG. 3, FIG. 6A is a top view, FIG. 6B is a cross-sectional view, and FIG. 6C is a partially enlarged view of a cross section.
  • FIG. 6 shows a state in which the semiconductor wafer W in a state where the thermosetting adhesive film is attached to the bump electrode B forming surface is diced, and the chip transfer plate 1 whose configuration is shown in FIG. 1 is formed.
  • the dicing is performed up to the thermosetting adhesive film and the semiconductor wafer W by blade dicing or the like. Therefore, a large number of semiconductor chips C separated by dicing at a predetermined pitch are supported by the support substrate 10, and the thermosetting adhesive film is provided on the bump electrode B side for each semiconductor chip C. ..
  • the operation of a large number of semiconductor circuits formed in the semiconductor wafer W plane can be checked to identify the defective portion. Therefore, it is possible to take over the information as to which of the large number of semiconductor chips C that have been separated as shown in FIG. 6 is a defective product (defective chip) to the subsequent process.
  • PL step shown in FIG. 2 a step (PL step shown in FIG. 2) of obtaining a chip laminate LC in which semiconductor chips C are laminated in a temporarily fixed state using the chip transfer plate 1 will be described.
  • the PL process shown in FIG. 2 is divided into steps as shown in FIG. 7, and each step will be described with reference to FIGS. 8 to 13.
  • FIGS. 8 to 11 are diagrams illustrating a case where the chip transfer plate 1 has no defective chip in step SL3 of FIG. 7 and the process proceeds from step SL3 to step SL41.
  • FIG. 8A shows a state in which the chip transfer 1 is prepared so as to face the temporary placement plate 2, and the state of step SL41 in FIG. 2 is shown.
  • the temporary plate 2 is arranged on a stage or the like in step SL1, and an adhesive layer 21 having photopeelability is provided on the surface of the temporary substrate 20. It is possible to use without the adhesive layer 21, but it is preferable to have the adhesive layer 21, and it is more preferable to use one having a property that the bubbles generated by irradiation with light of a specific wavelength enhance the peelability, as in the adhesive layer 11. ..
  • the temporary mounting plate 2 has a surface area sufficient to transfer all the semiconductor chips C of the chip transfer plate 1, and it is desirable that the temporary mounting substrate 20 has excellent flatness. Further, the surface of the stage on which the temporary plate 1 is arranged also needs to have excellent flatness.
  • step SL1 At the stage where the temporary plate 2 is arranged in step SL1, nothing is placed on the temporary plate 2, and the semiconductor chip C of the first layer is transferred, so that the number of stacked process chips n is 1. ..
  • step SL2 the chip transfer plate 1 is prepared, and if it is found from the inspection information in the previous process that there are no defective chips in the chip transfer plate 1 in step SL3, the semiconductor chip C of the chip transfer plate 1 is temporarily placed in step SL41. It will be transferred to 2.
  • the semiconductor chip C side of the chip transfer plate 1 faces the temporary placement plate 2 (the adhesive layer 21 side if there is an adhesive layer 21), and parallel adjustment and alignment are performed.
  • the temporary placement plate 2 the adhesive layer 21 side if there is an adhesive layer 21
  • parallel adjustment and alignment are performed.
  • the chip transfer plate 1 is brought closer to the temporary plate 2 until the thermosetting adhesive layer R of the chip transfer plate 1 is in close contact with the temporary plate 2 (FIG. 8 (b)).
  • the adhesive layer 11 of the chip transfer plate 1 is cured so as to exhibit peelability, and when the support substrate 10 of the chip transfer plate 1 is separated from the temporary placement plate 2, it is uncured as shown in FIG. 8 (c).
  • the semiconductor chip C is transferred to the temporary placement plate 2 and temporarily fixed.
  • the adhesive layer 11 when the adhesive layer 11 is photocurable, it may be irradiated with light having a wavelength to be photocured as shown in FIG. 11A.
  • the thermosetting adhesive layer R is cured at a temperature at which curing does not start. You need to choose a material like this.
  • step SL41 is completed, and the determination of step SL5 is performed.
  • step SL5 it is determined whether or not the number of chip stacks n to be laminated as the chip laminate LC has reached the number of chip stacks n to be laminated.
  • the number of stacking process chips n is 1, so if the number of stacking chips N to be laminated is 2 or more, the number n of stacking process chips is set to 2 and the process proceeds to step SL2.
  • FIG. 9A shows a state in which the semiconductor chip C of the newly prepared chip transfer plate 1 is opposed to the semiconductor chip C transferred to the temporary mounting plate 2 to perform parallel adjustment and alignment.
  • the semiconductor chips C of the chip transfer plate 1 are arranged on the support substrate 10 at a predetermined pitch, the semiconductor chips C of the newly prepared chip transfer plate 1 and the semiconductor chips transferred to the temporary placement plate 2 are transferred.
  • the pitch and arrangement are the same as C. Therefore, instead of aligning each semiconductor chip C, the vertical positions of a large number of semiconductor chips C are aligned by aligning the positions of the chip transfer plates 1.
  • alignment marks provided on the chip transfer plate 1 and the temporary placement plate 2 are provided respectively, and an image recognition means such as a two-field camera is used, but two semiconductor chips to be laminated with higher accuracy are used. It is desirable to make fine adjustments between Cs. Therefore, it is preferable to use a lattice pattern formed by the blade grooves formed during dicing. Therefore, by aligning using the alignment mark, the alignment is performed with an accuracy smaller than the size of the semiconductor chip C, and then the alignment is performed using the grid pattern, so that highly accurate alignment can be achieved (chip transfer). (By the relative movement of the plate 1 and the temporary plate 2).
  • the chip transfer plate 1 is brought closer to the temporary placement plate 2 until the thermosetting adhesive layer R of the chip transfer plate 1 is brought into close contact with the semiconductor chip transferred to the temporary placement plate 2 (FIG. 9 (b). )).
  • the adhesive layer 11 of the chip transfer plate 1 is cured so as to exhibit peelability, and the support substrate 10 of the chip transfer plate 1 is separated from the temporary placement plate 2, so that the semiconductor chip C becomes as shown in FIG. 9C. It is temporarily fixed in a state of being laminated on the semiconductor chip C transferred to the temporary plate 2.
  • step SL41 in which the process chip stacking number n is 2 is completed, and step SL5 is determined.
  • step SL5 it is determined whether or not the number of chip stacks n to be laminated as the chip laminate LC has reached the number of chip stacks n to be laminated.
  • FIG. 10 shows a state in which a large number of chip laminates LC in which four layers of semiconductor chips C are laminated in a temporarily fixed state are arranged on the temporary plate 2 in a temporarily fixed state.
  • FIGS. 8 to 11 have been described on the premise that the chip transfer plate 1 has no defective chips in step SL3 of FIG. 7, but all of the large number of semiconductor chips C included in the chip transfer plate 1 are non-defective chips. It is rarely the case, and usually includes defective chips.
  • step SL3 of FIG. 7 the chip transfer plate has a defective chip”.
  • step SL3 it is possible to know which semiconductor chip C in the chip transfer plate 1 is a defective chip from the inspection information of the previous process. Therefore, if the semiconductor chip C marked with “NG” in FIG. 12A is a defective chip, the defective chip is removed from the chip transfer plate 1.
  • the adhesive layer 11 having photo-peelability is irradiated with spot light (including a wavelength that exhibits photo-peelability) such as a laser. Then, the defective chip is removed. In this way, in step SL40, all defective chips among the semiconductor chips C of the chip transfer plate 1 are removed.
  • step SL41 the semiconductor chip C is transferred in step SL41 using the chip transfer 1 from which the defective chip has been removed.
  • 12 (c) and 12 (d) show the same process as in FIGS. 9 (a) and 9 (b) described above in the case where the number of stacking process chips n is 2, but partially. The semiconductor chip C is missing.
  • step SL42 a non-defective semiconductor chip C is replenished at a location where the semiconductor chip C is missing in FIG. 12 (d).
  • FIG. 13 illustrates this step SL42.
  • FIG. 13A shows a state in which the chip holding means 5 separately prepares a semiconductor chip C (which has the same specifications as the semiconductor chip C of the chip transfer substrate 1 and is a good product), sucks and holds it, and conveys the chip C.
  • the chip holding means 5 aligns the non-defective semiconductor chip C on the lower semiconductor chip C at the position where the semiconductor chip C is missing on the temporary mounting plate 2. Deploy.
  • the chip holding means 5 releases the adsorption of the semiconductor chip C and rises, so that the state of the semiconductor chip C laminated on the temporary plate 2 is shown in FIG. 9 (c). It becomes the same as.
  • a large number of semiconductor chips C can be laminated at the same time by using the chip transfer plate 1, and defective chips are removed from the chip transfer plate 1 before being transferred (laminated). Therefore, defective chips do not enter in the process of laminating the semiconductor chips C.
  • a process for removing defective chips and replenishing non-defective products is required, but since the ratio of defective products to the semiconductor chip C is less than a few percent, steps SL40 and SL42 in FIG. 7 are shown. The effect on the tact time of the entire PL process is also small.
  • a large number of chip laminates LC laminated on the temporary mounting plate 2 in a temporarily fixed state as shown in FIG. 10 are temporarily crimped to a predetermined position on the wiring board in the PA process of FIG. 2, and then finally crimped in the PB process. And implemented. Therefore, the PA process and the PB process will also be briefly described with reference to the drawings.
  • FIG. 14 shows how the chip laminate holding means 6 picks up an arbitrary chip laminate LC from a large number of chip laminate LCs.
  • the semiconductor chip C in the uppermost layer of the chip laminate LC is sucked and held by the chip laminate holding means 6 and then ascended, and the chip laminate LC is picked up as shown in FIG. 14B.
  • the adhesive strength of the adhesive layer 21 (or the temporary substrate 20 when the adhesive layer 21 is absent) is compared with the adhesive strength of the (uncured) photocurable adhesive layer R.
  • the adhesion of the thermosetting adhesive layer R must be stronger. Therefore, the adhesive layer 21 may be made photo-peelable, and the adhesive layer 21 directly under the target chip laminate LC may be irradiated with spot light when picking up.
  • the chip laminate LC picked up as shown in FIG. 14 (b) moves while being held by the chip laminate holding means 6, and is temporarily crimped to a predetermined position in FIG. 15 (a) with a slight pressure. Be placed.
  • the predetermined position is a position where the bump electrode B of the semiconductor chip C in the lowermost layer of the chip laminate LC and the electrode E of the wiring board S are aligned vertically.
  • the chip laminate LC temporarily crimped to the wiring board S is mounted on the wiring board S by performing main crimping by heat crimping.
  • a plurality of the temporarily-bonded chip laminate LC may be thermocompression-bonded at the same time as shown in FIG. 16 (a) shows a state in which the main crimping head 7 for thermocompression-bonding a plurality of chip laminates LC at the same time is arranged on the chip laminate LC
  • FIG. 16 (b) shows the main crimp head 7 of the chip laminate LC. It is in the state where thermocompression bonding has started.
  • the semiconductor chips C are laminated and then thermocompression-bonded for mounting, so that the laminated semiconductor chips C are electrically connected to each other. That is, as shown in FIG. 17A, the semiconductor chip C has an electrode EC exposed from the bump electrode B via the through electrode V to the opposite surface of the bump electrode B, and heat is generated after the semiconductor chips C are laminated.
  • the bump electrode B of the semiconductor chip C in the lowermost layer is electrically connected to the electrode E of the wiring substrate S
  • the bump electrode B of the semiconductor chip C above the second layer is an electrode of the semiconductor chip C directly below. It will be in a state of being electrically connected to the EC.
  • the thermosetting adhesive layer R is cured by thermocompression bonding, the electrical connection formed during thermocompression bonding is fixed after mounting as shown in FIG. 17B.
  • the laminated semiconductor chips C are electrically connected to each other, and the chip laminate LC connected to the wiring board S is fixed on the wiring board S, but is separated and packaged together with the wiring board S. By doing so, it becomes a semiconductor device. Since the present invention is suitable for stacking semiconductor chips C having the same specifications, it is particularly suitable for manufacturing a semiconductor device such as a memory element whose capacity is increasing.
  • the productivity is extremely high, and since defective chips can be removed at the stage before lamination, the yield when obtaining the chip laminates is high, and the semiconductor device can be used. It can be said that it has both productivity and yield in manufacturing.
  • the adhesive layer 11 is made of a material whose peelability is improved by the generation of bubbles, and bubbles are generated only when light of a specific wavelength is irradiated. Therefore, even in the adhesive layer 11 which has been cured and whose adhesive strength has decreased, the semiconductor chip C is retained even though it has a weak adhesive strength unless it is irradiated with light having a specific wavelength.
  • FIG. 18 shows a state in which all the semiconductor chips C of the chip transfer plate 1 are transferred to the temporary placement plate 2.
  • the periphery of the chip transfer plate 1 is held by the substrate holding means 101, and the semiconductor chip C side is temporarily placed. Transfer from the state of facing the plate 2.
  • the support substrate 10 When the support substrate 10 is entirely irradiated with light of a specific wavelength as shown in FIG. 19A so as to simultaneously peel off all the semiconductor chips C during transfer, the peeling force is applied to all the semiconductor chips C. Therefore, if the substrate holding means 101 is moved vertically so as to move away from the temporary plate 2 at the same time as the light irradiation, the semiconductor chip C is transferred as shown in FIG. 19B, and there is no problem. However, if the entire surface of the support substrate 10 is to be irradiated with light that peels off the semiconductor chip C at the same time, a large light source is required.
  • FIG. 20A there is a method of sequentially peeling the semiconductor chip C while scanning a spot light source such as a laser.
  • a spot light source such as a laser.
  • the semiconductor chips C and the adhesive layer 11 are in close contact with each other. This makes it difficult to peel off all the semiconductor chips C from the adhesive layer 11. That is, in the step of transferring all the semiconductor chips C of the chip transfer plate 1, the effect of the bubbles generated at the interface by the light of a specific wavelength cannot be fully utilized.
  • the substrate holding means 101 is arranged inward from the semiconductor chip C arranged on the outer peripheral portion of the chip transfer plate 1 with a slight force applied in the direction away from the temporary plate 2.
  • the semiconductor chip C is sequentially irradiated with light (of a specific wavelength). That is, in FIG. 21A, after irradiating the semiconductor chip C arranged on the outermost periphery with spot light moving in the DR direction, the semiconductor chip C arranged on the inner side is sequentially moved in the direction of the semiconductor chip C (DC direction). It irradiates spot light moving in the DR direction and sequentially transfers the semiconductor chip C arranged on the outer peripheral portion of the chip transfer plate 1.
  • the adhesive layer 11 that has received the spot light is completely separated from the semiconductor chip C by the movement of the substrate holding means 101, so that the adhesive layer Re-adhesion between 11 and the semiconductor chip C can be avoided.
  • FIG. 22C by sequentially peeling the adhesive layer from the inner semiconductor chip C, all the semiconductor chips of the chip transfer plate 1 are used without applying a large force to the substrate holding means 101. It is possible to reliably transfer C.
  • Chip transfer plate Temporary mounting plate 4 Heating head 5 Chip holding means 6 Chip laminated body holding means 7 Crimping head 10 Support board 11 Adhesive layer 20 Temporary board 21 Adhesive layer 101 Board holding means B Bump electrode C Semiconductor chip E electrode (Electrodes on the wiring board) EC electrode (formed on the opposite side of the bump electrode forming surface of the semiconductor chip) LC chip laminate R Thermosetting adhesive film S Wiring board V Through silicon via W Semiconductor wafer

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Abstract

複数の半導体チップが仮固定状態で積層されたチップ積層体を得るのに好適なチップ転写板ならびに半導体チップ積層方法を提供し、生産性と歩留まりを両立させた半導体装置の製造方法を提供すること。具体的には、サポート基板と、サポート基板の片面に設けられた粘着層と、前記粘着層に保持され、前記粘着層に保持された面の反対側にバンプ電極を有する、多数の半導体チップと、前記半導体チップ個々のバンプ電極側に未硬化の熱硬化性接着層が設けられた、チップ転写板ならびにこれを用いた半導体チップ積層方法および半導体装置の製造方法を提供する。

Description

チップ転写板ならびに半導体チップ積層方法および半導体装置の製造方法
　本発明は多数の半導体チップを転写するチップ転写板ならびに半導体チップ積層方法および半導体装置の製造方法に関する。
　近年、半導体チップ同士を積層させて実装密度を高める技術が進んでいる。特許文献１には、複数の半導体チップを仮圧着状態で積層したチップ積層体としてから、一括して本圧着するようにして、半導体チップが高温に曝される回数を少なくした構成が記されている。また、複数の半導体チップを仮圧着状態で積層するのに際して、特許文献１ではボンディングツールが半導体チップ１つずつを仮圧着して積層する例が示されている。
特開２０１２－２２２０３８号公報 WO２０１６／１５８９３５号国際公開公報
　チップ積層体として本圧着することで、１回の本圧着により処理できる半導体チップの数が増しており、半導体チップ１つあたりの本圧着時間は短縮されることになる。昨今では、積層数が増すとともに、複数のチップ積層体を一括で本圧着することも可能となっており、本圧着工程で単位時間あたりに処理する半導体チップの数は飛躍的に増加している。
　これに対して、仮圧着工程において、ボンディングツールが半導体チップをピックアップして仮圧着するまでのタクトタイムを短縮するための種々の方策が採られている。しかし、本圧着工程で単位時間あたりに処理する半導体チップの数の増加に対して、仮圧着工程での改善は充分ではなく、１台の本圧着装置に対する仮圧着装置の台数が増していく状況である。
　そこで、特許文献２では、半導体ウェハ同士を仮固定状態で積層してからダイシングして、多数のチップ積層体を形成する手法が示されている。この特許文献２の手法では、積層を半導体ウェハレベルで行なっていることから、極めて生産性高くチップ積層体を得ることが出来る。このため、半導体ウェハ内における欠陥率がゼロであれば極めて有効な手法である。
　しかし、半導体ウェハ内に不良チップとなるような欠点が含まれている場合においては、不良チップを含むチップ積層体が生じ、積層数が多きなるほど不良チップを含むチップ積層体の発生率は上昇してしまう。
　半導体ウェハレベルにおいて欠陥箇所を掌握することは可能であるので、多数のチップ積層体のなかの何れの何層目が不良チップであるかを知ることが出来、仮固定状態であるので、不良チップを良品チップにリペアすることは可能である。しかし、このようなリペア作業を行なうことにより生産性は低下してしまう。また、不良チップを含むチップ積層体を廃棄するのであれば、多くの良品チップも廃棄することになり、製品歩留まりは大きく低下する。
　本発明は、上記問題を鑑みてなされたものであり、複数の半導体チップが仮固定状態で積層されたチップ積層体を得るのに好適なチップ転写板ならびに半導体チップ積層方法を提供し、生産性と歩留まりを両立させた半導体装置の製造方法を提供するものである。
　上記の課題を解決するために、請求項１に記載の発明は、サポート基板と、サポート基板の片面に設けられた粘着層と、前記粘着層に保持され、前記粘着層に保持された面の反対側にバンプ電極を有する、多数の半導体チップと、前記半導体チップ個々のバンプ電極側に未硬化の熱硬化性接着層が設けられた、チップ転写板である。
　請求項２に記載の発明は、請求項１に記載のチップ転写板であって、
バンプ電極が面上に配置された半導体ウェハを、粘着層を介してサポート基板に固定し、前記半導体ウェハの前記バンプ電極が形成された面に、未硬化の熱硬化性接着フィルムを貼り合わせた後に、前記熱硬化性接着フィルムが積層された前記半導体ウェハをダイシングして多数の半導体チップに個片化して形成したチップ転写板である。
　請求項３に記載の発明は、請求項１または請求項２に記載のチップ転写板であって、
前記粘着層が、特定の波長の光により粘着力が低下して半導体チップを剥離する、光剥離性を有し、前記サポート基板が、前記特定の波長の光に対して透過性を有するチップ転写板である。
　請求項４に記載の発明は、請求項３に記載のチップ転写板であって、
前記粘着層が、特定の波長の光によりガスを発生し、半導体チップとの界面で気泡化する特性を有するチップ転写板である。
　請求項５に記載の発明は、請求項１から請求項４の何れかに記載のチップ転写板であって、
サポート基板に保持された半導体チップのピッチおよび配列が、転写先のピッチおよび配列一致するチップ転写板である。
　請求項６に記載の発明は、請求項１から請求項５の何れかに記載のチップ転写板を用い、
前記チップ転写板の半導体チップを全て仮置板上に転写して仮固定し、仮固定した半導体チップ上に、前記チップ転写板を用いて、順次、半導体チップを位置合わせして転写して仮固定状態で積層し、前記仮置板上に多数の仮固定状態のチップ積層体を形成する半導体チップ積層方法である。
　請求項７に記載の発明は、請求項６に記載の半導体チップ積層方法であって、
前記チップ転写板の半導体チップを、仮置板上または仮固定した半導体チップ上に転写して仮固定する際に、前記チップ転写板の外周部に配置された半導体チップから転写を始め、順次内側に向けて転写を進める、半導体チップ積層方法である。
　請求項８に記載の発明は、請求項６または請求項７に記載の半導体チップ積層方法であって、
前記チップ転写板の半導体チップの中に不良品がある場合、前記不良品のみを前記チップ転写板から剥離してから、仮置板または仮置板上に仮固定した半導体チップ上に、前記チップ転写板により半導体チップを転写し、前記不良品を剥離したため半導体チップが転写されなかった箇所に、別に用意した良品の半導体チップを配置する半導体チップ積層方法
である。
　請求項９に記載の発明は、請求項６から請求項８の何れかに記載の半導体チップ積層方法によって得られた仮固定状態のチップ積層体を配線基板上に配置し、
前記チップ積層体を熱圧着して前記配線基板に実装する工程を備えた、半導体装置の製造方法である。
　本発明により、複数の半導体チップが仮固定状態で積層されたたチップ積層体を得るのに好適なチップ転写板ならびに半導体チップ積層方法が提供され、生産性と歩留まりを両立させた半導体装置の製造方法が実現する。
本発明の実施形態に係るチップ転写板の構成を示す図である。 本発明の実施形態に係るチップ転写板の形成から半導体装置の製造に至る概略フローを示す図である。 本発明の実施形態に係るチップ転写板を形成する過程を示す図である。 本発明の実施形態に係るチップ転写板を形成するのに用いる半導体ウェハがサポート基板に貼り合わされた状態を示し、（ａ）上面図、（ｂ）断面図、（ｃ）断面の拡大図である。 本発明の実施形態に係るチップ転写板を形成する途上で、半導体ウェハ上に熱硬化性接着フィルムを貼り合わせた状態を示し、（ａ）上面図、（ｂ）断面図、（ｃ）断面の拡大図である。 本発明の実施形態に係り、サポート基板上の半導体ウェハを熱硬化性接着フィルムとともにダイシングしてチップ転写基板とした状態を示し、（ａ）上面図、（ｂ）断面図、（ｃ）断面の拡大図である。 本発明の実施形態に係るチップ転写板を用いて、半導体チップを仮置板上に積層するフローを示す図である。 本発明の実施形態に係るチップ転写板を用いて、半導チップを仮置板上に転写する様子を説明するもので、（ａ）チップ転写板の半導体チップを仮置板と対向させた状態を示し、（ｂ）チップ転写板の半導体チップを仮置板と密着させて転写を行なう状態を示し、（ｃ）半導体チップが仮置板に転写された状態を示す図である。 本発明の実施形態に係るチップ転写板を用いて、半導チップを仮置板上に積層する様子を説明するもので、（ａ）仮置板上に転写された半導体チップとチップ転写板の半導体チップを位置合わせして対向させた状態を示し、（ｂ）チップ転写板の半導体チップを仮置板上に転写済みの半導体チップと密着させて転写を行なう状態を示し、（ｃ）半導体チップが仮置板に転写済みの半導体チップ上に転写された状態を示す図である。 本発明の実施形態に係る転写方法により、仮置板上に多数の仮固定状態のチップ積層体を形成した状態の一例（４層積層）を示す図である。 本発明の実施形態に係るチップ転写板から半導体チップを剥離させる手法について説明するもので、（ａ）光照射によって剥離する例を示し、（ｂ）加熱によって剥離する例を示すものである。 本発明の実施形態に係るチップ転写板が有する半導体チップに不良品が含まれる場合の対応を説明するものであり、（ａ）不良（ＮＧ）半導体チップを有するチップ転写板の例を示し、（ｂ）同チップ転写板から不良チップを剥離して除去する状態を示し、（ｃ）不良チップが除去されたチップ転写板を仮置板上に配置した状態を示し、（ｄ）同転写板を用いて仮置板（上の半導体チップ）に半導体チップを転写する状態を示す図である。 不良チップを除去した、本発明の実施形態に係るチップ転写板による仮置板（上の半導体チップ）への半導体チップの転写を行なった後の処置を説明するものであ、（ａ）別に用意した良品半導体チップを仮置板上の半導体チップ欠落箇所に配置する途上を示し、（ｂ）同欠落箇所に良品半導体チップを配置した状態を示し、（ｃ）仮置板上から半導体チップ欠落箇所がなくなった状態を示す図である。 仮置板上に形成された仮固定状態のチップ積層体のうち１つをピックアップする様子を説明するもので、（ａ）チップ積層体保持手段が最上層の半導体チップを保持した状態を示し、（ｂ）チップ積層体保持手段が仮固定状態のチップ積層体をピックアップした状態を示す図である。 チップ積層体を配線基板上に配置する様子を説明するもので、（ａ）仮置板からピックアップしたチップ積層体を最下層の半導体チップと配線基板の電極の位置を合わせて配置した状態を示し、（ｂ）チップ積層体を配線基板に仮圧着した状態を示し、（ｃ）配線基板の表面に複数のチップ積層体が仮圧着された状態を示す図である。 仮圧着されたチップ積層体を本圧着して配線基板に実装する様子を説明する図であり、（ａ）本圧着ヘッドが実装対象のチップ積層体上に位置している状態を示し、（ｂ）同チップ積層体を本圧着ヘッドで加熱圧着している状態を示す図である。 チップ積層体について説明するもので（ａ）チップ積層体を構成する半導体チップの断面図、（ｂ）チップ積層体を配線基板上に実装した状態を示す図である。 本発明のチップ転写板の全ての半導体チップを仮置板に転写する際の状態を示す図である。 本発明のチップ転写板の全ての半導体チップを仮置板に転写する工程の例を説明するもので、（ａ）全ての半導体チップに同時に光を照射する状態を示し、（ｂ）チップ転写板から全ての半導体チップが剥離して転写された状態を示す図である。 本発明のチップ転写板の全ての半導体チップを仮置板に転写する工程の別の例を説明するもので、（ａ）半導体チップに個別に光照射する状態を示し、（ｂ）半導体チップ個別に光照射した後の剥離の難さを示す図である。 半導体チップに個別に光照射する方式でも転写を確実に行なうプロセスについて説明するもので、（ａ）スポット光の移動方向を上面から示したものであり、（ｂ）同移動方向について断面図で示したものである。 半導体チップに個別に光照射する方式でも転写を確実に行なうプロセスの効果を説明するもので、（ａ）転写前の状態を示し、（ｂ）最外周部の半導体チップを転写する状態を示す、（ｃ）最外周の半導体チップ転写後に内側の半導体チップが転写できる状態を示す図である。
　本発明の実施形態について図面を用いて説明する。図１は本発明の実施形態に係るチップ転写板１の構成を示す断面図である。図２は本発明の実施形態に係る半導体装置の製造方法を説明する概略フロー図である。
　図１において、チップ転写板１は、サポート基板１０の表面に粘着層１１を介して、多数の半導体チップＣが配列された状態で保持されている。ここで、半導体チップＣには、粘着層１１と反対側にバンプ電極Ｂが形成されており、更に、バンプ電極Ｂを覆う熱硬化性接着層Ｒが設けられている。
　なお、本明細書において「接着層」と「粘着層」という用語を用いているが、原則的には「接着層」が最終的に接続された状態に固定するものに用いているのに対して、「粘着層」は最終的に剥離するものに対して用いている。
　図３はチップ転写板１を形成する工程（図２におけるＰＴ工程）を示す概略フローであり、概略フローの各ステップを説明するのが図４ないし図６である。
　図４は、図３におけるステップＳＴ０を説明するものであり、図４（ａ）は上面図、図４（ｂ）は断面図、図４（ｃ）は断面の部分的拡大図である。図４において半導体ウェハＷは、所謂半導体ウェハ処理工程により、面内に多数の半導体回路が形成されたものであり、半導体回路毎の所定箇所にバンプ電極Ｂを形成されたものである。ここで、半導体ウェハＷは直径が数十ｃｍあるのに対して厚みが５０μｍと非常に薄く、取り扱いが難しいため、粘着層１１を介してサポート基板１０に固定された状態でハンドリングされる。サポート基板１０は平面性に優れた材質が好ましく、具体的な材質としてはガラスやシリコンが好適である。また、粘着層１１は所定の波長の光を照射されることで硬化して（粘着力が低下し）剥離性を発現するものが好ましい。特に、特定の波長の光を照射されることでガスが発生し、界面に生じる気泡により剥離性を高めたものが製品化（例えば積水化学工業株式会社のＳＥＬＦＡ（登録商標））されており、このような特性を有するものを粘着層１１に用いることが更に好ましい。なお、バンプ電極Ｂの高さは１５～２０μｍである。
　図５は、図３におけるステップＳＴ１を説明するものであり、図５（ａ）は上面図、図５（ｂ）は断面図、図５（ｃ）は断面の部分的拡大図である。図５は、図４の状態のバンプＢ形成面に熱硬化性接着層Ｒを設けた状態を示すものである。ここで、熱硬化性接着層Ｒを設けるのに際して、ＮＣＦ（Ｎｏｎ　Ｃｏｎｄｕｃｔｉｖｅ　Ｆｉｌｍ）と呼ばれている熱硬化性接着フィルムを用いて、バンプ電極Ｂ形成面に貼り付けるのが好ましい。なお、熱硬化性接着フィルムの厚みは、バンプ電極Ｂの先端も覆うものを選ぶ。具体的には２０μｍ程度である。
　図６は、図３におけるステップＳＴ２を説明するものであり、図６（ａ）は上面図、図６（ｂ）は断面図、図６（ｃ）は断面の部分的拡大図である。図６は、バンプ電極Ｂ形成面に熱硬化性接着フィルムが貼られた状態の半導体ウェハＷをダイシングした状態を示すものであり、図１に構成を示したチップ転写板１が形成される。ここで、ダイシングは、ブレードダイシング等で、熱硬化性接着フィルムと半導体ウェハＷまで行なう。このため、所定ピッチのダイシングによって個片化された多数の半導体チップＣはサポート基板１０によって支持され、熱硬化性接着フィルムは個々の半導体チップＣ単位でバンプ電極Ｂ側に設けられた状態となる。
　ところで、図４のようにバンプ電極Ｂが形成された状態で、半導体ウェハＷ面内に形成された多数の半導体回路の動作チェックを行なって、動作不良の箇所を識別することが出来る。このため、図６のように個片化された多数の半導体チップＣのなかの何れが不良品（不良チップ）であるかという情報を後工程に引き継ぐことも出来る。
　次に、チップ転写板１を用いて、半導体チップＣを仮固定状態で積層したチップ積層体ＬＣを得る工程（図２に示すＰＬ工程）について説明する。図２に示したＰＬ工程は、図７に示すようにステップ分され、各ステップを図８ないし図１３を用いて説明する。
　ここで、図８から図１１までは、図７のステップＳＬ３においてチップ転写板１に不良チップがないことを前提としており、ステップＳＬ３からステップＳＬ４１に進むケースを説明する図である。
　図８（ａ）において、チップ転写１を仮置板２と対向させて用意した状態であり、図２のステップＳＬ４１の状態を示している。ここで、仮置板２はステップＳＬ１でステージ等に配置されるものであり、仮置基板２０の表面に光剥離性を有する粘着層２１が設けられたものである。粘着層２１なしも可能であるが、ある方が好ましく、粘着層１１と同様に、特定の波長の光を照射されること発生する気泡が剥離性を高める特性を有するものを用いることが更に好ましい。
　仮置板２は、チップ転写板１の全ての半導体チップＣを転写するだけの表面積を有しており、仮置基板２０としては平面性に優れたものが望ましい。また、仮置板１を配置するステージの表面も平面性に優れている必要がある。
　ステップＳＬ１で仮置板２を配置した段階で、仮置板２には何も載っておらず、１層目の半導体チップＣを転写することになるため、工程チップ積層数ｎは１となる。
　ステップＳＬ２ではチップ転写板１を用意し、前工程での検査情報よりステップＳＬ３でチップ転写板１に不良チップが無いことが判れば、ステップＳＬ４１でチップ転写板１の半導体チップＣを仮置板２に転写することになる。
　図８（ａ）では、チップ転写板１の半導体チップＣ側を仮置板２（粘着層２１がある場合は粘着層２１側）と対向させ、平行調整と位置合わせを行う。位置合わせは、チップ転写板１と仮置板２にそれぞれ設けられたアライメントマークを設けて、２視野カメラ等の画像認識手段を用いることが望ましい。
　次に、チップ転写板１を仮置板２の相対距離を、チップ転写板１の熱硬化性接着層Ｒが仮置板２に密着するまで接近させる（図８（ｂ））。その後、チップ転写板１の粘着層１１が剥離性を発現するように硬化させ、チップ転写板１のサポート基板１０を仮置板２から離せば、図８（ｃ）のように、未硬化の熱硬化性接着層Ｒが有する粘着性により半導体チップＣは仮置板２に転写され仮固定される。ところで、粘着層１１を硬化させる方法としては、粘着層１１が光硬化性の場合は、光硬化させる波長の光を図１１（ａ）のように照射すればよい。なお、粘着層１１に熱硬化性のものを用いて、図１１（ｂ）のように加熱ヘッド４により硬化させることも可能であるが、熱硬化性接着層Ｒが硬化開始しない温度で硬化するような材料を選ぶ必要がある。
　以上でステップＳＬ４１は完了し、ステップＳＬ５の判定を行なう。ステップＳＬ５において、チップ積層体ＬＣとして積層すべきチップ積層数Ｎに、工程チップ積層数ｎが達しているか判定する。ここで、図８（ｃ）に示すように工程チップ積層数ｎは１であるので、積層すべきチップ積層数Ｎが２以上であれば、工程チップ積層数ｎを２としてステップＳＬ２に進む。
　前述のとおり、図９においてもチップ転写板１に不良チップがないことを前提としており、ステップＳＬ３からステップＳＬ４１に進む。図９（ａ）は、新たに用意したチップ転写板１の半導体チップＣを仮置板２に転写された半導体チップＣと対向させ、平行調整と位置合わせを行う状態である。ここで、チップ転写板１の半導体チップCは所定のピッチでサポート基板１０上に配置されているので、新たに用意したチップ転写板１の半導体チップCと仮置板２に転写された半導体チップCとは、ピッチ及び配列が一致している。このため、半導体チップＣ毎に位置合わせを行うのではなく、チップ転写板１の位置を合わせることで、多数の半導体チップＣの上下位置が揃う。ところで、位置合わせは、チップ転写板１と仮置板２にそれぞれ設けられたアライメントマークを設けて、２視野カメラ等の画像認識手段を用いるが、更に高精度に積層対象となる２つの半導体チップＣ同士の微調整を行うことが望ましい。そのために、ダイシングの際に形成された刃溝による格子模様を利用するのが良い。そこで、アライメントマークを用いた位置合わせにより半導体チップＣのサイズより小さいレベルでの精度で位置合わせを行ってから、格子模様を用いて位置合わせを行う事で、高精度な位置合わせが（チップ転写板１と仮置板２の相対移動で）実現する。
　次に、チップ転写板１を仮置板２の相対距離を、チップ転写板１の熱硬化性接着層Ｒが仮置板２に転写された半導体チップに密着するまで接近させる（図９（ｂ））。その後、チップ転写板１の粘着層１１が剥離性を発現するように硬化させ、チップ転写板１のサポート基板１０を仮置板２から離せば、図９（ｃ）のように半導体チップＣは仮置板２に転写された半導体チップＣに積層された状態で仮固定される。
　以上で工程チップ積層数ｎが２におけるステップＳＬ４１は完了し、ステップＳＬ５の判定を行なう。ステップＳＬ５において、チップ積層体ＬＣとして積層すべきチップ積層数Ｎに、工程チップ積層数ｎが達しているか判定する。
　このようにして、工程チップ積層数が積層すべきチップ積層数ＮとなってステップＳＬ５の判定が行なわれるまで転写による積層が行なわれる。このため、積層すべきチップ積層数Ｎが４であれば、図１０に示した状態まで半導体チップＣの積層が進んだ段階でステップＳＬ５の判定を経てＰＬ工程は完了する。すなわち図１０は、４層の半導体チップＣが仮固定状態で積層されたチップ積層体ＬＣが、仮置板２に仮固定状態で多数配置された状態となっている。
　以上、図８から図１１までは、図７のステップＳＬ３においてチップ転写板１に不良チップがないことを前提として説明してきたが、チップ転写板１が有する多数の半導体チップＣの全てが良品チップであることは殆どなく、通常は不良チップが含まれる。
　そこで、以下、本実施形態のＰＬ工程において、チップ転写板１の半導体チップCに不良チップが含まれる場合の処理について説明する。すなわち、図７のステップＳＬ３で「チップ転写板に不良チップ有」となった場合である。
　ステップＳＬ３の段階で、前工程の検査情報から、チップ転写板１内の何処の半導体チップＣが不良チップであるか判る。そこで、図１２（ａ）で「ＮＧ」と記した半導体チップＣが不良チップであれば、チップ転写板１から不良チップを除去する。チップ転写板１から、不良チップを除去するのに際して、図１２（ｂ）の例では、光剥離性を有する粘着層１１にレーザー等のスポット光（光剥離性を発現する波長を含む）を照射して、不良チップを除去している。このように、ステップＳＬ４０では、チップ転写板１の半導体チップＣの内、全ての不良チップを除去する。
　この後、不良チップを除去したチップ転写１を用いて、ステップＳＬ４１で半導体チップＣの転写を行なう。図１２（ｃ）および図１２（ｄ）は、工程チップ積層数ｎが２の場合について、前述の図９（ａ）と図９（ｂ）と同じ過程を示すものであるが、部分的に半導体チップＣが欠落している。
　ところで、仮置板２に半導体チップＣを仮固定状態で転写しながら積層するのに際して、半導体チップＣが欠落した箇所の上には半導体チップＣを積層出来なくなる。そこで、図１２（ｄ）で半導体チップＣが欠落している箇所に、ステップＳＬ４２において、良品の半導体チップＣを補充するように配置する。このステップＳＬ４２を説明するのが図１３である。
　図１３（ａ）は、チップ保持手段５が、（チップ転写基板１の半導体チップＣと同仕様でかつ良品の）半導体チップＣを別に用意して、吸着保持して搬送する状態である。次に、図１３（ｂ）のように、チップ保持手段５は良品の半導体チップＣを、仮置板２上で半導体チップＣが欠落した箇所で、下層の半導体チップＣ上に位置合わせして配置する。その後、図１３（ｃ）のように、チップ保持手段５が半導体チップＣの吸着を解除して上昇することで、仮置板２に積層された半導体チップＣの状況は、図９（ｃ）と同様になる。
　このように、本発明では、チップ転写板１を用い、多数の半導体チップＣを同時に積層することが出来るとともに、不良チップはチップ転写板１から転写（積層）する前に除去される。このため、半導体チップＣを積層する過程で不良チップが入りこむことはなくなる。なお、不良チップを除去して、良品を補充するための工程が必要となるが、半導体チップＣに占める不良品の割合は数％にも満たないことから、図７のステップＳＬ４０とステップＳＬ４２がＰＬ工程全体のタクトタイムに及ぼす影響も小さい。
　図１０のように仮置板２上に仮固定状態で積層された多数のチップ積層体ＬＣは、図２のＰＡ工程で配線基板上の所定位置に仮圧着された後に、ＰＢ工程で本圧着され実装される。そこで、ＰＡ工程とＰＢ工程についても、図を用いて簡単に説明する。
　図１４および図１５は、ＰＡ工程について説明するものである。図１４は、多数のチップ積層体ＬＣの中から、チップ積層体保持手段６が任意のチップ積層体ＬＣをピックアップする様子を示したものである。図１４（ａ）のようにチップ積層体ＬＣの最上層の半導体チップＣをチップ積層体保持手段６が吸着保持してから上昇して、図１４（ｂ）のようにチップ積層体ＬＣをピックアップする。ここで、チップ積層体ＬＣをピックアップするためには、（未硬化の）光硬化性接着層Ｒの粘着力に比べて、粘着層２１の粘着力（粘着層２１がない場合は仮置基板２０と熱硬化性接着層Ｒの密着力）よりも強い必要がある。そこで、粘着層２１を光剥離性のものにして、ピックアップする際に対象のチップ積層体ＬＣ直下の粘着層２１にスポット光を照射してもよい。
　図１４（ｂ）のようにピックアップされたチップ積層体ＬＣは、チップ積層体保持手段６に保持された状態で移動し、図１５（ａ）の所定位置に、若干の圧力で仮圧着して配置される。ここで、所定位置とはチップ積層体ＬＣの最下層の半導体チップＣのバンプ電極Ｂと配線基板Ｓの電極Ｅが上下に揃った位置である。この後、チップ積層体保持手段６による吸着保持を解除し、仮置板２からチップ積層体ＬＣを順次ピックアップして、配線基板Ｓの実装箇所全てにチップ積層体ＬＣを仮圧着状態で配置する。
　配線基板Ｓに仮圧着されたチップ積層体ＬＣは加熱圧着による本圧着を行うことで、配線基板Ｓ上に実装される。仮圧着されたチップ積層体ＬＣを本圧着する際は、図１６のように複数を同時に熱圧着してもよい。図１６（ａ）は複数のチップ積層体ＬＣを同時に加熱圧着する本圧着ヘッド７をチップ積層体ＬＣの上に配置した状態で、図１６（ｂ）は本圧着ヘッド７がチップ積層体ＬＣの熱圧着を開始した状態である。
　ところで、半導体チップＣは積層してから熱圧着して実装することで積層した半導体チップＣ同士が電気的にも接続されるものである。すなわち、図１７（ａ）に示すように半導体チップＣはバンプ電極Ｂから貫通電極Ｖを経てバンプ電極Ｂの反対面に露出した電極ＥＣを有しており、半導体チップＣを積層してから熱圧着することで、最下層の半導体チップＣのバンプ電極Ｂが配線基板Ｓの電極Ｅと電気的に接続し、２層目より上の半導体チップＣのバンプ電極Ｂは直下の半導体チップＣの電極ＥＣと電気的に接続された状態となる。また、熱圧着により熱硬化性接着層Ｒが硬化するため、図１７（ｂ）のように熱圧着時に形成された電気的な接続は実装後に固定される。
　このように、積層された半導体チップＣ同士が電気的に接続され、配線基板Ｓに接続されたチップ積層体ＬＣは配線基板Ｓ上に固定されるが、配線基板Ｓとともに個片化やパッケージングすることで半導体装置となる。なお、本発明は同仕様の半導体チップＣを積層するのに適したものであることから、大容量化が進むメモリー素子のような半導体装置の製造に特に適している。
　本発明は、同時に多数のチップ積層体を形成できることから生産性が極めて高いとともに、積層前の段階で不良チップを除去することができるので、チップ積層体を得る際の
歩留まりも高く、半導体装置の製造において生産性と歩留まりを両立したものだと言える。
　ところで、ここまでの説明において、粘着層１１が特定の波長の光を照射されることで半導体チップＣを確実に剥離する例について説明した。これは、（特定の波長の光を照射されることで粘着力が低下するとともに）気泡発生により剥離性を高めた材質を粘着層１１として用いることにより容易に実現し得るものとなっている。
　しかし、気泡発生により剥離性を高めた材質を粘着層１１において、特定の波長の光を照射された時にしか気泡は発生しない。このため、硬化して粘着力が低下した粘着層１１でも、特定の波長の光を照射されていなければ半導体チップＣを弱い粘着力ながらも保持する。
　そこで、このような残存保持力の影響と対策に関して以下に記述するが、残存保持力の影響を考慮しなければならないのは、図８（ｂ）から図８（ｃ）および図９（ｂ）から図９（ｃ）に示す、チップ転写板１の全ての半導体チップＣを仮置板２または（仮置板２上に）仮固定した半導体チップＣ上に転写する段階である。
　チップ転写板１の全ての半導体チップＣを仮置板２に転写する際の状態を図１８に示すが、チップ転写板１は周囲を基板保持手段１０１で保持して、半導体チップＣ側を仮置板２に対向させた状態から転写する。
　転写に際して、全ての半導体チップＣを同時に剥離するように、図１９（ａ）のようにサポート基板１０に全面的に光を特定の波長の光を照射する場合、全ての半導体チップＣに剥離力が働くため、光照射と同時に仮置板２から遠ざかるように垂直に基板保持手段１０１を移動させれば、図１９（ｂ）のように半導体チップＣの転写が行なわれ問題ない。ところが、サポート基板１０全面に同時に、半導体チップＣを剥離させる光を照射しようとすると大型な光源が必要になる。
　このため、図２０（ａ）のように、レーザー等のスポット光源を走査しながら、半導体チップCを順次剥離させる方法がある。しかし、この方法で、全ての半導体チップCに光を照射してから、基板保持手段１０１を仮置板２から遠ざかるように垂直に移動させようとしても半導体チップCと粘着層１１が密着した状態になっており、全ての半導体チップCを粘着層１１から剥離するのが難しくなる。すなわち、チップ転写板１の全ての半導体チップＣを転写する工程では、特定の波長の光により界面に発生する気泡の効果を充分に活かすことができない。
　そこで、特定の波長の光により界面に発生する気泡の効果をスポット光源を用いても活かすための方法を模索した結果、新たな発明に至った。そのプロセスは、図２１のように、基板保持手段１０１を仮置板２から遠ざかる方向に僅かな力を加えた状態で、チップ転写板１の外周部に配置された半導体チップＣから内側に配置された半導体チップＣに、順次（特定の波長の）光を照射するというものである。すなわち、図２１（ａ）において、最外周に配置された半導体チップＣをＤＲ方向に移動するスポット光を照射した後に、内側に配置された半導体チップＣ方向（ＤＣ方向）に順次移動しながら、ＤＲ方向に移動するスポット光を照射して、チップ転写板１の外周部に配置された半導体チップＣから順次転写するものである。
　このようにすることで、図２２（ａ）から図２２（ｂ）に示すようにスポット光を受けた粘着層１１が、基板保持手段１０１の移動により半導体チップＣから完全に離れるため、粘着層１１と半導体チップＣの再密着が回避できる。以後、図２２（ｃ）のように、順次内側の半導体チップＣから粘着層が剥離するようにすることで、基板保持手段１０１に大きな力を加えることなく、チップ転写板１の全ての半導体チップＣを確実に転写することが可能となる。
　　１　　　チップ転写板
　　２　　　仮置板
　　４　　　加熱ヘッド
　　５　　　チップ保持手段
　　６　　　チップ積層体保持手段
　　７　　　本圧着ヘッド
　１０　　　サポート基板
　１１　　　粘着層
　２０　　　仮置基板
　２１　　　粘着層
１０１　　　基板保持手段
　　Ｂ　　　バンプ電極
　　Ｃ　　　半導体チップ
　　Ｅ　　　電極（配線基板上の電極）
　　ＥＣ　　電極（半導体チップのバンプ電極形成面の反対側に形成）
　　ＬＣ　　チップ積層体
　　Ｒ　　　熱硬化性接着フィルム
　　Ｓ　　　配線基板
　　Ｖ　　　貫通電極
　　Ｗ　　　半導体ウェハ

Claims (9)

  1. 　サポート基板と、サポート基板の片面に設けられた粘着層と、
    前記粘着層に保持され、前記粘着層に保持された面の反対側にバンプ電極を有する、多数の半導体チップと、
    前記半導体チップ個々のバンプ電極側に未硬化の熱硬化性接着層が設けられた、チップ転写板。
  2. 　請求項１に記載のチップ転写板であって、
    バンプ電極が面上に配置された半導体ウェハを、粘着層を介してサポート基板に固定し、
    前記半導体ウェハの前記バンプ電極が形成された面に、未硬化の熱硬化性接着フィルムを貼り合わせた後に、
    前記熱硬化性接着フィルムが積層された前記半導体ウェハをダイシングして多数の半導体チップに個片化して形成したチップ転写板。
  3. 　請求項１または請求項２に記載のチップ転写板であって、
    前記粘着層が、特定の波長の光により粘着力が低下して半導体チップを剥離する、光剥離性を有し、
    前記サポート基板が、前記特定の波長の光に対して透過性を有するチップ転写板。
  4. 　請求項３に記載のチップ転写板であって、
    前記粘着層が、特定の波長の光によりガスを発生し、半導体チップとの界面で気泡化する特性を有するチップ転写板。
  5. 　請求項１から請求項４の何れかに記載のチップ転写板であって、
    サポート基板に保持された半導体チップのピッチおよび配列が、
    転写先のピッチおよび配列一致するチップ転写板。
  6. 　請求項１から請求項５の何れかに記載のチップ転写板を用い、
    前記チップ転写板の半導体チップを全て仮置板上に転写して仮固定し、
    仮固定した半導体チップ上に、前記チップ転写板を用いて、順次、半導体チップを位置合わせして転写して仮固定状態で積層し、
    前記仮置板上に多数の仮固定状態のチップ積層体を形成する半導体チップ積層方法。
  7. 　請求項６に記載の半導体チップ積層方法であって、
    前記チップ転写板の半導体チップを、仮置板上または仮固定した半導体チップ上に転写して仮固定する際に、
    前記チップ転写板の外周部に配置された半導体チップから転写を始め、順次内側に向けて転写を進める、半導体チップ積層方法。
  8. 　請求項６または請求項７に記載の半導体チップ積層方法であって、
    前記チップ転写板の半導体チップの中に不良品がある場合、
    前記不良品のみを前記チップ転写板から剥離してから、仮置板または仮置板上に仮固定した半導体チップ上に、前記チップ転写板により半導体チップを転写し、
    前記不良品を剥離したため半導体チップが転写されなかった箇所に、別に用意した良品の半導体チップを配置する半導体チップ積層方法。
  9. 　請求項６から請求項８の何れかに記載の半導体チップ積層方法によって得られた仮固定状態のチップ積層体を配線基板上に配置し、
    前記チップ積層体を熱圧着して前記配線基板に実装する工程を備えた、半導体装置の製造方法。
PCT/JP2020/012204 2019-02-14 2020-03-19 チップ転写板ならびに半導体チップ積層方法および半導体装置の製造方法 WO2020196225A1 (ja)

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