JP4506767B2 - 半導体装置の製造方法 - Google Patents
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Description
請求項2に記載の発明に係る半導体装置の製造方法は、請求項1に記載の発明において、前記再配線上層絶縁膜の開口部内に再配線を形成する工程は、前記再配線上層絶縁膜の開口部内を含む前記再配線上層絶縁膜の上面全体に下地金属層を形成する工程と、前記下地金属層の上面に、再配線形成領域に対応する部分に開口部を有する再配線形成用メッキレジスト膜を形成する工程と、前記下地金属層をメッキ電流路とした電解メッキを行なうことにより前記再配線形成用メッキレジスト膜の開口部内において前記再配線上層絶縁膜の開口部内に形成された前記下地金属層の上面に上部金属層をその上面が前記再配線上層絶縁膜の上面と面一かそれよりも低くなるように形成する工程と、を含むことを特徴とするものである。
請求項3に記載の発明に係る半導体装置の製造方法は、請求項1に記載の発明において、前記柱状電極の周囲に封止膜を形成する工程を有することを特徴とするものである。
請求項4に記載の発明に係る半導体装置の製造方法は、請求項3に記載の発明において、前記柱状電極上に半田ボールを形成する工程を有することを特徴とするものである。
図1はこの発明の第1実施形態としての半導体装置の断面図を示す。この半導体装置は、CSPと呼ばれるもので、シリコン基板(半導体基板)1を備えている。シリコン基板1の上面には集積回路(図示せず)が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド2が集積回路に接続されて設けられている。
図12はこの発明の第2実施形態としての半導体装置の断面図を示す。この半導体装置において、図1に示す半導体装置と異なる点は、配線および上層絶縁膜を2層とした点である。すなわち、保護膜5の上面にはポリイミド系樹脂等からなる第1の上層絶縁膜(下面側上層絶縁膜)31aが設けられている。第1の上層絶縁膜31aの上面の第1の配線形成領域には開口部32が保護膜5の開口部6に連通されて設けられている。
図20はこの発明の第3実施形態としての半導体装置の断面図を示す。この半導体装置において、図12に示す半導体装置と異なる点は、柱状電極12が形成される第2の配線39の接続パッド部39bに対応する領域の第1の上層絶縁膜31aに開口部51を設け、該開口部51内にダミー下地金属層52およびその上に積層されたダミー上部金属層53からなるダミー接続パッド部54を島状に設けた点である。
2 接続パッド
3 絶縁膜
5 保護膜
7 上層絶縁膜
9 下地金属層
10 上部金属層
11 配線
12 柱状電極
13 封止膜
14 半田ボール
21 半導体ウエハ
23 上部金属層形成用メッキレジスト膜
25 柱状電極形成用メッキレジスト膜
Claims (4)
- 上面に複数の接続パッドを有する半導体基板上に、前記接続パッドに対応する部分に開口部を有する絶縁膜を形成する工程と、
前記絶縁膜の上面に、平面サイズが前記接続パッドの開口部より大きく、その膜厚全体に貫通し、且つ前記接続パッドの開口部に連通する第1の開口部を有する下面側上層絶縁膜を形成する工程と、
前記下面側上層絶縁膜の第1の開口部内に下面側配線をその上面が前記下面側上層絶縁膜の上面と面一かそれよりも低くなるように形成する工程と、
前記下面側上層絶縁膜および前記下面側配線の上面に、その膜厚全体に貫通し、且つ前記下面側配線の少なくとも一部に連通する第2の開口部を有する再配線上層絶縁膜を形成する工程と、
前記再配線上層絶縁膜の第2の開口部内に再配線をその上面が前記再配線上層絶縁膜の上面と面一かそれよりも低くなるように形成する工程と、
前記再配線の上面に、前記再配線の接続パッド部に対応する部分に開口部を有する柱状電極形成用メッキレジスト膜を形成する工程と、
前記柱状電極形成用メッキレジスト膜の開口部内の前記再配線の接続パッド部上面に柱状電極を形成する工程と、
前記柱状電極形成用メッキレジスト膜を剥離する工程と、
を含み、
一部の前記下面側配線は前記接続パッドに接続された接続部のみからなるように形成し、一部の前記再配線は残りの前記下面側配線の接続パッド部に接続された接続パッド部のみからなるように形成し、
前記下面側配線を形成する工程は、前記絶縁膜上において接続部のみからなる前記下面側配線に接続される前記再配線の接続パッド部下にダミー接続パッド部を島状に形成する工程を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の発明において、前記再配線上層絶縁膜の開口部内に再配線を形成する工程は、前記再配線上層絶縁膜の開口部内を含む前記再配線上層絶縁膜の上面全体に下地金属層を形成する工程と、前記下地金属層の上面に、再配線形成領域に対応する部分に開口部を有する再配線形成用メッキレジスト膜を形成する工程と、前記下地金属層をメッキ電流路とした電解メッキを行なうことにより前記再配線形成用メッキレジスト膜の開口部内において前記再配線上層絶縁膜の開口部内に形成された前記下地金属層の上面に上部金属層をその上面が前記再配線上層絶縁膜の上面と面一かそれよりも低くなるように形成する工程と、を含むことを特徴とする半導体装置の製造方法。
- 請求項1に記載の発明において、前記柱状電極の周囲に封止膜を形成する工程を有することを特徴とする半導体装置の製造方法。
- 請求項3に記載の発明において、前記柱状電極上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。
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JP2007050001A JP4506767B2 (ja) | 2007-02-28 | 2007-02-28 | 半導体装置の製造方法 |
TW097106543A TW200847369A (en) | 2007-02-28 | 2008-02-26 | Semiconductor device and manufacturing method thereof |
KR1020080017686A KR100931424B1 (ko) | 2007-02-28 | 2008-02-27 | 반도체장치 및 그 제조방법 |
CN2008100815219A CN101256994B (zh) | 2007-02-28 | 2008-02-28 | 半导体器件及其制造方法 |
US12/072,833 US20080203569A1 (en) | 2007-02-28 | 2008-02-28 | Semiconductor device and manufacturing method thereof |
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US7928574B2 (en) * | 2007-08-22 | 2011-04-19 | Texas Instruments Incorporated | Semiconductor package having buss-less substrate |
JP5536388B2 (ja) * | 2009-08-06 | 2014-07-02 | 株式会社テラプローブ | 半導体装置およびその製造方法 |
KR101701380B1 (ko) * | 2010-08-17 | 2017-02-01 | 해성디에스 주식회사 | 소자 내장형 연성회로기판 및 이의 제조방법 |
US10141288B2 (en) * | 2015-07-31 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface mount device/integrated passive device on package or device structure and methods of forming |
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- 2008-02-27 KR KR1020080017686A patent/KR100931424B1/ko not_active IP Right Cessation
- 2008-02-28 CN CN2008100815219A patent/CN101256994B/zh not_active Expired - Fee Related
- 2008-02-28 US US12/072,833 patent/US20080203569A1/en not_active Abandoned
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Also Published As
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KR20080080026A (ko) | 2008-09-02 |
KR100931424B1 (ko) | 2009-12-11 |
CN101256994A (zh) | 2008-09-03 |
CN101256994B (zh) | 2012-02-08 |
TW200847369A (en) | 2008-12-01 |
JP2008218494A (ja) | 2008-09-18 |
US20080203569A1 (en) | 2008-08-28 |
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